JPH0440271Y2 - - Google Patents
Info
- Publication number
- JPH0440271Y2 JPH0440271Y2 JP1982150194U JP15019482U JPH0440271Y2 JP H0440271 Y2 JPH0440271 Y2 JP H0440271Y2 JP 1982150194 U JP1982150194 U JP 1982150194U JP 15019482 U JP15019482 U JP 15019482U JP H0440271 Y2 JPH0440271 Y2 JP H0440271Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- resistor
- semiconductor substrate
- insulating layer
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15019482U JPS5954960U (ja) | 1982-10-02 | 1982-10-02 | 半導体装置の電極構造 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15019482U JPS5954960U (ja) | 1982-10-02 | 1982-10-02 | 半導体装置の電極構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5954960U JPS5954960U (ja) | 1984-04-10 |
| JPH0440271Y2 true JPH0440271Y2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1992-09-21 |
Family
ID=30333188
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15019482U Granted JPS5954960U (ja) | 1982-10-02 | 1982-10-02 | 半導体装置の電極構造 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5954960U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5756211B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1973-04-06 | 1982-11-29 | ||
| JPS5233261U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1975-08-29 | 1977-03-09 | ||
| JPS53110465A (en) * | 1977-03-09 | 1978-09-27 | Nec Corp | Semiconductor device |
-
1982
- 1982-10-02 JP JP15019482U patent/JPS5954960U/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5954960U (ja) | 1984-04-10 |