JPH0439760B2 - - Google Patents

Info

Publication number
JPH0439760B2
JPH0439760B2 JP5704187A JP5704187A JPH0439760B2 JP H0439760 B2 JPH0439760 B2 JP H0439760B2 JP 5704187 A JP5704187 A JP 5704187A JP 5704187 A JP5704187 A JP 5704187A JP H0439760 B2 JPH0439760 B2 JP H0439760B2
Authority
JP
Japan
Prior art keywords
data
memory cell
rom
memory
resistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP5704187A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6310399A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS6310399A publication Critical patent/JPS6310399A/ja
Publication of JPH0439760B2 publication Critical patent/JPH0439760B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
JP62057041A 1986-07-01 1987-03-13 複数個の読取専用メモリ・デ−タを記憶可能な読取／書込用記憶セル Granted JPS6310399A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/880,967 US4805142A (en) 1986-07-01 1986-07-01 Multiple ROM data state, read/write memory cell
US880967 1992-05-08

Publications (2)

Publication Number Publication Date
JPS6310399A JPS6310399A (ja) 1988-01-16
JPH0439760B2 true JPH0439760B2 (en:Method) 1992-06-30

Family

ID=25377507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62057041A Granted JPS6310399A (ja) 1986-07-01 1987-03-13 複数個の読取専用メモリ・デ−タを記憶可能な読取／書込用記憶セル

Country Status (4)

Country Link
US (1) US4805142A (en:Method)
EP (1) EP0250930B1 (en:Method)
JP (1) JPS6310399A (en:Method)
DE (1) DE3781336T2 (en:Method)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58186233A (ja) * 1982-04-23 1983-10-31 Oki Electric Ind Co Ltd トランスポンダ装置における電波返送方式
JPH03200089A (ja) * 1989-12-28 1991-09-02 Nippon Kouro Hiyoushiki Kyokai トランスポンダの応答データ検出方法
US7071060B1 (en) * 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US8199576B2 (en) * 2009-04-08 2012-06-12 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US7983065B2 (en) * 2009-04-08 2011-07-19 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof
US8547720B2 (en) 2010-06-08 2013-10-01 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541531A (en) * 1967-02-07 1970-11-17 Bell Telephone Labor Inc Semiconductive memory array wherein operating power is supplied via information paths
US3618052A (en) * 1969-12-05 1971-11-02 Cogar Corp Bistable memory with predetermined turn-on state
US4095281A (en) * 1976-03-04 1978-06-13 Rca Corporation Random access-erasable read only memory cell
US4134151A (en) * 1977-05-02 1979-01-09 Electronic Memories & Magnetics Corporation Single sense line memory cell
US4158239A (en) * 1977-12-20 1979-06-12 International Business Machines Corporation Resistive gate FET flip-flop storage cell
US4202044A (en) * 1978-06-13 1980-05-06 International Business Machines Corporation Quaternary FET read only memory
US4327424A (en) * 1980-07-17 1982-04-27 International Business Machines Corporation Read-only storage using enhancement-mode, depletion-mode or omitted gate field-effect transistors
US4462088A (en) * 1981-11-03 1984-07-24 International Business Machines Corporation Array design using a four state cell for double density
US4546453A (en) * 1982-06-22 1985-10-08 Motorola, Inc. Four-state ROM cell with increased differential between states
US4583201A (en) * 1983-09-08 1986-04-15 International Business Machines Corporation Resistor personalized memory device using a resistive gate fet

Also Published As

Publication number Publication date
DE3781336D1 (de) 1992-10-01
JPS6310399A (ja) 1988-01-16
DE3781336T2 (de) 1993-04-01
US4805142A (en) 1989-02-14
EP0250930B1 (en) 1992-08-26
EP0250930A3 (en) 1989-11-23
EP0250930A2 (en) 1988-01-07

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