JPH04354132A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04354132A JPH04354132A JP12806391A JP12806391A JPH04354132A JP H04354132 A JPH04354132 A JP H04354132A JP 12806391 A JP12806391 A JP 12806391A JP 12806391 A JP12806391 A JP 12806391A JP H04354132 A JPH04354132 A JP H04354132A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer wiring
- insulating film
- barrier metal
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 239000002184 metal Substances 0.000 claims abstract description 26
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 229910052782 aluminium Inorganic materials 0.000 abstract description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 47
- 239000010408 film Substances 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 239000010936 titanium Substances 0.000 description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 238000001459 lithography Methods 0.000 description 5
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910018523 Al—S Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05073—Single internal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は多層配線構造をなす半導
体装置の構造に関する。多層配線構造を有する半導体装
置の第一層配線の材料としては、アルミニウム（Ａｌ）
に１％程度のシリコン（Ｓｉ）を含有させた Ａｌ−Ｓ
ｉ合金が広く使用されて来た。これは、第一層配線に純
アルミニウムを使用すると、配線形成後のシリコン基板
の熱処理によりアルミニウムとシリコンのコンタクト部
でアルミニウムのスパイクが発生し、これがｐｎ接合を
破壊することがあるからである。ところが、 Ａｌ−Ｓ
ｉ合金を使用した場合には、シリコン基板の熱処理によ
りシリコンとのコンタクト部にシリコンがエピタキシア
ル成長し、コンタクト抵抗が増加する、という問題があ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device having a multilayer wiring structure. Aluminum (Al) is used as a material for the first layer wiring of a semiconductor device having a multilayer wiring structure.
Al-S containing about 1% silicon (Si)
i-alloys have been widely used. This is because when pure aluminum is used for the first layer wiring, heat treatment of the silicon substrate after wiring formation generates aluminum spikes at the contact portion between aluminum and silicon, which may destroy the pn junction. However, Al-S
When i-alloy is used, there is a problem in that heat treatment of the silicon substrate causes silicon to epitaxially grow in the contact area with silicon, increasing contact resistance.
【０００２】近年、半導体集積回路では高集積・高密度
化の要求に対応してパターンの微細化が進められ、コン
タクトホールの面積が小さくなって来たが、そのために
Ａｌ−Ｓｉ合金の配線の上記の問題点が無視出来なく
なり、最近ではこれを解決する手段として、アルミニウ
ムとシリコンとの間にバリアメタルを介在させることが
行われるようになって来た。このような目的のバリアメ
タルとして、Ｔｉ （チタン） ＋ＴｉＮ （窒化チタ
ン）が実用化されている（但し、バリアメタルとして主
として機能するのは ＴｉＮであり、 Ｔｉ はシリコ
ンとのコンタクト抵抗を下げるためのものである）。尚
、バリアメタルはストレス・マイグレーション対策とし
ても有効であることが知られている。In recent years, in response to demands for higher integration and higher density in semiconductor integrated circuits, patterns have become finer and the area of contact holes has become smaller. The above-mentioned problems can no longer be ignored, and recently, as a means to solve this problem, interposing a barrier metal between aluminum and silicon has been practiced. As a barrier metal for this purpose, Ti (titanium) + TiN (titanium nitride) has been put into practical use (however, it is TiN that primarily functions as a barrier metal, and Ti is used to lower the contact resistance with silicon. ). Note that barrier metal is known to be effective as a stress/migration countermeasure.
【０００３】0003
【従来の技術】多層配線構造をなし、コンタクトホール
部での配線と素子とのコンタクトの信頼性向上のために
第一層配線下側全面にバリアメタルを積層した半導体装
置の従来例を図を参照しながら説明する。図２は従来例
を示す断面図である。図において、図１と同じものには
同一の符号を付与した。１はシリコン基板、２は第一の
絶縁膜、３はバリアメタル、４は第一層配線、５は第二
の絶縁膜（層間絶縁膜）、６は第二層配線、７は第三の
絶縁膜（パッシペーション膜）、２１はボンディングパ
ッドである。[Prior Art] The figure below shows a conventional example of a semiconductor device that has a multilayer wiring structure and has a barrier metal layered all over the lower side of the first layer wiring in order to improve the reliability of the contact between the wiring and the element at the contact hole portion. I will explain while referring to it. FIG. 2 is a sectional view showing a conventional example. In the figure, the same parts as in FIG. 1 are given the same reference numerals. 1 is a silicon substrate, 2 is a first insulating film, 3 is a barrier metal, 4 is a first layer wiring, 5 is a second insulating film (interlayer insulation film), 6 is a second layer wiring, and 7 is a third layer wiring. An insulating film (passivation film) 21 is a bonding pad.
【０００４】第一の絶縁膜２は ＳｉＯ２ ＋ＰＳＧ（
燐ガラス）であり、バリアメタル３側がＰＳＧである。
バリアメタル３は第一層配線４下のみに存在し、 Ｔｉ
と ＴｉＮとが積層されており、第一の絶縁膜２側が
Ｔｉ 、第一層配線４側が ＴｉＮである。第一層配
線４及び第二層配線６はアルミニウム（又はアルミニウ
ム合金）である。ボンディングパッド２１は第二の絶縁
膜５と第三の絶縁膜７とを開孔して形成したものであり
、第一層配線４から引き出されている。ところで、バリ
アメタル３は第一層配線４と同時にパターニングされる
ものであるから、両者は同じパターンを有している。従
ってボンディングパッド２１の直下においても第一層配
線４と第一の絶縁膜２との間にこのバリアメタル３が存
在することになる。[0004] The first insulating film 2 is made of SiO2 +PSG (
(phosphorous glass), and the barrier metal 3 side is PSG. The barrier metal 3 exists only under the first layer wiring 4 and is made of Ti
and TiN are stacked, with Ti on the first insulating film 2 side and TiN on the first layer wiring 4 side. The first layer wiring 4 and the second layer wiring 6 are made of aluminum (or aluminum alloy). The bonding pad 21 is formed by opening holes in the second insulating film 5 and the third insulating film 7, and is drawn out from the first layer wiring 4. By the way, since the barrier metal 3 is patterned at the same time as the first layer wiring 4, both have the same pattern. Therefore, this barrier metal 3 exists between the first layer wiring 4 and the first insulating film 2 even directly under the bonding pad 21 .
【０００５】[0005]
【発明が解決しようとする課題】ところが、このような
、絶縁膜との間にバリアメタルが存在するボンディング
パッドのボンディング試験を行うと、バリアメタルが存
在しないボンディングパッドの場合より小さい力でボン
ディングパッドがバリアメタルの Ｔｉ と第一の絶縁
膜のＰＳＧとの界面で剥離する、という問題があった。However, when performing a bonding test on a bonding pad that has a barrier metal between it and the insulating film, it is found that the bonding force is lower than that for a bonding pad that does not have a barrier metal. There was a problem in that the barrier metal Ti was peeled off at the interface between the first insulating film PSG.
【０００６】本発明はこのような問題を解決して、コン
タクトホール部におけるコンタクトの信頼性とボンディ
ングの信頼性が共に高い半導体装置を提供することを目
的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a semiconductor device in which both contact reliability and bonding reliability in a contact hole portion are high.
【０００７】[0007]
【課題を解決するための手段】この目的は、本発明によ
れば、第一層配線４の下側全面にバリアメタル３を有し
、ボンディングパッド１１は第二層配線６又はそれより
上層の配線から引き出されていることを特徴とする半導
体装置とすることで、達成される。[Means for Solving the Problems] According to the present invention, the barrier metal 3 is provided on the entire lower side of the first layer wiring 4, and the bonding pad 11 is connected to the second layer wiring 6 or an upper layer. This can be achieved by providing a semiconductor device characterized by being drawn out from the wiring.
【０００８】[0008]
【作用】コンタクトホール部での配線と素子とのコンタ
クトの信頼性向上のために第一層配線の下側全面に Ｔ
ｉ ＋ ＴｉＮのバリアメタルを設けた場合、第一層配
線からボンディングパッドを引き出すと、ボンディング
パッドの下では Ｔｉ とＰＳＧが接することになる。
ＰＳＧとの密着性においては Ｔｉ はアルミニウム（
Ａｌ−Ｓｉ合金を含む）より劣るから、ボンディング
試験では低い力でボンディングパッドが剥離する。[Operation] In order to improve the reliability of the contact between the wiring and the element at the contact hole part, T is applied to the entire bottom surface of the first layer wiring.
When a barrier metal of i + TiN is provided, when the bonding pad is drawn out from the first layer wiring, Ti and PSG will be in contact with each other under the bonding pad. In terms of adhesion to PSG, Ti is aluminum (
(including Al-Si alloy), the bonding pad peels off with low force in the bonding test.
【０００９】一方、第二層より上層のアルミニウム配線
にはバリアメタルを設けないから、ボンディングパッド
を第二層より上層のアルミニウム配線から引き出せば、
第一層配線の下側全面に Ｔｉ ＋ ＴｉＮのバリアメ
タルが積層されていてもボンディングパッド下ではアル
ミニウムとＰＳＧが接しており、ボンディングパッドの
密着強度は低下することはなく、信頼性の高いボンディ
ングを得ることが出来る。On the other hand, since no barrier metal is provided on the aluminum wiring layer above the second layer, if the bonding pad is drawn out from the aluminum wiring layer above the second layer,
Even if the barrier metal of Ti + TiN is laminated on the entire lower side of the first layer wiring, the aluminum and PSG are in contact with each other under the bonding pad, so the adhesion strength of the bonding pad will not decrease, resulting in highly reliable bonding. can be obtained.
【００１０】0010
【実施例】本発明に基づく半導体装置の実施例を図を参
照しながら説明する。図１は本発明の実施例を示す断面
図である。図において、１はシリコン基板、２は第一の
絶縁膜、３はバリアメタル、４は第一層配線、５は第二
の絶縁膜、６は第二層配線、７は第三の絶縁膜、１１は
ボンディングパッド、１２はスルーホールである。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device according to the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a first insulating film, 3 is a barrier metal, 4 is a first layer wiring, 5 is a second insulating film, 6 is a second layer wiring, and 7 is a third insulating film. , 11 is a bonding pad, and 12 is a through hole.
【００１１】第一の絶縁膜２は ＳｉＯ２ とＰＳＧの
二層構造（シリコン基板１側が ＳｉＯ２ ）である。
バリアメタル３は第一層配線４直下のみに存在し、Ｔｉ
（厚さ ２００Å程度）と ＴｉＮ （厚さ１０００
Å程度） との二層構造（第一の絶縁膜２側が Ｔｉ
）である。第一層配線４は Ａｌ 又は Ａｌ 合金か
らなる。第二の絶縁膜５は層間絶縁膜であり、ＰＳＧか
らなる。第二層配線６は Ａｌからなる。第三の絶縁膜
７はパッシペーション膜であり、ＰＳＧからなる。The first insulating film 2 has a two-layer structure of SiO2 and PSG (SiO2 on the silicon substrate 1 side). The barrier metal 3 exists only directly under the first layer wiring 4, and the Ti
(thickness about 200 Å) and TiN (thickness 1000 Å
Ti
). The first layer wiring 4 is made of Al or Al alloy. The second insulating film 5 is an interlayer insulating film and is made of PSG. The second layer wiring 6 is made of Al. The third insulating film 7 is a passivation film and is made of PSG.
【００１２】ボンディングパッド１１は第二層配線６上
の第三の絶縁膜７を開口して形成したものであり、第二
層配線６から引き出されているから直下にバリアメタル
３は存在しない。スルーホール１２は第二の絶縁膜５を
開口して形成したものであり、第二層配線６の材料が充
填されて第二層配線６と第一層配線４とを電気的に接続
している。The bonding pad 11 is formed by opening the third insulating film 7 on the second layer wiring 6, and since it is drawn out from the second layer wiring 6, there is no barrier metal 3 directly below. The through hole 12 is formed by opening the second insulating film 5, and is filled with the material of the second layer wiring 6 to electrically connect the second layer wiring 6 and the first layer wiring 4. There is.
【００１３】この様な構造の半導体装置は次のようにし
て得られる。先ず拡散層を形成したシリコン基板１の表
面全面にＣＶＤ法により ＳｉＯ２ とＰＳＧとをこの
順に被着して第一の絶縁膜２を形成する。次にこの第一
の絶縁膜２の所定の位置にリソグラフィ法によりコンタ
クトホールを開孔してシリコン基板１の拡散層を露出さ
せる（図示は省略）。その後スパッタリング法により、
上記コンタクトホールを含む全面に Ｔｉ と ＴｉＮ
とを連続して被着する。この上に更に Ａｌ 又は Ａ
ｌ 合金をスパッタリング法により被着する。その後こ
の Ｔｉ ＋ ＴｉＮ＋ Ａｌ 又はＡｌ 合金の三層
の金属薄膜をリソグラフィ法により同時にパターニング
して、同一パターンのバリアメタル３と第一層配線４と
を形成する。A semiconductor device having such a structure can be obtained as follows. First, a first insulating film 2 is formed by depositing SiO2 and PSG in this order on the entire surface of a silicon substrate 1 on which a diffusion layer has been formed by CVD. Next, a contact hole is opened at a predetermined position in the first insulating film 2 by lithography to expose the diffusion layer of the silicon substrate 1 (not shown). Then, by sputtering method,
Ti and TiN are applied to the entire surface including the above contact hole.
and are applied continuously. On top of this, Al or A
l The alloy is deposited by sputtering. Thereafter, the three-layer metal thin film of Ti+TiN+Al or Al alloy is simultaneously patterned by lithography to form barrier metal 3 and first layer wiring 4 of the same pattern.
【００１４】次に全面にＣＶＤ法によりＰＳＧを被着し
て第二の絶縁膜５を形成した後、この第二の絶縁膜５の
所定の位置にリソグラフィ法によりスルーホール１２を
開孔して第一層配線４の一部を露出させる。次にこのス
ルーホール１２を含む全面に Ａｌをスパッタリング法
により被着し、これをリソグラフィ法によりパターニン
グして第二層配線６を形成する。次にＣＶＤ法によりＰ
ＳＧを被着して第三の絶縁膜７を形成した後、この第三
の絶縁膜７の所定の位置をリソグラフィ法により開孔し
て第二層配線６の一部を露出させ、ボンディングパッド
１１を形成する。Next, after depositing PSG on the entire surface by CVD to form a second insulating film 5, through holes 12 are opened at predetermined positions in the second insulating film 5 by lithography. A part of the first layer wiring 4 is exposed. Next, Al is deposited on the entire surface including the through hole 12 by sputtering, and is patterned by lithography to form the second layer wiring 6. Next, by CVD method, P
After depositing SG to form the third insulating film 7, a hole is opened at a predetermined position in the third insulating film 7 by lithography to expose a part of the second layer wiring 6, and a bonding pad is formed. 11 is formed.
【００１５】このようにして得た半導体装置のボンディ
ングパッド１１のボンディング試験を行った結果、ボン
ディングパッドの密着強度は従来例におけるボンディン
グパッド（図２の２１） の場合の約二倍の値が得られ
た。As a result of conducting a bonding test on the bonding pad 11 of the semiconductor device thus obtained, the adhesion strength of the bonding pad was approximately twice that of the conventional bonding pad (21 in FIG. 2). It was done.
【００１６】本発明は以上の実施例に限定されることな
く、更に種々変形して実施することが出来る。例えば三
層配線構造をなす半導体装置における第三層配線からボ
ンディングパッドを引き出す場合であっても、又、バリ
アメタルがＴｉ ＋ＴｉＮ 以外であっても、本発明は
有効である。The present invention is not limited to the above embodiments, but can be implemented with various modifications. For example, the present invention is effective even when a bonding pad is drawn out from the third layer wiring in a semiconductor device having a three-layer wiring structure, or even when the barrier metal is other than Ti + TiN.
【００１７】[0017]
【発明の効果】以上説明したように、本発明によれば、
コンタクトホール部におけるコンタクトの信頼性とボン
ディングの信頼性が共に高い半導体装置を提供すること
が出来、半導体装置の信頼性向上に寄与する。[Effects of the Invention] As explained above, according to the present invention,
It is possible to provide a semiconductor device in which both contact reliability and bonding reliability in the contact hole portion are high, contributing to improved reliability of the semiconductor device.
【図１】 本発明の実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】 従来例を示す断面図である。FIG. 2 is a sectional view showing a conventional example.
１ シリコン基板
２ 第一の絶縁膜
３ バリアメタル
４ 第一層配線（第一層アルミニウム配線）５ 第
二の絶縁膜
６ 第二層配線（第二層アルミニウム配線）７ 第
三の絶縁膜
１１， ２１ ボンディングパッド
１２ スルーホール1 Silicon substrate 2 First insulating film 3 Barrier metal 4 First layer wiring (first layer aluminum wiring) 5 Second insulating film 6 Second layer wiring (second layer aluminum wiring) 7 Third insulating film 11, 21 Bonding pad 12 Through hole
Claims (1)
アメタル（３） を有し、ボンディングパッド（１１）
は第二層配線（６） 又はそれより上層の配線から引き
出されていることを特徴とする半導体装置。Claim 1: A barrier metal (3) is provided on the entire lower side of the first layer wiring (4), and a bonding pad (11) is provided.
A semiconductor device characterized in that the second layer wiring (6) is drawn out from the second layer wiring (6) or from the wiring in an upper layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12806391A JPH04354132A (en) | 1991-05-31 | 1991-05-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12806391A JPH04354132A (en) | 1991-05-31 | 1991-05-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04354132A true JPH04354132A (en) | 1992-12-08 |
Family
ID=14975555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12806391A Withdrawn JPH04354132A (en) | 1991-05-31 | 1991-05-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04354132A (en) |
-
1991
- 1991-05-31 JP JP12806391A patent/JPH04354132A/en not_active Withdrawn
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|---|---|---|---|
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