JPH04345224A - Alarm signal detection circuit - Google Patents

Abstract

PURPOSE:To allow the detection circuit to easily cope with revision of alarm release condition without increasing the circuit scale even when the alarm release condition is revised with respect to the alarm signal detection circuit detecting publication and release of an alarm from a data signal sent via a transmission line. CONSTITUTION:An arithmetic section 101 outputs 0 when a data signal and a clock signal are logical 1 and outputs 1 in other cases. An integration section 102 repetitively integrates number of is outputted by the arithmetic section 101 for each prescribed period. A comparator section 103 outputs a level 1 (alarm publication) when the result of integration of the integration section 102 reaches a reference value or over and outputs a level 0 (alarm release) when the result of integration is less than the reference value. Then a setting section 104 sets the said reference value to an optional value. That is, the result of integration by the integration section 102 is (n-k) when levels of is of the data signal change into 0 for a prescribed period with respect to a clock signal in which is and 0s are repeated for n-times only for the said period. Thus, the comparator 103 compares the value (n-k) with a reference value S and outputs alarm publication when the value (n-k) is the reference value S or over and outputs alarm release when the value (n-k) is less than the reference value S.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an alarm signal detection circuit for detecting the issuance and release of an alarm from data signals transmitted via a transmission line.

0002

2. Description of the Related Art Conventionally, this type of alarm signal detection circuit receives data transmitted via a transmission line, and when the signal is 1 continuously for a predetermined period, it is determined to be an alarm signal, so-called AIS signal. However, there is also known a system in which it is determined that the alarm has been canceled when the number changes from 1 to 0 by a reference number of times during a predetermined period.

0003

[Problem to be Solved by the Invention] However, in such a conventional alarm detection circuit, the conditions for alarm cancellation,
That is, when the reference number of times a signal changes from 1 to 0 during a predetermined period is changed, there is a problem in that it is difficult to easily respond to the change.

[0004] The present invention has been made in consideration of the above circumstances, and provides an alarm detection circuit that can easily respond to changes in the conditions for canceling the alarm without increasing the circuit scale. It is something.

[0005]

[Means for Solving the Problems] As shown in FIG. 1, the present invention determines that a received data signal is an alarm signal when it is 1 continuously for a predetermined period, and An alarm signal detection circuit configured to determine that it is an alarm release signal when it changes from 1 to 0 receives a data signal and a clock signal and outputs 0 when the data signal is 1 and the clock signal is 1. However, in other states, there is an arithmetic unit 101 that outputs 1, and an integration unit 1 that repeatedly adds up the number of 1s output by the arithmetic unit 101 at predetermined intervals.
02, a comparison unit 103 that outputs 1 when the integration result of the integration unit 102 exceeds a reference value, and outputs 0 when it becomes less than the reference value, and a setting unit 104 that arbitrarily sets the reference value. The present invention provides an alarm signal detection circuit characterized by the following.

[0006]

[Operation] In FIG. 1, the arithmetic unit 101 outputs 0 when the data signal and the clock signal are in the 1 state, and outputs 1 in other states. The integration unit 102 is the calculation unit 101
The number of 1's output by is repeatedly integrated at predetermined intervals. Comparison unit 103 outputs 1 (alarm issue) when the integration result of integration unit 102 exceeds the reference value, and outputs 0 when it becomes less than the reference value.
Outputs (alarm release). Then, the setting unit 104 arbitrarily sets the reference value.

In other words, for a clock that repeats 1 and 0 n times during a predetermined period, the data signal repeats k times during the same period.
When the value changes from 1 to 0 by the number of times, the integration result of the integration unit 102 becomes (n−k). Therefore, the comparison unit 103 calculates (n−
k) and a reference value S, and if (n-k) is greater than or equal to S, an alarm is issued, and if (n-k) is less than S, an alarm is issued.

Note that this reference value S can be arbitrarily set in the setting section 104, so that even if the alarm release condition, that is, k changes, it can be easily accommodated.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on embodiments shown in the drawings. This invention is not limited by this.

FIG. 2 is a block diagram showing an embodiment of the present invention. Roughly divided, 101 receives a data signal and a clock signal, and the data signal is 1 ("H" in this embodiment).
, and outputs 0 ("L" in this embodiment) when the clock signal is in the state of 1 ("H"), and outputs 1 ("H") in other states. Also, 102
103 is an integration unit that repeatedly integrates the number of 1 (“H”) output from the calculation unit 101 at predetermined intervals, and 103 outputs 1 (“H”) when the integration result of the integration unit exceeds a reference value. ,
This is a comparison unit that outputs 0 (“L”) when the value is less than the reference value. Furthermore, 104 is a setting unit that arbitrarily sets the reference value.

The arithmetic unit 101 is composed of a NAND gate that receives a clock signal A and a data signal B and outputs a signal C. The integration unit 102 includes a 32-decimal counter 2, a RAM 3,
E-OR gate 4, increment circuit 5, selector 6
and a buffer 7. Further, the comparison section 103 includes a compare circuit 8 and a flip-flop 9.

The counter 2 determines the address of the RAM 3 based on the output S1, and the RAM 3 writes and reads data S2 to the address instructed by the counter 2. The increment circuit 5 performs an operation of adding "1" to the data S2 read from the RAM 3. The buffer 7 is controlled by the output C of the NAND gate 1, and opens its gate when writing to the RAM 3, and transfers the output of the increment circuit 5 to the RAM 3. OR gate 4 and selector 6
generates data "00" which the RAM 3 writes to the address specified by the count 2 as an initial value. The compare circuit 8 compares the data S2 with a reference value ("30" in this embodiment) arbitrarily set by the setting section 104, and the flip-flop 9 latches the comparison result and outputs it as a signal D.

The operation in such a configuration will be explained using the time chart shown in FIG. First, in the period T1, the data signal B is always "H" with respect to the clock signal A from 1 to 32, so when the counter 2 outputs the output signal S1 from "00" to "31", Sequential data “00” to the corresponding ROM3 address
Writing and reading of "31" is performed. The finally read data "31" is compared with the reference value "30" set by the setting unit 104 in the compare circuit 8, and in this case, the read data "31" is larger than the reference value. Therefore, the compare circuit 8 outputs "H" (alarm), which is latched by the flip-flop 9, and "H" is output as the signal D during the period T2.

Next, in period T2, when the data signal B changes from "H" to "L" twice, the NAND gate 1
The number of times the buffer 7 is opened is reduced by two in response to the output C of the buffer 7. Therefore, the data S2 that is sequentially written and read from the address of RAM3 is "00" to "29", and the finally read data "29" is the reference value "
30”. In this case, the read data “
Since "29" is smaller than the reference value "30", the compare circuit 8 outputs "L" (alarm release), and the flip-flop 9 latches it in the period T3.

[0015] In this embodiment, the alarm release condition is set to 32.
The data signal changes from “H” to “” twice during the period of the clock signal.
The reference value set by the setting section 104 was set to "30" assuming that the alarm would change to "L". However, if the alarm release condition is different from this, it is easy to change the reference value of the setting section 104. Furthermore, since the main components of the integration section are a counter and a RAM, the overall circuit scale is reduced.

[0016]

According to the present invention, the conditions for canceling the alarm signal can be arbitrarily set, and the circuit can be miniaturized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

[Explanation of symbols]

101 Arithmetic unit 102 Integration section 103 Comparison section 104 Setting section 1 NAND gate 2 Counter 3 RAM 4 OR gate 5 Increment circuit 6 Selector 7 Buffer 8 Compare circuit 9 Flip-flop

Claims (1)

[Claims] [Claim 1] A received data signal is transmitted during a predetermined period of time.
In an alarm signal detection circuit configured to determine that it is an alarm signal when it is 1 continuously, and to determine that it is an alarm release signal when it changes from 1 to 0 a predetermined number of times, the data signal and the clock signal are The data signal is 1
and an arithmetic unit (101) that outputs 0 when the clock signal is 1 and outputs 1 in other states, and repeatedly adds up the number of 1s output by the arithmetic unit (101) at predetermined intervals. an integration section (102); a comparison section (103) that outputs 1 when the integration result of the integration section (102) is equal to or greater than a reference value; and a comparison section (103) that outputs 0 when the integration result is less than the reference value; and arbitrarily sets the reference value. An alarm signal detection circuit characterized in that it includes a setting section (104).