JPS61145655A - Slave error supervisory device - Google Patents

Slave error supervisory device

Info

Publication number
JPS61145655A
JPS61145655A JP59267644A JP26764484A JPS61145655A JP S61145655 A JPS61145655 A JP S61145655A JP 59267644 A JP59267644 A JP 59267644A JP 26764484 A JP26764484 A JP 26764484A JP S61145655 A JPS61145655 A JP S61145655A
Authority
JP
Japan
Prior art keywords
slave
signal
output
response signal
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59267644A
Other languages
Japanese (ja)
Inventor
Shigeo Suzuki
重雄 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP59267644A priority Critical patent/JPS61145655A/en
Publication of JPS61145655A publication Critical patent/JPS61145655A/en
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To detect slave runaway to the utmost by utilizing an existing watchdog timer or the like for runaway detection of a master itself so as to use an logic circuit only for slave runaway detection independently of number of slaves. CONSTITUTION:When a slave SL is in the normal operation, both a slave error signal E being an output of an AND gate G10 and a slave error signal D being an output of an AND gate G11 remain logical L and then a slave error signal C always remains logical L. The slave error operation is whether any slave SL does not output a response signal RP, outputs a response signal or intermit the response signal. When no response signal RP is outputted, that is, a response signal RPN of the final slave SLN is not outputted as logical H, a supervisory signal B remains logical H and not reset, and when the next supervisory trigger signal A is outputted as logical H, the error signal D goes to H by the gate G11 and then the error signal C goes to logical H.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 この発明はマスタＣＰＵ（以後マスタと呼ぶ）と、マス
タから否にコントロールできない複数のスレーブＣＰＵ
（以俊スレーブと呼ぶ）とを備えたマイクロコンピュー
タシステム−こおけるスレーブの異常の監視Ｖｉ、置夛
こ関する。[Detailed description of the invention] [Technical field to which the invention pertains] This invention relates to a master CPU (hereinafter referred to as master) and a plurality of slave CPUs that cannot be controlled by the master.
A microcomputer system equipped with a microcomputer system (referred to as a slave) (hereinafter referred to as a "slave") relates to the monitoring of abnormalities in a slave (Vi and its installation).

〔従来技術とその曲謳点〕[Prior art and its highlights]

以下各図の説明をこおいて同一の符号は同−又は相当部
分を示す。In the following description of each figure, the same reference numerals indicate the same or corresponding parts.

従来この種の監視方式としては第６図のようｔＣ。A conventional monitoring system of this type is tC as shown in FIG.

スレーブＳＬ’（ＳＬ１〜ＳＬりの各々にウォッチＯド
ッグ・タイマＷＤ（ＷＤ１〜ＷＤ！１）を付し、　マス
タＭはウォッチドッグタイマＷＤの何れかのオーバーフ
ロー信号を、オアゲートＧｌを通して一括入力し１．ス
レーブ８Ｌの何れかの異常を知る方式が知られている。A watch O-dog timer WD (WD1 to WD!1) is attached to each of the slaves SL' (SL1 to SL), and the master M inputs the overflow signal of any of the watchdog timers WD at once through the OR gate Gl. .A method for detecting an abnormality in any of the slaves 8L is known.

ところがこの方式ではスレーブ８Ｌの数だけウォッチ・
ドッグ・タイマＷＤが必要となる。またスレーブの暴走
の仕方暑ζよりては、当該のスレーブか、対応するウォ
ッチ・ドッグ響タイマに対し、常時リセット信号を出力
したままになったり、あるいはやたら膠こリセット信号
をオン／オフしたりすることもあり、このような場合は
ウォッチ・ドッグ・・タイマがオーバーフローしないた
め、マスタはそのスレーブの暴走を検知できない、など
という問題点がある。However, with this method, the number of watch
A dog timer WD is required. In addition, depending on how the slave goes out of control, the reset signal may be constantly output to the slave or the corresponding watchdog timer, or the reset signal may be turned on/off excessively. In such cases, the watch dog timer does not overflow, so there is a problem that the master cannot detect the slave's runaway.

〔発明の目的〕[Purpose of the invention]

この発明は前記の欠点を除きスレーブの数には無関係に
、スレーブ暴走検知のためのロジック回路を一つにして
回路構成を簡単化し１、しかもスレーブの暴走を極力検
知できるような信頼性の高いスレーブ監視装置を提供す
ることを目的とする。This invention has the advantage of simplifying the circuit configuration by integrating the logic circuit for detecting slave runaway, regardless of the number of slaves, except for the above-mentioned drawbacks. The purpose is to provide a slave monitoring device.

〔発明の要点〕[Key points of the invention]

この発明の要点は、マスタＣＰＵ（以下マスタという）
及び複数のスレーブＣＰＵ（以下スレーブという）を備
え、スレーブの何ｎかの異常をマスタが検知するスレー
ブ異常監視装置曇ζおいて。The main point of this invention is that the master CPU (hereinafter referred to as master)
and a plurality of slave CPUs (hereinafter referred to as slaves), and a slave abnormality monitoring device (hereinafter referred to as "slave") in which a master detects abnormalities of a number of slaves.

繰返し、監視トリガ信号を出力する手段（マスタ憂ζ属
するウォッチ−ドッグ・タイマ（図外）など）と、該監
視トリガ信号をラッチし監視信号として出力するラッチ
手段（フリップ・フロップなど）と、各スレーブに対応
して設けられ、当該のスレーブが入力した応答信号を、
該スレーブから新たな応答信号として出力させる手段（
各スレーブに属する入出力回路、ＲＯＭ（図外）など）
とを設け、 前記入、出力の応答信号を順次授受するように前記スレ
ーブを縦続に接続し、前記監視信号を前記縦続接続の一
端のスレーブに前記入力の応答信号として与え、同じく
他端のスレーブから出力される前記応答信号（以下最終
スレーブ応答信号という）を前記ラッチ手段に与えて前
記監視信号のラッチ出力を消滅させるよう一ζ構成する
とともに、前記のラッチされた監視信号の存続中に前記
監視トリガ信号が出力さｎることを判別する第１の判別
手段（アンドゲートなど）と、 前記監視信号の消滅中に前記最終スレーブ応答信号が出
力されたことを判別する第２の判別手段（アンドゲート
など）と、前記第１又は第２の判別手段の判別信号をマ
スタに与える手段（オアゲートなど）とを備えるように
した点ｔこある。A means for repeatedly outputting a monitoring trigger signal (such as a watchdog timer (not shown) belonging to the master alarm), a latching means (such as a flip-flop) for latching the monitoring trigger signal and outputting it as a monitoring signal, and It is provided corresponding to the slave, and receives the response signal input by the slave.
Means for outputting a new response signal from the slave (
Input/output circuits belonging to each slave, ROM (not shown), etc.)
The slaves are connected in cascade so as to sequentially transmit and receive response signals of the input and output, the monitoring signal is given to the slave at one end of the cascade connection as a response signal of the input, and the slave at the other end is given the monitoring signal as a response signal of the input, and The response signal (hereinafter referred to as final slave response signal) output from A first determining means (such as an AND gate) that determines that the supervisory trigger signal is output; and a second determining means (such as an AND gate) that determines that the final slave response signal is output while the supervisory signal disappears. (AND gate, etc.) and means (OR gate, etc.) for supplying the discrimination signal of the first or second discrimination means to the master.

〔発明の実施例〕[Embodiments of the invention]

以下第１図〜第５図に基づいて本発明の詳細な説明する
。第１図は本発明の一実施例としての構成を示すブロッ
ク回路図、第２図〜第５図は第１図の動作を説明するタ
イムチャートで、第２図は全てのスレーブが正常な場合
を、第３図〜第５図は何れかのスレーブが異常となった
場合を示す。The present invention will be described in detail below based on FIGS. 1 to 5. Fig. 1 is a block circuit diagram showing the configuration of an embodiment of the present invention, Figs. 2 to 5 are time charts explaining the operation of Fig. 1, and Fig. 2 shows a case where all slaves are normal. 3 to 5 show cases where any slave becomes abnormal.

なお以下の説明中論理Ｈｉ　ｇ　ｈは単にＩＨ”と。Note that in the following explanation, logic Hi gh is simply ``IH''.

論理ＬＯＷは単にＩＬＩと記すこととする。Logic LOW is simply written as ILI.

第１図に８いて、５Ｌ（８Ｌ１〜５ＬＮ）は縦続に接続
されたスレーブ、ＲＰ（ＢＰ１〜ＲＰｍ）は各スレーブ
ＳＬ１〜８ＬＮが出力する後述の応答信号。8 in FIG. 1, 5L (8L1 to 5LN) are slaves connected in cascade, and RP (BP1 to RPm) are response signals, which will be described later, output by each slave SL1 to 8LN.

ＦＦはフリップ・フロップ、２０はスレーブＳＬＮから
出力される応答信号ＲＰＶの立下がりを検出する立下が
り検出回路、Ｇ１０．Ｇ１１はアンドゲート、Ｇ１２は
オアゲート、ＡはマスタＭから７リツプ・フロップＦＦ
に繰返し出力される監視トリガ信号、Ｂはフリップ・フ
ロップＦＦからスレーブ８Ｌ１ｓζ出力される監視信号
、ＣはオアゲートＧ１２からマスタＭｔＣ出力されるス
レーブ異常信号、ＤはアンドゲートＧｌｌからオアゲー
トＧ１２１Ｃ出力されるスレーブ異常信号、Ｅはアンド
ゲートＧ１０からオアゲートＧ１２に出力されるスレー
ブ異常信号である。FF is a flip-flop; 20 is a fall detection circuit for detecting the fall of the response signal RPV output from slave SLN; G10. G11 is AND gate, G12 is OR gate, A is 7 lip-flop FF from master M.
B is the monitoring signal outputted from the flip-flop FF to the slave 8L1sζ, C is the slave abnormality signal outputted from the OR gate G12 to the master MtC, and D is the slave outputted from the AND gate Gll to the OR gate G121C. The abnormal signal E is a slave abnormal signal output from the AND gate G10 to the OR gate G12.

また第２図〜第５図−こおいて、（１）は監視トリガ信
号Ａ％（２）は監視信号Ｂ、　（３）　、　（４）　、
　（５）はそｎぞれ応答信号ＲＰ１．　ＲＩＦ２．　Ｒ
ＩＰＮ、　（６）はスレーブ異常信号り、（７）はスレ
ーブ異常信号Ｅの各出力のタイミングを示す。Also, in Figures 2 to 5, (1) is the monitoring trigger signal A%, (2) is the monitoring signal B, (3), (4),
(5) are the response signals RP1. RIF2. R
IPN, (6) shows the timing of each output of the slave abnormal signal E, and (7) shows the timing of each output of the slave abnormal signal E.

始め蕾こ第２図を参照しつつ、スレーブＳＬの正常時ｆ
Ｃおける第１図の動作を説明する。まずマスタＭ＆ｉ”
ＨＩの監視トリガ信号Ａをパルス状に出力する（第２図
（１）１時点ｔ２０）。フリップ・フロップＦＦはこの
監視トリガ信号Ａをセット端子Ｓに入力してラッチし１
．その出力であるＩＨｌの監視信号Ｂをスレーブ８Ｌ１
に対して出力する（第２図（ｚ１時時点２１）。スＬ／
−ブｓｔ、ｔは、監視信号Ｂの立上がりを検知Ｌ’ｋ　
　＃　Ｈ＃の応答信号ＲＰ１をパルス状にスレーブ８Ｌ
２に出力する（第２図（３）。Referring to Figure 2, the slave SL's normal f
The operation of FIG. 1 in C will be explained. First, master M&I”
The HI monitoring trigger signal A is output in the form of a pulse (1 time point t20 in FIG. 2 (1)). The flip-flop FF inputs this monitoring trigger signal A to the set terminal S and latches it.
．． The output IHL monitoring signal B is sent to slave 8L1.
(Figure 2 (time point 21 at z1).
- bus st, t detects the rise of the monitoring signal B L'k
#H# response signal RP1 is pulsed to slave 8L.
2 (Figure 2 (3)).

時点ｔ２２）。同様にスレーブＳＬ２もＩＨ”の応答信
号ＲＰ１の立上がりを検知し１次のスレーブに応答信号
ＢＰ２を出力する（第２図（ａ１時時点２３）。Time t22). Similarly, slave SL2 also detects the rise of response signal RP1 of IH'' and outputs response signal BP2 to the primary slave (FIG. 2 (time point 23 at a1)).

このようにして最終スレーブ８１１もＩＨｌの応答信号
ＲＰＮを出力する（第２図（５）１時点ｔ２４）。In this way, the final slave 811 also outputs the IHl response signal RPN (time t24 in FIG. 2(5)).

次）Ｃ立下がり検出回路２０はこの応答信号ＲＰｉｒの
立下がりをとらえ、フリップ・フロップＦ　Ｆのリセッ
ト端子几に入力し、監視信号Ｂをリセットする（第２図
（５）、■９時時点２５）。Next) The C fall detection circuit 20 captures the fall of this response signal RPir, inputs it to the reset terminal of the flip-flop FF, and resets the monitoring signal B (Fig. 2 (5), ■ At 9 o'clock) 25).

このようにスレーブ異常が正常動作中、７リツブ・７０
ツブＦＦがセットされているとき１Ｃは。In this way, when the slave abnormality is operating normally, 7 ribs and 70
1C when Tsubu FF is set.

７リツプ・フロップＦＦの反転出力ＱｆＪＳ”Ｌｌであ
るため、またフリップ・７０ツブＦＦがリセットされて
いるとき（反転出力ＱがＩＨＩのとき）Ｉｃは、Ｉ／に
終スＬ／−＃６の応答信号ＲｐｍｆｆｉｓＬ１であるた
め、アンドゲートＧＩＯの出力であるスレーブ異常信号
ＥはＩＬ”のままである。また監視トリガ信号Ａの出力
周期を応答信号ＲＰＮが戻ってくるまでの時間より十分
に余裕をもった値ｔこしておけば、監視トリガ信号人を
出力する時シζは。Since the inverted output QfJS"Ll of the 7 flip-flop FF, and when the flip 70-tub FF is reset (when the inverted output Q is IHI), Ic is the final step L/-#6 of I/. Since the response signal is RpmffisL1, the slave abnormality signal E, which is the output of the AND gate GIO, remains at IL''. Furthermore, if the output period of the monitoring trigger signal A is set to a value t that is sufficiently longer than the time required for the response signal RPN to return, the time ζ for outputting the monitoring trigger signal A can be determined as follows.

監視信号Ｂが１Ｌ１となっているため、アンドゲートＧ
ｌｌの出力であるスレーブ異常信号りも・Ｌｌのままで
ある。従ってスレーブ異常信号Ｃはオアゲート０１２に
より常に１Ｌ″のままである。、゛ツテ次ｔζスレーブ
異常時の動作を説明する。スレーブ異常の事例ＩＣは、 ■　いずれかのスレーブ８Ｌが応答信号ＢＰを出力し、
ない。Since the monitoring signal B is 1L1, the AND gate G
The slave abnormality signal which is the output of ll remains at Ll. Therefore, the slave abnormality signal C always remains at 1L'' due to the OR gate 012. Next, we will explain the operation at the time of slave abnormality.In the case of slave abnormality, the IC is as follows: ■ One of the slaves 8L outputs the response signal BP. death,
do not have.

■　いずれかのスレーブが応答信号を出力したままとな
る。■ One of the slaves continues to output the response signal.

■　いずれかのスレーブが勝手會こ応答信号を断続する
。■ One of the slaves intermittents the response signal.

といったことが考えられる。Something like this can be considered.

第３図は一例としてスレーブ８Ｌ２が■の異常となった
場合を示すタイムチャートであり、この場合は結果きし
て最終スレーブ８ＬＩの応答信号孔ＰＩがＩＨＩとして
出力されず（第３図６））％監視信号３３　ｆＪＳ＃　
ＨＩのままでリセットされないため（第３図（り）１次
の監視トリガ信号人が１Ｈ１として出力されると（第３
図（１）９時点ｔ３１）％アンドゲートＧＩＩＩＣより
スレーブ異常信ｉ也Ｓ’Ｈ’。FIG. 3 is a time chart showing, as an example, a case where the slave 8L2 becomes abnormal (■). In this case, as a result, the response signal hole PI of the final slave 8LI is not output as IHI (FIG. 3, 6). )% monitoring signal 33 fJS#
Since it remains HI and is not reset (Fig. 3), when the primary monitoring trigger signal is output as 1H1 (the 3rd
Figure (1) 9 time point t31) Slave abnormal signal S'H' from AND gate GIIIC.

従って同信号ＣもＷＨＩとなる（第３図（６）９時点ｔ
３１）。Therefore, the same signal C also becomes WHI (Fig. 3 (6) 9 time t
31).

第４図は一例としてスレーブＳＬ２が■の異常となった
場合を示すタイムチャートである。この場合時点ｔ４０
ｓこ出力された監視トリガ信号Ａ＃ζ基Φ づいて時点４１に出力された応答信号ＲＰ２が以後立下
がることがないので、監視信号Ｂは一度は時点ｔ４２ｆ
こ最終スレーブ８Ｌ２の応答信号’ＢＰｗでリセットさ
れるが、次の時点ｔ４３に出力される監視トリガ信号へ
に基づいては、応答信号ＲＰ２は変化せず”Ｈｌのまま
であり、従って最終スレーブＳＬＨの応答信号ＲＰ）Ｉ
も出力されず、監視信号ＢはリセットされずａＨｌのま
まとなる。このため次−こ次点ｔ４４＃ζ出力される１
Ｈ１の監視トリガ信号Ａによって、アンドゲートＧ１１
の出力信号としてのスレーブ異常信号りがＩＨｌ、従っ
て開信号Ｃカ’　Ｈ”　トｆ９ｓ　（第４図（１）、■
、（ｅ１時時点４４）。FIG. 4 is a time chart showing, as an example, a case where the slave SL2 becomes abnormal (■). In this case, time t40
Since the response signal RP2 outputted at time 41 does not fall thereafter, the supervisory signal B once reaches time t42f.
This is reset by the response signal 'BPw of the final slave 8L2, but based on the monitoring trigger signal output at the next time t43, the response signal RP2 does not change and remains at "Hl", so the final slave SLH response signal RP)I
is not output, and the supervisory signal B is not reset and remains at aHl. Therefore, the next point t44#ζ is outputted as 1
By the monitoring trigger signal A of H1, AND gate G11
The slave abnormality signal as the output signal of
, (44 at time e1).

第５図は一例としてスレーブＳＬ２が■の異常となった
場合を示すタイムチャートである。時点ｔ５０＋こ出力
される監視トリガ信号人＃こよって各スレーブは一旦正
常＃Ｃ見える動作を行い、時点ｔ５１には、最終応答信
号ＲＰＭによって監視信号Ｂはリセットされる、しかし
ながら以後スレーブＳＬ２は勝手に時点ｔ５２．　ｔ５
４で応答信号ＲＰ２の出力を繰返えすため、この場合監
視信号ＢがＩＬＩ（従って７リツプＯ７０ツブＦＦの反
転信号回がＩＨｗ　）の間に１時点ｔ５２　ｓζ出力さ
れた応答信号Ｒ，Ｐ２に基づく最終応答信号ＲＰＶが時
８３１ζ出力さｎ、るものとすると、アンドゲートＧＩ
Ｏによりスレーブ異常信号Ｅが”Ｈｌ、従って同信号Ｃ
も”Ｈｌとなる。FIG. 5 is a time chart showing, as an example, a case where the slave SL2 becomes abnormal (■). The monitoring trigger signal outputted from time t50+ Therefore, each slave once performs what appears to be a normal operation, and at time t51, the monitoring signal B is reset by the final response signal RPM. However, from then on, slave SL2 automatically Time t52. t5
In order to repeat the output of the response signal RP2 at step 4, in this case, the monitoring signal B is changed to the response signal R, P2 output at one point in time t52 sζ during ILI (therefore, the inverted signal time of the 7-lip O70-tub FF is IHw). If the final response signal RPV based on the output is 831ζ n, then the AND gate GI
O, the slave abnormality signal E becomes "Hl", so the same signal C
Also becomes “Hl”.

本発明においてはマスタＭからスレーブ異常側に向けて
監視トリガ信号Ａを繰返し送出する必要があるが、この
ためにはマスタＭ自体の暴走検出用の既存のウォッチ・
ドッグ・タイマ（図外）等を利用すわば、新たな部品を
追加することなく、監視トリガ信号へを発生することが
できる。In the present invention, it is necessary to repeatedly send the monitoring trigger signal A from the master M to the slave abnormality side, but for this purpose, the existing watch signal for detecting runaway of the master M itself is required.
By using a dog timer (not shown) or the like, it is possible to generate a monitoring trigger signal without adding any new parts.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなよう一ζ本発明昏ζよれば、マ
スタ側から繰返し送出されるスレーブ異常監視用の信号
を縦続＃Ｃ接続された複数のスレーブが順次応答信号と
して授受するようにし、最終スレーブの応答信号出力側
には異常判定回路を設け、その異常判定信号をマスタが
検知するよう−こ構成するととも１ζ、マスタから出力
した監視トリガ信号及びそれをラッチした監視信号が共
にＩＨＩの時、及び監視信号がｌ　Ｉ、　Ｉで最終スレ
ーブからの応答信号がＩＨ’の時、スレーブ異常と判定
することとしたので、最大限のスレーブ異常を検知でき
る。As is clear from the above description, according to the present invention, a plurality of cascade-connected slaves sequentially send and receive signals for slave abnormality monitoring sent from the master side as response signals, and the final An abnormality determination circuit is provided on the response signal output side of the slave, and the master is configured to detect the abnormality determination signal.1ζWhen both the monitoring trigger signal output from the master and the monitoring signal latched thereto are at IHI, , and when the monitoring signal is l I, I and the response signal from the final slave is IH', it is determined that the slave is abnormal, so that the maximum number of slave abnormalities can be detected.

また゛この異常判定をウォッチＱドッグ・タイマという
特別な回路をスレーブ毎−こ設けなくても良く、極めて
簡単な回路で実施できるという効果も得らｎる。Another advantage is that it is not necessary to provide a special circuit called a watch Q-dog timer for each slave, and the abnormality determination can be carried out using an extremely simple circuit.

【図面の簡単な説明】[Brief explanation of drawings]

＠１図は本発明の一実施例としての構成を示すブロック
回路図％第２図〜第５図は嬉１図の動作を説明するため
のタイムチャート、第６図は従来装置の構成を示すブロ
ック回路図である。 Ｍ・・・・・・マスタＣＰＵ（マスタ）、５Ｌ（ＳＬ１
〜８ＬＮ）・・・・・・スレーブＣＰＵ（スレーブ）、
　２０・・・立下がり検出回路、ＦＦ・・・・・・７リ
ツブ・７０ツブ、Ｇ１０．Ｇ１１・・・・・・アンドゲ
ート、Ｇ１２・・・・・・オアゲート、Ａ・・・・・・
監視トリガ信号、Ｂ・・・・・・監視信号、ＢＰ（ＲＰ
　１〜ＲＩＰＭ）・・・−・・応答信号、Ｃ，Ｄ、　Ｂ
・・・・・・スレーブ異常信号。@Figure 1 is a block circuit diagram showing the configuration as an embodiment of the present invention. Figures 2 to 5 are time charts for explaining the operation of Figure 1. Figure 6 shows the configuration of a conventional device. FIG. 2 is a block circuit diagram. M...Master CPU (master), 5L (SL1
~8LN)...Slave CPU (slave),
20...Falling detection circuit, FF...7 ribs, 70 ribs, G10. G11...And gate, G12...Or gate, A...
Monitoring trigger signal, B...Monitoring signal, BP (RP
1~RIPM) ---Response signal, C, D, B
...Slave abnormal signal.

Claims (1)

【特許請求の範囲】 １）マスタＣＰＵ（以下マスタという）及び複数のスレ
ーブＣＰＵ（以下スレーブという）を備え、スレーブの
何れかの異常をマスタが検知するスレーブ異常監視装置
において、 繰返し、監視トリガ信号を出力する手段と、該監視トリ
ガ信号をラツチし監視信号として出力するラツチ手段と
、各スレーブに対応して設けられ、当該のスレーブが入
力した応答信号を、該スレーブから新たな応答信号とし
て出力させる手段とを設け、 前記入，出力の応答信号を順次授受するように前記スレ
ーブを縦続に接続し、前記監視信号を前記縦続接続の一
端のスレーブに前記入力の応答信号として与え、同じく
他端のスレーブから出力される前記応答信号（以下最終
スレーブ応答信号という）を前記ラツチ手段に与えて前
記監視信号のラツチ出力を消滅させるように構成すると
ともに、前記のラツチされた監視信号の存続中に前記監
視トリガ信号が出力されることを判別する第１の判別手
段と、 前記監視信号の消滅中に前記最終スレーブ応答信号が出
力されたことを判別する第２の判別手段と、前記第１又
は第２の判別手段の判別信号をマスタに与える手段とを
備えたことを特徴とするスレーブ異常監視装置。[Scope of Claims] 1) A slave abnormality monitoring device comprising a master CPU (hereinafter referred to as master) and a plurality of slave CPUs (hereinafter referred to as slaves), in which the master detects an abnormality in any of the slaves, which repeatedly receives a monitoring trigger signal. a means for outputting the monitoring trigger signal, a latch means for latching the monitoring trigger signal and outputting it as a monitoring signal, and a latch means provided corresponding to each slave to output a response signal input by the slave as a new response signal from the slave. The slaves are connected in cascade so as to sequentially transmit and receive the input and output response signals, and the monitoring signal is applied to the slave at one end of the cascade connection as a response signal to the input, and the slave at the other end of the cascade connection is provided with means for The response signal outputted from the slave (hereinafter referred to as the final slave response signal) is applied to the latching means to eliminate the latch output of the supervisory signal, and while the latched supervisory signal continues, a first determining means for determining that the supervisory trigger signal is output; a second determining means for determining that the final slave response signal is output while the supervisory signal is disappearing; A slave abnormality monitoring device comprising: means for providing a discrimination signal of the second discrimination means to the master.
JP59267644A 1984-12-19 1984-12-19 Slave error supervisory device Pending JPS61145655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59267644A JPS61145655A (en) 1984-12-19 1984-12-19 Slave error supervisory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59267644A JPS61145655A (en) 1984-12-19 1984-12-19 Slave error supervisory device

Publications (1)

Publication Number Publication Date
JPS61145655A true JPS61145655A (en) 1986-07-03

Family

ID=17447536

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59267644A Pending JPS61145655A (en) 1984-12-19 1984-12-19 Slave error supervisory device

Country Status (1)

Country Link
JP (1) JPS61145655A (en)

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