SU858117A1 - Shift register testing device - Google Patents

Description

(54) DEVICE FOR CONTROLLING REGISTER OF SHIFT

The invention relates to the field of computing and can be used to control computer nodes in particular shift registers. A device for controlling the shift is known, containing a controlled register, AND elements, delay elements |}. The disadvantage of the device is the relative complexity of the circuit implementation. The closest known from the technical essence is a device for monitoring the shift register containing a controlled shift register elements AND, elements NOT, triggers, and a 2J diagnostic test signal generator. The principle of this device is to control the shift register by periodically diagnosing its test combinations. The disadvantages of this device are relatively large hardware costs and the need for additional time for register diagnostics. The purpose of the invention is to increase the speed and simplify the device. The goal is achieved by the fact that the device for controlling the shift register containing the elements AND, the clock bus, is. The write and connect widths and the resolution bus are entered by the elements OR and the reversible counter, the first input of which is connected to the information resolution bus, the second and third inputs of the reversible counter are connected respectively to the write and read buses, the first input of the first And element is connected to the output of the first the OR element, the second input of the first element AND is connected to the clock bus, not za38581

isi, and the second input of the second element And to the first input of the device, the outputs of the elements And are connected respectively to the first and second outputs of the device, the output of the second element And connected to the first input of the second element OR, the second input of which is connected to the second input of the device, the output of the second element OR is connected to the fourth input of the reversible counter, the output of which is connected to the third output of the device.

The drawing shows the functional diagram of the proposed device .15

The device contains a controlled shift register 1, elements AND 2 and 3, elements OR 4 and 5, a reversible counter 6, a clock bus, write and read buses 8 and 9, and a data output resolution bus 10.

The reversible counter 6 is a counting device operating in the modes of addition and subtraction with a code sequence decoder at the output, which is polled at certain points in time by the information release signal. The number of bits n in the reversible counter 6 is selected from the ratio

2 km /

where m is the number of bits in the controlled register.

The proposed device works as follows.35

Before the device starts operation, the register 1 and the reversible counter 6 are reset to the initial zero state (the initial state setting circuits are not indicated in the drawing). 40 When a write signal arrives on bus 8 through an OR 4 element, an AND 2 element opens and the clock pulses go to the monitored register 1 to provide input information to it. At the same time, the recording signal goes to the second input of reBet) CHBHoro counter 6, sets it to addition mode, and opens element 3, through which information 50, represented by a binary code (codogram), is written to register 1, and through element 5 it goes to the counting input of the reverse, counter b, —which performs 55 counting of single pulses arriving as part of a codogram to the input of register 1.-,

74

After the completion of reception in register 1 of the codogram, the write signal is removed and the counter corresponding to the number of codogram units received in register 1 is set in the counter. To read the codogram from register 1, a read signal is transmitted to the bus .9 and opens the AND 2 element through the OR element and the clock pulses are fed to the register to read the waveforms from it. At the same time, the read signal is fed to the third input of the reversible counter 6, setting it to the subtraction mode. In this case, the units of the codogram from the output of register G through the element OR 5 are again fed to the counting input of the reversible counter 6, changing the previously recorded code in it. At the end of the read signal, the first input of the reversing counter 6 receives a resolution signal on the bus 10, which interrogates the decoder of the code combinations of the counter b, while the following variants of the state of the counter 6 are possible:

a) if the number of Kodo1G units received in register J is equal to the number of codogram units read from it after storage, then

the counter b is set to the source zero state code. The indicated status is polled by the information release signal;

b) if during storage in the register I of the received codogram the number of units for some reason (from interference, malfunction of register 1, etc.) changes (increases or decreases}), then in counter 6 a code is set that is different from the original In this case, after the counter b is polled by a signal to receive information on its output, a failure signal is generated.

Claims (2)

 The proposed device allows control of the register s during its main operation, i.e. without additional time for diagnostics of the register. In addition, the device compares with the known devices of this type from a simple circuit implementation, which reduces the cost of its equipment. The proposed device can be used to control shift registers of various lengths. An apparatus for monitoring a shift register containing AND elements, a clock bus, a write and read bus, and an information resolution bus, characterized in that, in order to increase the speed of the device and simplify it, OR elements and a reversible counter are entered into it, the input of which is connected to the information resolution resolution bus, the second and third inputs of the reversible counter are connected respectively to the write and read buses, the first input of the first element I is connected to the output of the first element OR, the second input of the first element AND is connected to the clock bus, the inputs of the first element OR are connected respectively to the write and read buses, the first input of the second element AND is connected to the recording bus, and the second input of the second element AND to the first input of the device, the outputs - And s are connected respectively to the first and second outputs of the device, the output of the SECOND element AND is connected to the first input of the second CM element, the second input of which is connected to the second input of the device, the output of the second element OR is connected to the fourth swing down counter whose output is connected to the third output device. Sources of information taken into account in examination 1. USSR author's certificate No. 529488, cl. G P S 29/00, 1978. 2. Authors certificate USSR 463973, cl. G 06 F 11/00, 1974 (prototype). Vmz On8 t- ten