JPH0773074A - Timer circuit - Google Patents

Abstract

PURPOSE:To provide a timer circuit which can measure plural time through the use of a single counter. CONSTITUTION:Differential registers (0-15) and corresponding comparison registers (0-15) are included in a communication controller 20. A bus controller 21 releases the mask bit of an interruption register 27 by an indication from CPU. When interruption corresponding to the bit becomes a permission state, the bus controller 21 adds the values of the corresponding differential registers (0-15) and the output value of a counter 24 in an adder 28, and stores an addition value in the corresponding comparison registers (0-15). When the counter 24 counts up and the value matches with the values of the comparison registers (0-15), a time-up signal is outputted from EX-OR gates 29-0,...29-15 and it is supplied to an interruption controller 22. The interruption controller 22 receives the time-up signal and outputs an interruption signal to an external part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control device. In particular, it relates to a communication control device used for a communication interface to which a plurality of control devices are connected.

[0002]

2. Description of the Related Art GPIB and RS232 are used as communication standards for connecting various measuring devices and computers.
Communication standards such as C are defined.

Of these, GPIB (General P
The urpose Interface Bus) is a digital interface defined as a standard by the Institute of Electrical and Electronics Engineers in 1978, and its standard name is IEEE-4.
Also called 88.

The basic standard is a parallel interface devised by Hewlett-Packard Company (hereinafter referred to as HP) in the United States in order to communicate data between its measuring instrument and a personal computer. In HP, this standard is called HP-IB.

FIG. 4 shows a connection configuration diagram of the GPIB. In the GPIB connection example shown in FIG. 4, one measurement / control device 10 has three measurement devices 12-
1, 12-2, 12-3 are connected via the GPIB bus 14. In FIG. 4, the measurement / control device 10 is
It plays a role of issuing a measurement instruction to the other measuring devices 12-1, 12-2, 12-3 and receiving and storing the measured value. Although only four devices are shown in total in FIG. 4, up to 15 devices can be connected in the GPIB standard. Therefore, for small and medium-sized applications, it is possible to easily build a measurement system with a single-line bus.

[0006]

Conventionally, GPIB has been used for the purpose of constructing a small / medium scale measurement system with few connected devices, and has a high function and high speed to simultaneously control a plurality of measurement devices. It was not used for the required purpose. This is because, as described above, GPIB is defined for the purpose of constructing a relatively small scale measurement system. For this reason, a dedicated measuring system was produced when it was necessary for a special purpose.

However, in recent years, there are many devices that can be connected,
With GPIB, which has been widely distributed in the market for many inexpensive devices, it has become desirable to build a system that can meet the demand for high functionality and high speed.

However, since GPIB connects a plurality of devices with one cable, a talker (caller) can have only one device at a time. Therefore, when simultaneously controlling a plurality of measuring devices (when simultaneously reading out data, etc.), the measurement / control device must constantly monitor the timing of data output of each measuring device by polling. As a result, the software becomes complicated and the processing time also increases.

On the other hand, the data processing time of each measuring device (the processing time from when a command to measure is issued until the data can be actually output) is often
It is almost constant. That is, the thermometer (12
Since -1), the pressure gauge (12-2), and the like perform only a single operation of measuring a single physical quantity, the processing time is generally the same.

Therefore, it is possible to control a plurality of devices by using an interrupt by a timer without using the above-mentioned polling. In this case, the software does not become so complicated because it is only necessary to create a processing routine for the timer interrupt. Under this idea,
The measurement / control device 10a incorporating the timer 14 is shown in FIG.
Is shown in. As shown in FIG. 5, since the number of timers 14-1, 14-2, ... 14-15 is equal to the number of measuring devices to be controlled, in the case of GPIB, the maximum number of timers is 15. A timer was needed, and the amount of hardware became huge.

The present invention has been made to solve the above problem, and an object thereof is to obtain a timer circuit that operates equivalently to a plurality of timer circuits using only one counter.

[0012]

In order to solve the above-mentioned problems, the first aspect of the present invention, counting means for counting a predetermined clock signal, a plurality of difference registers, and a comparison provided for each of the difference registers. A register, an output value of the counting means, an addition means for adding the output value of any one of the difference registers, and storing the result in the corresponding comparison register, an output value of the counting means, and the comparison register. And a time-up detecting means for outputting a time-up signal for each of the comparison registers when they match each other.

In order to solve the above-mentioned problems, the second aspect of the present invention is, in the timer circuit of the first aspect of the present invention, an interrupt signal generating means for outputting an interrupt signal for each of the comparison registers to which the time-up signal is output. It is a timer circuit characterized by including.

In order to solve the above problems, a third aspect of the present invention is the timer circuit of the second aspect of the present invention, which includes an interrupt mask register for masking an interrupt signal for each comparison register, and is effective for each interrupt signal. / A timer circuit characterized by setting invalidity.

According to a fourth aspect of the present invention, in order to solve the above problems, in the timer circuit of the second or third aspect of the present invention, when any one of the interrupt signals is output, the interrupt signal is latched. A timer circuit characterized by including an interrupt register and notifying the latched contents to the outside.

In order to solve the above-mentioned problems, a fifth aspect of the present invention is a communication control device connected to a plurality of controlled devices via a communication line, wherein a processing waiting time is set for each of the controlled devices. In a communication control device including timer interrupt means for setting and outputting an interrupt signal when a processing waiting time for each controlled device has elapsed, the timer interrupt means is the second or third or fourth book. It is a timer circuit of the invention, and is a communication control device characterized in that the processing waiting time for each of the controlled devices is set in the difference register.

[0017]

The adding means in the first aspect of the present invention adds the counter output value of the counting means and the output value of the difference register. Then, it is stored in the comparison register corresponding to the difference register. Therefore, the value stored in the comparison register is larger than the counter output value by the output value of the difference register.

The interrupt signal generating means in the second aspect of the present invention outputs the corresponding interrupt signal immediately after the time-up signal is output for each comparison register. Therefore, the interrupt signal can be output with different time-up times for each of the plurality of comparison registers.

The mask register in the third invention is
The validity / invalidity is set for each of a plurality of interrupt signals. Therefore, it is possible to enable only the required number of interrupt signals among the plurality of comparison registers.

The interrupt register according to the fourth aspect of the present invention latches a plurality of interrupt signals. Therefore, it is possible to know which interrupt signal has occurred by reading the latched contents from the outside.

The timer interrupt means in the fifth aspect of the present invention is
In the timer circuit according to the second, third, or fourth aspect of the present invention, since the processing waiting time for each controlled device to be processed is set in the plurality of difference registers, An interrupt signal is generated after the elapse of the time set to.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows a block diagram of a communication control apparatus according to a preferred embodiment of the present invention. In this embodiment, the conventional measurement / control device 10a (see FIG. 5) is used.
Unlike the above, only a single GPIB interrupt timer outputs an interrupt signal after a lapse of a plurality of periods corresponding to a plurality of measuring devices. That is, the GPIB interrupt timer 20 in this embodiment is the timers 14-1, 14-2, ... In FIG.
14-15 and an interrupt controller.

The characteristic of this embodiment is that this G
The PIB interrupt timer 20 has only a single counter. This makes it possible to prevent an increase in hardware and obtain a small communication control device.

GPIB interrupt timer 20 in this embodiment
A detailed configuration block diagram of the above is shown in FIG. As shown in FIG. 1, the GPIB interrupt timer 20 is connected to the CPU bus via a bus controller 21. That is, in this embodiment, the GPIB interrupt timer 20 exists as a part of the memory or the I / O circuit as seen from the CPU. This bus controller 21
Is an internal register (difference register 0 to 15, interrupt register, interrupt mask register) according to a command from the CPU.
The value held in is sent to the CPU, or a predetermined value is set in the internal register. Further, the bus controller 21 causes the adder 28 to add the values of the counter 24 and any one of the difference registers (0 to 15), and the addition result is added to each of the difference registers (0 to 1).
5) corresponding to the comparison register (0-1
Store in the corresponding comparison register in 5).

The counter 24 is a counter for counting the clock signal φ from the outside. This clock signal φ
The CPU clock signal and the GPIB clock signal are supplied. In this embodiment, the counter 24 is an up counter, and the value held by the counter 24 is incremented in synchronization with the clock signal φ.

The difference register (0 to 15) stores a predetermined value from the CPU via the bus controller 21 as described above. As will be described later, the value held in the difference register (0 to 15) is added to the output value of the counter 24 in the adder 28 and stored in the corresponding comparison register (0 to 15). The value held in the comparison register (0 to 15) is compared with the output value of the counter 24 as described later, and if they match, an interrupt signal is output. This point is a characteristic configuration of the present embodiment, and has various operational effects. That is, since the value to be compared with the output value of the counter 24 is held in a plurality of comparison registers (0 to 15), it is possible to realize an interrupt timer having a plurality of intervals. As a result, a plurality of counters 24 are conventionally required to realize a plurality of timer interrupts, but only one counter 24 is used.

That is, this difference register (0 to 15)
The value stored in is set to the time until the interrupt signal is output. The difference registers (0 to 1) are stored in the corresponding comparison registers (0 to 15).
A value obtained by adding the time set in 5) to the current output value of the counter 24 is set. Therefore, the comparison register (0
15), regardless of the current value of the counter 24, the difference register (0 to 1) is always added to the output value of the counter 24.
A value obtained by adding the time held in 5) is set.

The value representing the time to be stored in the difference register (0 to 15) is preferably obtained by actual measurement when the GPIB measurement system is completed. Or
It is also preferable that the processing time of all the measuring devices be obtained by software when the power of the measuring system is turned on.

In the comparison register (0 to 15), a value obtained by adding the corresponding difference register (0 to 15) and the output value of the counter 24 as described above is set. Therefore, the comparison register (0 to
The value held in 15) is always larger than the output value of the counter 24 by the value held in the difference register (0 to 15). As a result, from the time when the value is set in the comparison register (0 to 15), after the time (value) held in the difference register (0 to 15) elapses, It becomes equal to the output value of the counter 24. EX in each comparison register (0 to 15)
-OR gates 29-0, ..., 29-15 are connected. Although not shown in FIG. 1 by one line, each EX-OR gate 29-0, ... 29-1
5 has the same number of bits as the comparison register (0 to 15) and the counter 24, and the corresponding comparison register (0 to 1).
5) and the output value of the counter 24 are constantly compared.
Then, when both have the same value, the time-up signal is supplied to the interrupt controller 22.

The adder 28 is connected to the bus controller 21.
The difference register (0-15) and the output value of the counter 24 are added, and the addition result is stored in the corresponding comparison register (0-15). In this way, the addition is performed by the instruction of the bus controller 21,
At the same time, the value of which difference register (0 to 15) is the counter 2
4 is added to the output value of the corresponding comparison register (0 to
The bus controller 21 also specifies whether to store in 15). That is, the bus controller 21 appropriately switches between the selector 28 a provided at the input of the adder 28 and the selector 28 b provided at the output of the adder 28 when the addition is performed by the adder 28.

The interrupt controller 22 receives the time-up signal from the EX-OR gates 29-0, ... 29-15 and sends the interrupt signal to the external CPU. The interrupt controller 22 uses one of the EX-OR gates 29-0,
When the time-up signal from 29-15 is received, the interrupt mask register 27 is first read. Then, it is possible to know which time-up signal is masked based on the value read from the interrupt mask register 27.
This interrupt mask register 27 is a 16-bit register, and each 1-bit corresponds to a corresponding comparison register (0 to 15) to an EX-OR gate 29-0, ... 29-.
It indicates whether or not the time-up signal output via 15 is masked. For example, if a predetermined 1 bit of the interrupt mask register 27 is "0", the corresponding time-up signal is valid without being masked. However, if the predetermined bit is "1", the corresponding time-up signal is in a so-called masked state, and even if this time-up signal is output, the interrupt controller 22 sends the interrupt signal to the outside. There is no such thing. In this way, the interrupt controller 22 outputs the interrupt signal to the outside when the time-up signal not masked by the interrupt mask register 27 is output. At the same time as outputting the signal, the interrupt controller 22 sets a bit at a predetermined position in the interrupt register 26 corresponding to the time-up signal which is a factor of the interrupt signal to "1". The interrupt register 26 also has the same number of bits as the comparison registers (0 to 15), and the interrupt controller 22 outputs the interrupt signal to the outside and, at the same time, the position corresponding to the time-up signal output. The value in which the bit of is set to “1” is stored in the interrupt register 26. Since the interrupt register 26 holds the time-up signal that caused the interrupt in this way, the CPU reads the value of the interrupt register 26 through the bus controller 21 to generate any kind of interrupt. It is possible to know how.

The bit of the interrupt mask register 27 corresponding to the position set to "1" in the interrupt register 26 becomes "1", and the next interrupt is prohibited.

Further, the CPU is the bus controller 21.
A predetermined value can be written in the interrupt mask register 27 through. By setting a predetermined bit of the value to be written here to "1", an interrupt caused by the fact that the value stored in the corresponding comparison register (0 to 15) matches the output value of the counter 24 Can be masked. Note that the bus controller 21 in this embodiment constantly monitors whether or not there is a write in the interrupt register 27. If there is a write, the value before the write and the newly written value are written. Are compared to determine whether or not there is a comparison register (0 to 15) whose mask has been released.

When there is a comparison register (0 to 15) whose mask has been released, the difference register (0 to 15) corresponding to it and the output value of the counter 24 are added in the adder 28, Corresponds to a value (ie
Store in unregistered compare register (0-15). Of course, the masked comparison register (0 to 15)
If there are a plurality of items, the addition is performed a plurality of times.
That is, start was instructed (mask released)
The comparison value is newly stored in the comparison register (0 to 15).

In this case, switching between the input and the output of the adder 28 is automatically performed by the bus controller 21 controlling the selectors 28a and 28b provided at the input and the output of the adder 28. . That is, CPU
After writing a predetermined value to each difference register (0 to 15), all the bits except the bit corresponding to the timer you want to use are set to "1" and stored in the interrupt register 27. A predetermined value is set in the comparison register (0 to 15).

An example of a program to be executed by the CPU inside the communication control device 20 in this embodiment is shown in the flowchart of FIG. As shown in FIG. 3, in the initialization after the power is turned on, a predetermined count value is set in the difference register (0 to 15) as shown in step S3-1. This count value represents the time of the interval at the time of timer interruption as described above.

In the GPIB processing, first, the measuring instrument 1 is instructed to read data as shown in step S3-2. Here, for example, the measuring instrument 1 is a measuring instrument such as a thermometer as shown in FIG.

Next, in step S3-3, bit 0 of the interrupt mask register 27 is set to clear "0". All bits of the interrupt mask register 27 are set to "1" by power-on reset when the power is turned on. That is, in this step S3-3, only the bit 0 of the value of the interrupt mask register 27 becomes "0", and all other bits remain "1".

As described above, in the bus controller 21 of this embodiment, any bit of the interrupt mask register 27 is unmasked (that is, the bit is changed from "1" to "0"). When it is determined that the mask is released, the adder 28 adds the corresponding value of the difference register 0 and the output value of the counter 24. At this time, the selector 28a on the input side of the adder 28
Is switched to the difference register 0 as described above. Further, the selector 28b provided on the output side of the adder 28 is also switched to the comparison register 0, and the addition output value of the adder 28 is stored in the comparison register 0. These series of addition / storing are automatically performed by the bus controller 21 and do not appear as a program of the CPU. That is, the CPU simply clears bit 0 of the interrupt mask register 27 as is done in step S3-3.

If the value held in the interrupt register 0 matches the output value of the counter 24 after a predetermined time has passed, the EX-OR gate 29-0 outputs a time cup signal, Result The interrupt controller 22 outputs an interrupt signal to the CPU. Then, in this timer interrupt processing routine, the interrupt register 26 is first read in step S3-4. This interrupt register 26
By reading out, the comparison register (0 to 15) that caused the interrupt is specified.

In step S3-5, it is determined whether the specified one is the timer 0.

When it is determined that the timer is 0 in step S3-5, it is checked in step S3-6 whether data can be read from the measuring instrument 1.
As a result, when the data can be read from the measuring instrument 1,
The process moves to step S3-7, the data is actually read, and the interrupt process ends.

If the data cannot be read from the measuring instrument 1 in step S3-6, it is determined that the count value stored in the difference register (0 to 15) is too small in the initial setting, and step S3-8 At, the value of the difference register 0 is corrected. After the processing of step S3-8, an inspection is performed again in step S3-6 as to whether or not the data can be read from the measuring instrument 1. Then, the process of correcting the value of the difference register 0 is repeated until the data can be read from the measuring instrument 1. In this way, the value of the difference register is appropriately corrected during the actual processing, and the most appropriate value is set.

If the timer is not 0 in step S3-5, it is determined that the interrupt is from another timer, and a check is made as to whether or not the timer is another timer. This inspection is step S3-5 shown in FIG.
Since it is basically the same as the processing from steps S3 to S3-8, it is not shown in FIG.

As described above, according to this embodiment, it is possible to generate a plurality of types of timer interrupts using only one counter. Therefore, even when the communication control device according to the present embodiment controls a plurality of measuring devices at the same time, without increasing the amount of hardware, and
It is possible to prevent the program from becoming complicated. Therefore, an inexpensive and small communication control device can be obtained, and a measurement system with good performance can be constructed.

[0047]

As described above, according to the first aspect of the present invention, it is possible to obtain the timer circuit which can output the timer-up signal after a plurality of times have elapsed while using only the single counting means. To be

Further, according to the second aspect of the present invention, the interrupt signal generating means is applied to the timer circuit of the first aspect of the present invention. Therefore, while using a single counting means, the timer interrupt is generated after a plurality of times have elapsed. A timer circuit that can be activated is obtained.

According to the third aspect of the present invention, the timer circuit of the third aspect of the present invention is further provided with a mask register capable of setting valid / invalid of each of a plurality of interrupt signals. It is possible to set an arbitrary number of timers for outputting an interrupt signal.

According to the fourth aspect of the present invention, the timer circuit of the second or third aspect of the present invention further includes an interrupt register for latching an interrupt signal. It is possible to know from which of a plurality of timers the interrupt signal has occurred by reading out.

According to the fifth aspect of the present invention, in the communication control device using the timer circuit of the second, third or fourth aspect of the present invention as timer interrupt means,
The processing waiting time was set for each controlled device. for that reason,
Since each controlled device detects the time when the processing is completed, it is not necessary to constantly monitor the communication line by polling or the like.

[Brief description of drawings]

1 is a configuration block diagram showing a detailed configuration of a GPIB interrupt timer 20 shown in FIG.

FIG. 2 is a configuration block diagram of a communication control device according to a preferred embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of software to be executed by a CPU in the present embodiment.

FIG. 4 is a configuration diagram showing a connection of a conventional GPIB.

5 is a configuration diagram when the measurement / control device 10 in FIG. 4 generates a plurality of timer interrupts. FIG.

[Explanation of symbols]

 21 bus controller 22 interrupt controller 24 counter 26 interrupt register 27 interrupt mask register 28 adder 28a, 28b selector 29-0, ... 29-15 EX-OR gate

Claims (5)

[Claims] 1. A counting means for counting a predetermined clock signal, a plurality of difference registers, a comparison register provided for each difference register, a counter output value of the counting means, and any one of the differences. Adder means for adding the output value of the register and storing in the corresponding comparison register, the output value of the counting means and the output value of the comparison register are compared, and if they match, the comparison register A timer circuit comprising: a time-up detecting means for outputting a time-up signal for each time. 2. The timer circuit according to claim 1, further comprising: an interrupt signal generating unit that outputs an interrupt signal for each of the comparison registers to which the time-up signal is output. 3. The timer circuit according to claim 2, further comprising an interrupt mask register for masking an interrupt signal for each of the comparison registers, and setting valid / invalid for each of the interrupt signals. 4. The timer circuit according to claim 2, further comprising an interrupt register that latches each of the interrupt signals when any of the interrupt signals is output.
A timer circuit for notifying the latched content to the outside. 5. A communication control device connected to a plurality of controlled devices via a communication line, wherein a processing waiting time is set for each of the controlled devices, and a processing waiting time is set for each of the controlled devices. In a communication control device including a timer interrupt unit that outputs an interrupt signal when time has elapsed, the timer interrupt unit is the timer circuit according to claim 2, 3 or 4, and the process for each controlled device A communication control device, wherein a waiting time is set in the difference register.