JPS60142433A - Generating device of false error signal - Google Patents

Abstract

PURPOSE:To simulate the actually returning state of an error signal by returning a signal RDY as a signal ERR only when the counted value of a counter for counting the rising point of the signal RDY coincides with a set value. CONSTITUTION:When switches 3a, 3c are turned off and other switches are turned off as an example, logic ''1'' is obtained from terminals 0, 2 of a multiplexer 4 and logic ''0'' is obtained from other terminals. Therefore, a signal (e) of logic ''1'' is outputted from a terminal Y only at the phases of No.0 (A' B' C') and No.2 (A' B C') out of eight phases of No.0-No.7. A signal RDY is inverted by an inverter 6, the inverted signal is inputted to one input of a gate 9 and a signal passed through the gate 9 is inverted by an inverter 10, so that a signal (f) is obtained as a false error signal.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a central processing unit (hereinafter referred to as CP) for error signals.
This invention relates to a pseudo-error signal generating device that generates a pseudo-error signal and inputs it to a CPU in order to test the operation of a computer (abbreviated as U).

[Prior art]

Conventionally, the equipment for this building was as shown in Figure 1. In the figure (1), CPU%ul+ is the address bus, (6
) is the data bus, (13) is the control signal output line, ◇◆ is the status signal input line, and (2) is the non-inverting amplifier.During normal operation, the non-inverting amplifier +21 is not connected and generates a pseudo error signal. An amplifier (21) is connected when it is necessary to generate voltage. However, the voltage amplification degree of the amplifier (2) must be l,
A non-inverter with an open collector output is used. The buses U, IJ, 02, signal lines, and α◆ are connected to an input/output device (hereinafter abbreviated as "engine"; one set is not shown in the drawing).

When the CPU [11 accesses Ilo, it sends an address signal on the address bus (Ill) and the purpose of the access is C.
When outputting data from PU (1), data bus o
The data is output on the control signal output line α3, and a control signal (for example, the signal RDY shown in FIG. 1) is output on the control signal output line α3. Ilo receives these signals and performs signal input processing, but as part of this manual processing, it checks the data for code errors, and if the data is normal, it proceeds to the next process.
If there is an error in the data, an error signal (the Hakugo box shown in Figure 1 is sent to the status signal input line (J4).The CPU il+ is interrupted by the signal ERR on the line Execute the processing program.

In order to test whether the 11 C1-'U mountain correctly executes a predetermined processing program based on the signal ERR, a signal simulating the signal ERR is input to the CPU fi+. A conventional circuit for this purpose connects a non-inverter (2) shown in Figure 1 to convert the signal RDY itself into a signal ERπ- to the cPU.
It was to be sent back to tl+.

However, in such conventional devices, the signal ERR is always returned every time the signal Rl) There is a drawback in that it is not possible to simulate a situation that occurs only when an error is detected on the I10 side.

[Summary of the invention]

This invention has been made in order to eliminate the above-mentioned drawbacks of the conventional methods.This invention includes a counter that counts the rising points of the signal RDY and a multiplexer that decodes the count value of this counter. , to simulate a state in which an error signal is actually returned by returning the signal as signal i only when the value set to this multiplexer from the outside matches the count value of the counter. It was made so that it could be done.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a connection diagram showing an embodiment of the present invention, in which (3a), (3b), (3s), (3d), (3e)
, (3f), (3g).

(3h) is a switch that can be set arbitrarily from the outside, (4)
are multiplexers, (5a), (5bL(5c,), (
5d), (5fL (5gJ.

(5h) is a pull-up resistor, (6; is an inverter with hysteresis characteristics at the input, and the inverter (6;
The input of 1 is connected to the spelling (i31) in Fig.
is input. (7) is an inverter, (8) is a counter, and in the example shown in the figure, counter (8) is a 4-stage binary counter, using only the lower 3 stages, and its output is very high.

It is output from the QB and Qc terminals and sent to the multiplexer (4
(is input to terminals A, J3, and C of (9) is an AND gate, 1lO1 is an inverter, and the inverter (
The output of lO) is connected to line α◆ in FIG. 1 as a pseudo error signal simulating signal ERR.

Figures 2 and 3 are operation time charts showing the logic of the signals in each part of the circuit in Figure 2.
bl is the output Q of the first stage of the counter (81) that is triggered and inverted at the rising edge of the signal RDY, and cl is the output Q
The output Q of the second stage is triggered and inverted at the falling point of A.
In the same figure, (d+ is the output Q of the third stage that is triggered and inverted at the falling point of the output Q. In the figure (e), QA, QB, and QC are all logic 'O'. If QB is logic "1" and QA and Qc are logic "0", the output becomes logic "L".
The output signal of O) is shown.

As an example, if switches (3a,), (3c,) are turned off and the other switches are turned on, a logic "1" signal is applied to terminal 0.2 of the multiplexer (4), and a logic "1" signal is applied to the other terminals. A "0" signal is added. Therefore, the Na obtained by decoding the inputs A, B, and C of the multiplexer is
0-Nα Among the 708 types of phases, rank 0 (ABC) and N
Logic “1” is output from terminal Y only in the phase of a2 (ABC).
" signal is output.

This is the signal shown in FIG. 3(e). Figure 3 (al
The signal shown in Fig. 10 is inverted by the inverter (6) and the game is
If the signal passed through the gate (9) is inverted by using an inverter as one input of the gate (9), as shown in Figure 3 (the signal at f+ is
This signal is used as a pseudo error signal. That is,
The pseudo error signal is generated only twice every eight times the signal RDY arrives, and the interval between the two times is N[L O to Na2
up to two intervals of signal RDY and N(L 2 to Na
0 (=Nt18), the interval is equal to six times of the signal RDY, and it is possible to simulate the state in which the signal ERR actually occurs.

Note that in the embodiment shown in FIG.
Although we used a stage counter, it can be made into an arbitrary modulo counter, and the multiplexer (41) can be changed accordingly, and the switch (3a) of the multiplexer (4)
), (3b), . . . can be set arbitrarily, so that they can be set so that the pseudo error signal is generated under a situation that approximates the actual situation.

Furthermore, in the embodiment of FIG.
A pseudo error signal having a predetermined waveform may be separately generated at a signal point that occurs at the logic "1" level of the output signal.

〔Effect of the invention〕

As described above, according to the present invention, a pseudo error signal can be generated in a situation similar to a situation in which an error signal actually occurs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart showing the logic of each signal in FIG. (4)...Multiplexer, +81...Counter,
+61, +71. 1101...Inverter, (9)...And gate. Agent Masuo Oiwa

Claims (1)

[Scope of Claims] A pseudo error signal generating device that generates a pseudo error signal and inputs it to the central processing unit in order to test the operation of the central processing unit in response to an error signal, comprising: a predetermined control output from the central processing unit; A means for detecting a predetermined logical change in a signal on a signal line to generate a pulse, an arbitrary modulo counter that inputs and counts the above pulse, and inputs the parallel output of this counter and decodes it into a signal representing each count value. a multiplexer for setting the multiplexer, means for setting any one kind of number or combination of arbitrary kinds of numbers in the range of numerical values within the above modulo to this multiplexer, and setting the count value represented by the parallel output of the above counter to the above multiplexer; A pseudo-error characterized by comprising: means for outputting a signal from the multiplexer each time the signal matches the number determined by the multiplexer, and means for generating a pseudo-error signal at the time of the signal output from the multiplexer and inputting it to the central processing unit. Signal generator.