JPS6217846A - Testing method for microprocessor - Google Patents

Abstract

PURPOSE:To apply electric stress effectively by inputting a specific binary signal to bidirectional data buses consisting of plural terminals in a microprocessor through 1KOMEGA-1MOMEGA serial resistors, and when the signal coincides with a stop instruction, resetting the signal. CONSTITUTION:A signal from a clock pulse generating circuit 2 is applied to 12 binary counters 3 connected successively and a binary signal is formed by reducing its frequency into a half successively and inputted to the microprocessor 1 through 1KOMEGA-1MOMEGA serial resistors and the bidirection data buses D7-D0 in the microprocessor 1. Signals outputted from the counters 3 are inputted to a NAND circuit 4 for a reset signal generating circuit, and only when a stop instruction is outputted from a certain counter 3, a reset signal is outputted to the processor 1. Thus, even if the processor 1 is stopped due to malfunction, the processor 1 can be reset during the circulation of the input signal.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to microprocessors at room temperature, high temperature, high temperature constant humidity,
In reliability evaluation tests in various environments such as radiation,
The present invention relates to an operation test method for simply and effectively applying electrical stress to the internal circuits of a microprocessor.

[Conventional technology]

Conventional microprocessor operation testing methods can be roughly divided into (1) tests in which DC bias is applied to the power supply terminal and input terminals, and (2) tests in which a pulse is input only to the clock and DC bias is applied to other terminals. Test, (8) microprocessor and microprocessor peripheral circuits. There is a test in which a memory circuit is connected, instructions, data, and addresses for microprocessor operation are stored in the memory circuit, and the microprocessor is operated by executing the instructions.

In method (1) above, since the internal circuit does not operate in a pulsed manner as in practical use, it is not possible to effectively apply electrical stress to the internal circuit of the microprocessor.

In method (2) above, since the data bus is DC-fixed, the instruction code given to the data bus is repeatedly executed. Therefore, only a portion of the circuits related to the execution of this single instruction operate, and electrical stress cannot be applied to the entire internal circuitry of the microprocessor. The method (8) above allows the microprocessor to execute any command, so it is possible to apply electrical stress extremely effectively. However, it includes various problems such as the following. ■Connecting microprocessor peripheral circuits and memory circuits increases the number of integrated circuits, making test circuits complex. ■It is necessary to create a program for operation testing. ■The operation test program must be written in the programmable OM so that it will not be erased due to power outage, noise, etc. ■In harsh environments such as high temperatures and radiation, microprocessors may not operate normally and may not be able to execute instructions as expected.

[Structure of the invention]

In the present invention, in a reliability test of a microprocessor, a binary signal that is easy to generate is created and inputted to the data bus of the microprocessor.

It is characterized by effectively operating the internal circuits of a microprocessor by executing various instructions accompanied by various data and various address signals, and is used in a reliability test of a microprocessor.

various instructions and data that are executed by the microprocessor,
A test to effectively operate the internal circuits of a microprocessor by executing various instructions by inputting easily generated binary signals directly to the data bus without using a memory circuit to store address signals. The purpose is to provide a method.

〔Example〕

FIG. 1 shows an embodiment of the present invention. / is a microprocessor under test, λ is a clock pulse generation circuit, 3 is a binary counter, and lA is a NAND circuit for the reset generation circuit. Other terminal connections of the microprocessor are omitted.

The figure shows an example of a t-bit parallel processing microprocessor, where D7 to Do are r-bit bidirectional data buses, OLK is a clock input, and RFiSBT td! J Sera) Input text; h le. The microprocessor is reset by manual input at FLESBTH'L' level. In the figure, 72 stages of binary counters are connected to create the -D7 signal. If the clock period is To, then r). The period of is 3.2
'ro becomes. 32"f' for D7-D0 data bus
ooooooooo every o.

0000000/, ..., ////////
23- signals are input which sequentially change. The number of clock cycles required to execute an instruction differs depending on the type of instruction and the type of microprocessor, but for example, if we execute a Jr to 3 cycle instruction depending on the type of instruction, then in the example shown in the figure, it will be executed every 3.2 cycles. The same instruction may be executed once in a row because the signal on the data bus changes during the execution of the instruction, and the signal on the data bus may change during the execution of the instruction. Since the purpose is to apply electrical stress, there is no problem in either case. Signals input from the data bus include data and memory address signals in addition to instruction codes.
The microprocessor receives the four signals as either an instruction code, data, or memory address, and operates accordingly. No matter which signal the microprocessor determines is the signal input to the data bus, there is no problem because the purpose is to operate the internal circuit. Note that the address signal inputted from the data bus is a type of data, and is outputted to the address bus of the microprocessor through the microprocessor internal circuit.

, 2 to 6 signals include some invalid instructions that the microprocessor does not accept. There is no problem for the purpose of the test even if a random operation is performed due to an invalid command or no operation is performed. A problem arises when a stop command is input. , 2J-4 signals naturally include a stop command.

Once the stop command is executed, the microprocessor will not perform any operation until it is reset 11. The problem can be solved by generating a reset signal when a stop command is input to the data bus and inputting that signal to the microprocessor. FIG. 1 shows a circuit when the stop command code is 0lI10/1O. D, ~Do is oiiiiii
Only when it becomes o, all t inputs of Hiro's NAND circuit become 1H" level and the output becomes 1L1. This is input to REISBT of the microprocessor and reset.D, -Do becomes 0//10 /One other than 10!j
For all of the signals ≠ 7 of the inputs of the NAND circuit
R11SET becomes 1111 and the microprocessor is in the operating state. Since it is always reset during one cycle, it has the advantage of being able to be pulled out from a stopped state.

When the data bus of the microprocessor is in an output state, by inserting a resistor R in series with the data bus as shown in FIG. 1, excessive current flowing through the data bus can be prevented. The lower limit of the resistance value is determined by the output drive ability of the data bus and the output drive ability of the counter circuit, and the upper limit is determined by the allowable value of the pulse delay time due to the resistance value and the input terminal capacitance.

Although FIG. 1 shows an example in which there are seven microprocessors under test, if there are multiple microprocessors under test, they may be connected in parallel. However, each microprocessor's data bus has 11 resistors.
It is safer to include When testing a large number of microprocessors, it is necessary to include a pulse driver for each pulse.

In FIG. 7, the frequency is divided into j and 2'I'o by a binary counter of clock tt stage with period To. However, the purpose is achieved no matter how many stages. However, the internal clock cycle of the microprocessor is 2T.

In this case, DoIdCoTo or more is required. Furthermore, since three or more cycles may be required as a reset signal, this must also be taken into consideration.

All of the circuits in Figure 1 can use commercially available 10, -
For example, it is an extremely simple circuit that can be constructed of one clock generation circuit, two 7.2-stage counter circuits, seven inverters, and one input NAND circuit, for a total of j 0's.

〔Effect of the invention〕

As explained above, in the test of the present invention, various instruction codes, data,
An address signal can be input, and when a stop command is received, the microprocessor is reset to avoid a stopped state, and even if the data bus is in the output state, overcurrent flowing to the data bus can be prevented, so the microprocessor room temperature.

If used for reliability tests in various environments such as high temperature, high temperature and constant humidity, and radiation, it has the advantage that an inexpensive test circuit can effectively apply the same electrical stress to the internal circuits of a microprocessor as in actual use.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention. l... Microprocessor under test, Co... Clock pulse generation circuit, 3... Binary counter, ≠...♂ input NAND circuit.

Claims (1)

[Claims] When a binary signal whose frequency is sequentially lowered by half is input to a bidirectional data bus consisting of a plurality of terminals of a microprocessor through a series resistor of 1KΩ to 1MΩ, and the binary signal matches a stop command of the microprocessor. A microprocessor testing method characterized by resetting the microprocessor.