JPH04330732A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To restrain a change in the characteristic of a semiconductor device when hot carriers are injected and to increase the current driving ability of the semiconductor device in the semiconductor device such as a MOS transistor or the like. CONSTITUTION:In a MOS transistor, by a so-called LDD structure, which is provided with a low-concentration impurity region, a high-concentration impurity region 15 is overlapped with the lower part of ends of a gate electrode 13 in only a source region. In a drain region, the high-concentration impurity region 15 is formed so as to be separated from the gate electrode 13 via a low- concentration impurity region 14 in the same manner as in conventional cases.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which impurities are introduced into selective regions of a semiconductor substrate by ion implantation, and a method for manufacturing the same.

0002

2. Description of the Related Art In recent years, methods for manufacturing semiconductor devices have utilized a self-alignment method using ion implantation as semiconductor devices have become smaller.

A conventional method for manufacturing a semiconductor device will be explained below. FIGS. 2(a) to 2(f) show step-by-step cross-sectional views of a method for manufacturing an n-channel MOS field effect transistor (hereinafter abbreviated as nMOS transistor) as an example of a conventional method for manufacturing a semiconductor device. . In FIG. 2, 21 is a P-type silicon substrate, 22 is a gate oxide film, 23 is a polycrystalline silicon film, 24 is an n-type impurity layer, 2
5 is a sidewall oxide film, and 26 is an n+ type impurity layer.

A method of manufacturing the nMOS transistor configured as described above will be explained below.

First, in FIG. 2A, a gate oxide film 22 is formed on the surface of a P-type silicon substrate 21, and then a polycrystalline silicon film 23 is formed. Furthermore, a polycrystalline silicon film 23 that will become the gate electrode of the nMOS transistor is formed into a desired pattern by a well-known photolithography process and an anisotropic etching process.
The gate oxide film 22 in the etched region No. 3 is etched.

Next, in FIG. 2B, using the polycrystalline silicon film 23 as a mask, phosphorus is ion-implanted by a well-known ion implantation method to form a low impurity concentration n- A type impurity layer 24 is formed. The amount of phosphorus ion implanted at this time is about 1013 to 1014 cm-2.

Next, in FIG. 2(c), the well-known CVD
A sidewall oxide film 25 is formed using a method.

Next, in FIG. 2(d), the sidewall oxide film 2
5 is anisotropically etched to leave the sidewall oxide film 25 only on the sidewalls of the polycrystalline silicon film 23 of the gate electrode.

Next, in FIG. 2E, using the polycrystalline silicon film 23 and sidewall oxide film 25 as masks, arsenic is ion-implanted by a well-known ion implantation method to form a high-density layer near the surface of the P-type silicon substrate 21. N+ type impurity layer 2 with impurity concentration
form 6. The amount of arsenic ion implanted at this time was 10
It is about 15 to 1016 cm-2.

Next, in FIG. 2(f), 900 to 10
A heat treatment is performed at about 00° C. to diffuse the n − type impurity layer 24 and the n + type impurity layer 26, and as a result, an nMOS transistor is completed. This nMOS transistor structure is generally called an LDD structure.

[0011]

[Problems to be Solved by the Invention] However, in the conventional configuration described above, since an n-type impurity layer is provided to suppress characteristic fluctuations due to hot carrier injection, the current drive ability decreases (reduction in source/drain current, transfer conductance The problem was that there was a decrease in

The present invention solves the above-mentioned conventional problems by suppressing characteristic fluctuations caused by hot carrier injection and increasing current drive capability (increasing current between source and drain,
An object of the present invention is to provide a semiconductor device with increased transfer conductance and a method for manufacturing the same.

[0013]

[Means for Solving the Problems] In order to achieve this object, a semiconductor device of the present invention includes a source region consisting of a high concentration impurity region formed on a semiconductor substrate overlapping one end of a gate electrode, and a gate electrode. It consists of a low concentration impurity region formed on the semiconductor substrate overlapping the other end of the electrode, and a high impurity concentration region formed on the semiconductor substrate away from the gate electrode via the low concentration impurity region. and a drain region.

[0014]

[Operation] With this configuration, the high concentration impurity region of the source region of the MOS transistor overlaps with the gate electrode, so the current drive capability can be increased, and the MOS transistor
Since a low concentration impurity region is formed between the high concentration impurity region of the drain portion of the transistor and the gate electrode, characteristic fluctuations due to hot carrier injection can be suppressed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to 1(d) are sectional views showing step-by-step process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In FIG. 1, 11 is a P-type silicon substrate, 12 is a gate oxide film, 13 is a polycrystalline silicon film, 14 is an n- type impurity layer (low concentration impurity region), and 15 is an n+ type impurity layer (high concentration impurity region). It is.

A method of manufacturing a semiconductor device comprising an nMOS transistor configured as described above will be described below.
explain.

First, in FIG. 1A, a gate oxide film 12 is formed on the surface of a P-type silicon substrate 11, and then a polycrystalline silicon film 13 is formed. Furthermore, a polycrystalline silicon film 13 that will become the gate electrode of the nMOS transistor is formed into a desired pattern by a well-known photolithography process and an anisotropic etching process.
The gate oxide film 12 in the etched region No. 3 is etched.

Next, in FIG. 1B, using the polycrystalline silicon film 13 as a mask, phosphorus is ion-implanted obliquely at an angle by a well-known ion implantation method, so that phosphorus is ion-implanted into the vicinity of the surface of the P-type silicon substrate 11. , low impurity concentration n-type impurity layer 14
form. The phosphorus ion implantation angle (θ1) at this time was in the range of 0° to 75°, and the implantation amount was 1013 to 1
It is about 0.014 cm-2.

Next, in FIG. 1(c), using the polycrystalline silicon film 13 as a mask, arsenic is ion-implanted obliquely at an angle by a well-known ion implantation method, so that arsenic is ion-implanted into the vicinity of the surface of the P-type silicon substrate 11. , n+ type impurity layer 1 with high impurity concentration
form 5. At this time, the arsenic ion implantation angle (θ2
) is in the opposite direction to the phosphorus ion implantation when forming the n-type impurity layer 14, and is in the range of -15° to -75°, and the implantation amount is about 1015 to 1016 cm-2.

Next, in FIG. 1(d), 900°C to 1
Heat treatment is performed at approximately 000°C to diffuse the n- type impurity layer 14 and the n+ type impurity layer 15, and as a result, the nMOS
The transistor is completed.

As described above, according to this embodiment, the nMOS
In the source part of the transistor, the n+ type impurity layer 15 and the polycrystalline silicon film 13 serving as the gate electrode overlap, and the nMO
In the drain part of the S transistor, an n+ type impurity layer 15
and the polycrystalline silicon film 13 which is the gate electrode.
Since the LDD structure is provided with the − type impurity layer 14, it is possible to suppress characteristic fluctuations due to hot carrier injection and increase current drive capability (increase in source/drain current and increase in transfer conductance).

In the above embodiment, the gate electrode is made of polycrystalline silicon film 13, but the gate electrode is made of a wiring material that has a masking effect against ion implantation of phosphorus and arsenic, such as a high melting point metal and its silicide film. If so, it can be used.

Furthermore, a gate oxide film 1 is used as a gate insulating film.
2, but a nitride film or a composite film of an oxide film and a nitride film can also be used.

[0025]

As described above, the present invention provides a structure in which the high concentration impurity region and the gate electrode overlap in the source part of the MOS transistor, and the low concentration impurity region overlaps with the gate electrode in the drain part of the MOS transistor. By providing a concentrated impurity region, it is possible to provide a high-performance semiconductor device and a method for manufacturing the same, which can suppress characteristic fluctuations due to hot carrier injection and increase current drive capability.

[Brief explanation of drawings]

FIG. 1 is a step-by-step sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[Figure 2] Process-order cross-sectional diagram of a conventional semiconductor device manufacturing method

[Explanation of symbols]

Claims (2)

[Claims] 1. A gate electrode formed on a semiconductor substrate with a gate insulating film interposed therebetween; a source region formed of a high concentration impurity region formed on the semiconductor substrate and overlapping with one end of the gate electrode; A low concentration impurity region formed on the semiconductor substrate overlapping the other end of the gate electrode, and a high impurity concentration formed on the semiconductor substrate away from the gate electrode via the low concentration impurity region. What is claimed is: 1. A semiconductor device comprising at least a drain region formed of a drain region and a drain region. 2. A step of forming a gate electrode on a semiconductor substrate using anisotropic etching; The method comprises at least a step of ion-implanting a first impurity, and following that step, a step of ion-implanting a second impurity onto the semiconductor substrate from a direction tilted in a direction opposite to the one direction. A method for manufacturing a semiconductor device.