JPH02226759A - Manufacture of bicmos type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To unnecessitate the margin of an active base and an emitter, and reduce each pattern size to a minimum by making the base and the emitter of a bipolar transistor(Tr) of a BiCMOS type semiconductor circuit self-align, and linking the part between the active base and an inactive base by using a high concentration bridge layer. CONSTITUTION:After an N<+> type and a P<+> type buried layers 22, 23 are formed on the P-type semiconductor substrate 21 of a semiconductor device, an N<+> type epitaxial layer 24 with a specified depth is formed, and a P-type well layer 25 and an isolation diffusion layer 26 are formed at the same time by selective diffusion. On the whole surface of the substrate 21, a thin oxide film 27 with a specified thickness and nitride films 28-32 are formed in specified thicknesses. Said nitride films 28-32 are used as masks at the time of LOCOS isolation in the next process, and a nitride film between the following is eliminated; a nitride film 31 in the region where an NPN-Tr 101 turns to an active base, and a nitride film 30 in the region where the Tr 101 turns to an inactive base. A patterned resist 33 and the nitride film 31 are used as masks, and ion is implanted.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor integrated circuit, particularly a bipolar CMO3 (hereinafter abbreviated as B1Cl1O5) type semiconductor integrated circuit in which a bipolar transistor and an 0MO3 transistor are formed on the same substrate. It is related to.

(Prior art) In recent years, in order to pursue high-speed performance of 0MO3, bipolar elements are formed on the same chip, and the load driving ability of 0MO3 is increased by bipolar, thereby increasing the speed of BiCM.
O3 hybridization technology has become widely used.

In general, BiCMO3LSI has the characteristics of bipolar and 0MO3, so it is fast.

Although it can achieve excellent performance such as high integration, high breakdown voltage, high load drive capability, and low power consumption, it structurally requires epitaxial layers and isolation diffusion to mount bipolar elements.

In addition, in order to simultaneously form bipolar and 0MO3 elements without sacrificing their performance, the process is complicated and mask failure increases, but this is disadvantageous from an economic standpoint, so we are trying not to increase the number of steps. It is necessary to design the process.

Here, a conventional method for manufacturing a BiCMO3 type semiconductor integrated circuit will be explained with reference to FIG. First, as shown in FIG. 2(a), a N buried diffusion layer 2 and a P
After forming the podium feeding diffusion layer 3, an N-epitaxial layer 4 having a thickness of 2 Pa is formed, followed by a P well layer 52 and an isolation diffusion layer 6 by selective diffusion.

Thereafter, after forming a thin oxide film 7 of about 500 nm thick and a nitride film of about 1600 mm thick over the entire surface of the substrate, the nitride film in the region where the elements are to be isolated is selectively removed. In addition, in the figure, the nitride film 8
indicates a selectively removed state. Furthermore, using the patterned resist 9 as a mask, a P-type impurity such as B (boron) is implanted into the channel stopper region of NMOS (200) and the surface region of the isolation diffusion layer 6 by ion implantation. In addition, P M OS (3
N-type impurities are also implanted into the channel stopper region of 00).

Here, the N buried diffusion layer 2 is an NPN bipolar transistor (hereinafter abbreviated as N P N -Tr) (100
) to lower the collector series resistance ^3 (arsenic)
and sb (antimony) to a value of 20 to 100 Ω/portion, and is also simultaneously diffused into the PMOS (300) formation region to prevent PMOS (300) from causing parasitic bipolar operation. The P′ buried diffusion layer 3 is NPN
- In order to shorten the isolation and diffusion time by forming the Tr (100) element isolation region in advance by ion implantation, etc., and utilizing upward diffusion from the semiconductor substrate 1 during the epitaxial layer process and isolation diffusion in the next step. It is usually set to 50 to 300Ω/mouth using B, and NMOS
In order to prevent (200) from causing a parasitic bipolar operation, the NMOS (200) is also formed at the same time in the NMOS (200) formation region.
Device characteristics of Tr (100) and P M OS (300)
The concentration and thickness are determined to control the gate threshold voltage. Furthermore, P diffusion region 5.
6 is N P'N -Tr (100) element isolation and N M
It is diffused from the surface of the epitaxial layer 4 to control the threshold voltage of the OS (200).

Next, as shown in FIG. 2~), after removing the resist 9,
Activate the ion-implanted impurities at a temperature of about 00°C,
An oxide film 10 is formed by oxidation treatment, and LOGO3 isolation is completed. Note that 11 is N in which P-type impurities are implanted.
Channel stopper layer of MOS (200), 12
is a channel stopper layer of PMO3 (300) into which N-type impurities are implanted. After that, the known diffusion 9 photolithography,
By repeating etching, the Bi shown in Figure 2 (0)
The 0MO3 structure is completed.

Here, 13 is a P diffusion layer, N P N -Tr(10
0) active base, 14.15 is a P diffusion layer, 14 is the source and drain of PMOS (300), and 15 is an inactive base layer of N P N -Tr (100). . Note that the inactive base layer 15 is necessary to establish ohmic contact with the active base layer 13. Also, 16-18
is the N diffusion layer, 16 is the source and drain of NMOS (200), and 17 is N P N -Tr (100).
The emitter 18 forms a contact lead for the collector layer of the N P N -Tr (100). Furthermore, 19.
20 are P M OS (300) and N M
This is the gate of OS (200).

(Problem to be solved by the invention) However, the Bi CMO formed by the above manufacturing method
Type 3 semiconductor integrated circuits have the following problems.

(1) Emitter I of N P N -Tr (100)
7 has a structure in which it is pushed inside the active base 13, so it is necessary to ensure a margin for alignment, and therefore the element area becomes large.

(2) Since the emitter 17 is formed by directly diffusing impurities, it is difficult to form a shallow junction.

(3) A high-resistance active base layer 13 is interposed between the emitter 17 and the inactive base 15.

From this point of view, the base area and emitter area of N P N -Tr (100) must be made large and the junction formed deep, which increases the junction capacitance and also increases the equivalent base series resistance r. Higher prices, etc. are both NP
This deteriorated the high frequency characteristics of N-Tr(100).

As a result, the high-speed operation of Bi 0 MO 3 is limited by the bipolar transistor (100), resulting in a problem that desired performance cannot be obtained.

This invention eliminates the above-mentioned problems such as the large element area of bipolar transistors, which makes it difficult to make shallow junctions, and the large series resistance of the base, and enables the integration of bipolar transistors with excellent high-frequency characteristics. The purpose is to provide a method for manufacturing a circuit.

(Means for Solving the Problems) The present invention provides a method for manufacturing a BI CMO3 type semiconductor integrated circuit, in which a second conductive type epitaxial layer is formed on a first conductive type semiconductor substrate, and then a first conductive type epitaxial layer for a CMOS transistor is formed. A well layer and a separation layer of the first conductivity type are formed, and a first MOS transistor of one of P or N channel type is formed using a nitride film and a resist in a region where an active base is formed formed thereon as a mask. After implanting high-concentration impurities of the first conductivity type onto the channel stopper layer, the bridge layer between the active base and the inactive base, and the isolation layer, and forming an element isolation oxide film, polysilicon for the 0MO3 transistor is implanted. forming polysilicon on the gate and, if necessary, the region where the active base is to be formed, and introducing impurities of the first conductivity type;
Annealing to form an active base, and polysilicon and a first M formed on the active base.
A second conductivity type impurity is introduced into the source and drain Si Jli of the OS transistor and annealed to form an emitter and the source and drain, and then a first conductivity type impurity is selectively introduced to form a P or N channel. The source and drain of the other channel type 2' MOS transistor and the inactive base of the bipolar transistor are formed.

(Function) According to the present invention, the active base layer is formed using the element isolation oxide film as a mask, and the emitter layer is formed by diffusing the second conductivity type impurity from the polysilicon on the active base layer. The base and emitter can be formed by self-alignment, and there is no need for a margin for their alignment. Furthermore, since the emitter layer is formed by diffusion from polysilicon, a shallow junction can be formed. Furthermore, the active base layer and the inactive base layer are connected by a bridge layer, and this bridge layer is formed at the same time as the chamber stopper layer of the MOS transistor. can be reduced.

(Embodiment) FIG. 1 is a process cross-sectional view of a method for manufacturing a BiCMO3 type semiconductor integrated circuit showing an embodiment of the present invention, in which a PMO3 transistor (301) and an NMO3 transistor (2
01) and NPN bipolar transition failure (lot)
(Hereinafter, PMO3, NMO3 and NPN-
(abbreviated as Tr).

In the manufacturing process of such a semiconductor integrated circuit, as shown in FIG.
After forming the buried diffusion layers 22 and 23 of ゛ and P゛, an N-epitaxial layer 24 with a thickness of 2 # is formed, and then a P well layer 25 and an isolation diffusion layer 26 are simultaneously formed by selective diffusion, Further, after growing a thin oxide film 27 of about 500 mL and a nitride film of about 1600 mL on the entire surface of the substrate, the nitride film in the region for device isolation is selectively removed.

Incidentally, such a process is also described, for example, in Nikkei Microdevice, November 1986 issue, pages 72-76.

The selectively left nitrided R28 to R32 are treated with toc in the next step.
This is a mask when separating the OS, and PMO3 (30
1) and NMOS (201) are the same as the conventional ones, but N P N -Tr (101) is composed of the nitride film 31 in the active base region and the nitride film 30 in the inactive base region. The difference from the conventional method is that the nitride film in between is removed.

Next, as shown in FIG. 1+all, by ion implantation using the buttered resist 33 and nitride film 31 as a mask, the formation region 1 of the channel stopper layer 34 of NMOS (201) 1 and the isolation diffusion layer 26 are removed. The surface region and the region forming the active base layer (nitride film 31
) as a P-type impurity at an accelerating voltage of 30
l Q "ts-" injection at KeV.

In addition, in the same manner, P(
Selectively inject phosphorus).

Next, after removing 33 layers of resist and heating for 7 years at a Φ temperature of about 900°C, LOGO5 was removed as shown in Figure 1(b).
At this time, it is desirable to form the element isolation oxide film 36 at a relatively low temperature using a high-pressure oxidation method so that the ion-implanted P-type impurity is not deeply diffused.
After CO3 isolation, a P bridge layer 37 is formed under the channel stopper layer 34 and the surrounding oxide film forming the active base.

This P bridge layer 37 has the role of connecting an active base layer and an inactive base layer formed in a later step with a high concentration. Next, the nitride films 28 to 32 are removed, and using the patterned resist 38 (partially shown) as a mask, P is added as an N-type impurity at an accelerating voltage of 150 Ke.
After the resist 38 is removed and annealed, a deep collector layer 39 of N P N -Tr (101) is formed. Note that the deep collector layer 39 is necessary to reduce the collector series resistance of N P N -TrClol), and its formation method is the same as the conventional one.

Next, FIG. 1 101 shows a state in which this step has been completed, but as in the conventional case, the surface concentration of N' epitaxial layer 24 is adjusted as necessary to control the Threnshield voltage V in the PMO3 (301) forming region. After adjusting by ion implantation method, a gate oxide film 40 and a polysilicon gate 41 are formed. After forming this polysilicon gate 41, a thin oxide film 42 is formed on the entire surface of the substrate, and a resist 43 and element isolation are formed. Using the oxide film 36 as a mask, the P-type impurity 8' (boron) is IQ"cs-"
The active base layer 44 is formed by ion implantation to a certain extent and annealing at 950° C. for 7 times. At this time, ions are also implanted into the inactive layer formation region at the same time in order to lower the contact resistance.

Next, as shown in FIG. 1 (dl), the active base layer 4
After removing the thin oxide WA 42 on the active base layer 44 by selective etching, polysilicon is grown on the entire surface, and the parts other than the active base layer 44 are removed by selective etching. A silicon layer 45 is formed and a thin oxide film 46 is applied.Next, using a resist 47°48 as a mask, a polysilicon 45° deep collector layer 39 for the emitter and NMO
^3 is ion-implanted as an N-type impurity onto the source and drain 49 regions of S (201) at a high concentration of approximately IQ "cIl-".

After removing the resist 48, annealing is performed at 950°C, as shown in FIG. 1 (81).
The high concentration layer 50 on the surfaces of the source and drain layers 49 and deep collector layer 39 of 1) is formed.

Furthermore, N-type impurities are diffused from the emitter polysilicon 45 to form an I4 ivy layer 51.

Furthermore, using the resist as a mask again, PMOS (30
1), the source and drain regions 52 and the inactive layer 53 are doped with P at a high concentration of about lQ "am -".
A type impurity BF*'' is ion-implanted to form the source and drain 52 layers and the inactive layer 53.

Subsequently, contact holes are opened after all 54 of the BPSG layers 54, and metal wiring (not shown) is provided to complete a BiCMOS type semiconductor integrated circuit.

In this way, in the above manufacturing method, the active base layer 44
The pattern is determined by the LOCO5 isolation oxide film 36, and the emitter layer 51 is formed by diffusing N-type impurities from the polysilicon 45 using the isolation oxide wA 36 as a mask. Layer 51 can be formed in a self-aligned manner, thus eliminating the need for alignment margin between active base layer 44 and emitter layer 51.

Furthermore, compared to the conventional method, a process of selectively etching the thin oxide film 42 on the active base layer 44 and a process of selectively etching the thin oxide film 42 on the active base layer 44 and the process of selectively etching the thin oxide film 42 on the active base layer 44 and
Since only the step of patterning the polysilicon 45 for 1 is added, the number of mask steps can be suppressed to an increase of only 2 steps.

Further, since the emitter layer 51 is formed in the same step as the source and drain 49 of NMOS (201) and is diffused from the polysilicon 45 into which N-type impurities are ion-implanted, a shallow junction can be formed with good reproducibility.

Further, the channel stopper layer 34 of NMOS (201) and the bridge layer 37 surrounding the active base layer 44 and connecting the active base layer 44 and the inactive base layer 53 are simultaneously formed with high concentration. Therefore, the base series resistance of the N P N -Tr (101) can be reduced without increasing the number of process steps (mask steps).

Note that in the above embodiment, polysilicon 45 doped with N-type impurities was used for diffusion in the emitter layer 51 formation process.
In a similar manner, when forming the active base layer 44, a P-type impurity is diffused from polysilicon, and in the process of forming the emitter layer 51, a higher concentration of N-type impurity is introduced into the same polysilicon. It is also possible to do this, and in this way, it is possible to achieve a shallow junction between the layers. Further, in the above embodiments, there is no problem even if the N-type and P-type radii of the substrate and each layer are exchanged.

(Effects of the Invention) As explained in detail above, according to the manufacturing method of the present invention,
The base and emitter of a bipolar transistor in a Bi CMO3 type semiconductor integrated circuit are formed by self-aligning, the emitter is formed by diffusion from polysilicon, and a highly doped bridge layer is formed between the active base and the inactive base. Since the active base and the emitter are connected with each other, there is no need for a margin for alignment between the active base and the emitter, and each pattern can be made to the minimum size, making it possible to reduce the device area. In addition, the emitter can be made shallower, and the base series resistance of the bipolar transistor can be reduced without increasing the number of *ei processes. Therefore, the parasitic capacitance can be reduced through element miniaturization and shallow junctions, making it possible to increase the cut-off frequency t7 of the bipolar transistor and lowering the base series resistance.
MOS transistors can be formed at the same time.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of a method for manufacturing a BI CMO3 type semiconductor integrated circuit according to the present invention, and FIG. 2 is a process sectional view of a conventional method for manufacturing a Bi CMO3 type semiconductor integrated circuit. 21... P type semiconductor substrate, 24... N type epitaxial layer, 25... P well layer, 26... Separation layer, 2
7... Oxide film, 28-32... Nitride film, 33...
Resist, 34... Channel stopper layer, 36...
Element isolation oxide film, 37... Bridge layer, 41... Polysilicon gate, 44... Active base layer, 4
5...Polysilicon, 49...NMOS source,
Drain layer, 51... Emitter layer, 52... PMO
3 source and drain layers; 53...inactive base layer;

Claims (1)

[Scope of Claims] (a) After forming an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type, a well layer of a first conductivity type is formed in a CMOS transistor formation region, and a well layer of a first conductivity type is formed on a semiconductor substrate of a first conductivity type. (b) successively forming an oxide film and a nitride film on these entire surfaces, and selectively removing the nitride film around the device isolation region and the active base formation region of the bipolar transistor; After that, using the resist and the nitride film in the area where the active base is to be formed as a mask, the channel stopper layer of the first MOS transistor of either P channel type or N channel type and the active base of the bipolar transistor and the inactive (c) After forming an element isolation oxide film on these substrates,
Forming polysilicon on the polysilicon gate of the CMOS transistor and, if necessary, the active base formation region, selectively introducing impurities of a first conductivity type and annealing to form the active base of the bipolar transistor. (d) polysilicon selectively formed on the active base and the source of the first MOS transistor;
(e) selectively introducing impurities of the first conductivity type into the drain region and annealing to form the emitter of the bipolar transistor and the source and drain of the first MOS transistor; and forming a source and a drain of a second MOS transistor of the other channel type among P-channel type or N-channel type and an inactive base of a bipolar transistor. A method for manufacturing a BiCMOS type semiconductor integrated circuit.