JPH0429256B2 - - Google Patents
Info
- Publication number
- JPH0429256B2 JPH0429256B2 JP57042268A JP4226882A JPH0429256B2 JP H0429256 B2 JPH0429256 B2 JP H0429256B2 JP 57042268 A JP57042268 A JP 57042268A JP 4226882 A JP4226882 A JP 4226882A JP H0429256 B2 JPH0429256 B2 JP H0429256B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase
- loop filter
- pll circuit
- generates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Dram (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042268A JPS58161426A (ja) | 1982-03-17 | 1982-03-17 | デイジタルpll回路のル−プフイルタ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57042268A JPS58161426A (ja) | 1982-03-17 | 1982-03-17 | デイジタルpll回路のル−プフイルタ |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58161426A JPS58161426A (ja) | 1983-09-26 |
| JPH0429256B2 true JPH0429256B2 (cs) | 1992-05-18 |
Family
ID=12631286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57042268A Granted JPS58161426A (ja) | 1982-03-17 | 1982-03-17 | デイジタルpll回路のル−プフイルタ |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58161426A (cs) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0157053A3 (en) * | 1984-03-19 | 1987-09-02 | Western Digital Corporation | High order digital phase lock loop system |
| JP2954070B2 (ja) * | 1997-03-26 | 1999-09-27 | 日本電気アイシーマイコンシステム株式会社 | デジタルpll回路 |
| DE10129783C1 (de) * | 2001-06-20 | 2003-01-02 | Infineon Technologies Ag | Verzögerungsregelkreis |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5546095B2 (cs) * | 1973-03-15 | 1980-11-21 | ||
| JPS56748A (en) * | 1979-06-15 | 1981-01-07 | Fujitsu Ltd | Phase control circuit |
-
1982
- 1982-03-17 JP JP57042268A patent/JPS58161426A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58161426A (ja) | 1983-09-26 |
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