JPH04283951A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04283951A JPH04283951A JP3047160A JP4716091A JPH04283951A JP H04283951 A JPH04283951 A JP H04283951A JP 3047160 A JP3047160 A JP 3047160A JP 4716091 A JP4716091 A JP 4716091A JP H04283951 A JPH04283951 A JP H04283951A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- sealing
- semiconductor device
- brazing material
- lead mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000007789 sealing Methods 0.000 claims abstract description 35
- 238000005219 brazing Methods 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 9
- 238000002844 melting Methods 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims description 11
- 229910020220 Pb—Sn Inorganic materials 0.000 claims description 8
- 229910015363 Au—Sn Inorganic materials 0.000 claims description 6
- 229910017944 Ag—Cu Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 230000005496 eutectics Effects 0.000 claims 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052721 tungsten Inorganic materials 0.000 abstract description 7
- 239000010937 tungsten Substances 0.000 abstract description 7
- 238000001465 metallisation Methods 0.000 abstract description 2
- 239000004020 conductor Substances 0.000 description 16
- 238000000034 method Methods 0.000 description 12
- 229910000679 solder Inorganic materials 0.000 description 5
- 229910017980 Ag—Sn Inorganic materials 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 229910000833 kovar Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 1
- 229910020988 Sn—Ag Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体装置の放熱性が
良好で外形寸法を小さくできるフェイス・ダウン型ピン
・グリッド・アレイパッケージの構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a face-down type pin grid array package that allows a semiconductor device to have good heat dissipation properties and to reduce external dimensions.
【０００２】0002
【従来の技術】従来の半導体装置用パッケージの中でフ
ェース・ダウン型ピン・グリッド・アレイ（以後ＰＧＡ
と略す）パッケージは、最近の高集積化，ハイパワー化
，高密度実装化に適したパッケージである。しかしなが
らこのフェース・ダウン型ＰＧＡパッケージもパッケー
ジ外形寸法をフェース・アップ型ＰＧＡパッケージの大
きさにすることは困難であった。そこでフェース・ダウ
ン型ＰＧＡパッケージの高放熱性とフェース・アップ型
ＰＧＡパッケージの小型な外形寸法との両特性を備えた
ＰＧＡパッケージとして、図６（昭和４９年実用新案登
録出願公告第４５７２９号）、図７（昭和４８年特許出
願広告第３７２２３号）、図８（平成１年特許出願公開
第２５３９４２号）等が提案されている。[Prior Art] Face-down pin grid array (hereinafter referred to as PGA) is used in conventional semiconductor device packages.
) package is suitable for the recent trend toward higher integration, higher power, and higher density packaging. However, it has been difficult to make the package external dimensions of this face-down type PGA package as large as that of the face-up type PGA package. Therefore, as a PGA package that has both the high heat dissipation properties of a face-down type PGA package and the small external dimensions of a face-up type PGA package, we developed a PGA package as shown in Fig. 6 (Utility Model Registration Application Publication No. 45729 of 1972). Figure 7 (Patent Application Publication No. 37223, 1972), Figure 8 (Patent Application Publication No. 253942, 1999), etc. have been proposed.
【０００３】図６に示す昭和４９年実用新案登録出願広
告第４５７２９号はキャップ基板１の中央部のチップ搭
載部３にチップ２が固着されており、チップ２の周辺部
から外周に向ってメタライズ導体配線４が設けられその
端部が接続部５となっている。またキャップ基板１外周
部には１ｍｍ幅程度のメタライズ導体による封止部６が
設けられている。[0003] In 1972 Utility Model Registration Application Advertisement No. 45729 shown in FIG. 6, a chip 2 is fixed to a chip mounting portion 3 in the center of a cap substrate 1, and metallization is applied from the periphery of the chip 2 toward the outer periphery. A conductor wiring 4 is provided, and the end thereof serves as a connection part 5. Further, a sealing portion 6 made of a metallized conductor with a width of about 1 mm is provided on the outer peripheral portion of the cap substrate 1.
【０００４】又、外部リード取付基板７は、接続部５に
対応するようにスルーホール９が設けられ、そこに外部
リード８が挿入されロウ付されてる。封入部６も基板７
の外周にキャップ基板１に対応する様に設けられている
。The external lead mounting board 7 is provided with a through hole 9 corresponding to the connecting portion 5, into which the external lead 8 is inserted and brazed. The enclosure part 6 is also the substrate 7
The cap board 1 is provided on the outer periphery of the cap board 1 so as to correspond to the cap board 1.
【０００５】キャップ基板１にチップ２を接着後、Ａｕ
又はＡｌ線によりチップ電極とステッチとを接続する。
外部リード取付基板７は、接続部５と封入部６にＰｂ−
Ｓｎ−Ａｇ，Ａｕ−Ｓｎ，Ａｇ−Ｓｎ等の低融点ロウ材
をブレージング法により融着させる。これらのキャップ
基板１と外部リード取付基板７を治具により位置決めし
て窒素雰囲気中のベルト炉に通して接続部５と封止部６
とを同時封止したものであった。After bonding the chip 2 to the cap substrate 1, Au
Alternatively, the tip electrode and the stitch are connected by an Al wire. The external lead mounting board 7 has Pb-
A low melting point brazing material such as Sn-Ag, Au-Sn, Ag-Sn is fused by a brazing method. These cap substrate 1 and external lead attachment substrate 7 are positioned using a jig and passed through a belt furnace in a nitrogen atmosphere to form a connecting portion 5 and a sealing portion 6.
It was sealed at the same time.
【０００６】図７に示した昭和４８年特許出願広告第３
７２２３号は、図６と同様の構成であるが異なる点は、
外部リード取付基板７にもチップ２′を固着して実装密
度を２倍にした構造である。図８に示した平成１年特許
出願公開第２５３９４２号は、キャップ基板１上にポリ
イミド配線層１０を設け、この配線層１０のワイヤーボ
ンディング領域外に接続部５が設けられている。又キャ
ップ基板１の外周には１ｍｍ幅程度のメタライズ導体に
よる封止部６が設けられている。外部リード取付基板７
には積層配線によるメタライズ配線導体４が施されてお
り、そのメタライズ配線導体４がスルーホール９により
外部リード取付基板７の上面と下面に導出されている。
外部リード取付基板７の上面には、キャップ基板１に対
応した接続部５と封止部６がメタライズ導体で形成され
ている。外部リード取付基板７の下面は、外部リード取
付けの為のロウ付けパッド１２により外部リード８がロ
ウ付けされている。この外部リード取付基板７の接続部
５と封止部６にはブレージングによりＰｂ−Ｓｎ，Ａｇ
−Ｓｎ，Ａｕ−Ｓｎ等が融着されている。又、キャップ
基板１にはチップ２を接着後Ａｕ線又はＡｌ線によりチ
ップ電極とステッチを接続する。[0006] 1972 patent application advertisement No. 3 shown in Figure 7
No. 7223 has the same configuration as FIG. 6, but the difference is that
This structure doubles the mounting density by fixing the chip 2' to the external lead mounting board 7 as well. In Patent Application Publication No. 253942 of 1999 shown in FIG. 8, a polyimide wiring layer 10 is provided on a cap substrate 1, and a connecting portion 5 is provided outside the wire bonding area of this wiring layer 10. Further, a sealing portion 6 made of a metallized conductor with a width of about 1 mm is provided on the outer periphery of the cap substrate 1. External lead mounting board 7
A metallized wiring conductor 4 made of laminated wiring is applied to the metallized wiring conductor 4, and the metallized wiring conductor 4 is led out to the upper and lower surfaces of the external lead mounting board 7 through a through hole 9. On the upper surface of the external lead mounting board 7, a connecting part 5 and a sealing part 6 corresponding to the cap board 1 are formed of a metallized conductor. External leads 8 are soldered to the lower surface of the external lead mounting board 7 using brazing pads 12 for external lead mounting. The connecting portion 5 and sealing portion 6 of this external lead mounting board 7 are plated with Pb-Sn, Ag.
-Sn, Au-Sn, etc. are fused. Further, after bonding the chip 2 to the cap substrate 1, the chip electrodes and the stitches are connected using Au wires or Al wires.
【０００７】これらのキャップ基板１と外部リード取付
基板を治具により位置決めして、窒素雰囲気中のベルト
炉に通して接続部５と封止部６を同時封止を行うもので
あった。The cap substrate 1 and the external lead attachment substrate were positioned using a jig and passed through a belt furnace in a nitrogen atmosphere to simultaneously seal the connecting portion 5 and the sealing portion 6.
【０００８】以上の様な構造のパッケージを今後ＣＣＢ
・ＰＧＡ（コントロールド・コラップス・ボンディング
ＰＧＡの略）パッケージと呼ぶ。[0008] Packages with the above structure will be used as CCB in the future.
・It is called a PGA (abbreviation for Controlled Collapse Bonding PGA) package.
【０００９】[0009]
【発明が解決しようとする課題】従来のＣＣＢ・ＰＧＡ
パッケージの外部リード取付基板７の接続部５のバンプ
構造は、絶縁基板にメタライズ導体を形成後ディップ法
によるブレージングで接続部上にバンプを形成していた
。しかし、このバンプはメタライズパッド上に球形のバ
ンプを形成し、キャップ基板１と外部リード取付基板７
と治具により位置決めした後に加熱融着して接続と封止
を同時に行う。しかしながら、この時にバンプと封止部
の低融点ロウ材は、ロウ材の融点以上の温度にして接続
を行う為にバンプに掛かる荷重によってロウ材が平面方
向にはみ出して隣りのバンプと短絡したり、封止部ロウ
材のバンプとの短絡、又は外部への流出による治具汚染
あるいはロウ材流出によりロウ材不足となり気密不良な
どが発生する問題点があった。この傾向は現在の様に多
ピン化が進む中でバンプピッチの縮小化が要求されてお
り従来方法による接続は不可能になっている。[Problem to be solved by the invention] Conventional CCB/PGA
The bump structure of the connection part 5 of the external lead attachment board 7 of the package was formed by forming a metallized conductor on an insulating substrate and then forming a bump on the connection part by brazing using a dip method. However, this bump forms a spherical bump on the metallized pad, and the cap board 1 and external lead mounting board 7
After positioning with a jig, connection and sealing are performed at the same time by heating and fusing. However, at this time, the low melting point brazing material between the bump and the sealing part is heated to a temperature higher than the melting point of the brazing material to make the connection, so the load applied to the bump may cause the brazing material to protrude in the plane direction and short circuit with the adjacent bump. There is a problem in that the solder material in the sealing part is short-circuited with the bump, contaminates the jig due to leakage of the filler metal to the outside, or leaks out of the filler metal, resulting in a shortage of filler metal and poor airtightness. This trend is occurring as the number of pins increases, and as a result, the bump pitch is required to be reduced, making it impossible to connect using conventional methods.
【００１０】0010
【課題を解決するための手段】本発明によれば、外部リ
ード取付基板の封止部と接続部のうちすくなくとも接続
部には高融点金属の材料により突部を形成し、その突部
金属上に希金属を被着した後低融点ロウ材をメッキ法に
より厚く被着した構造を有している。[Means for Solving the Problem] According to the present invention, at least the connecting portion of the sealing portion and the connecting portion of the external lead mounting board is formed with a protrusion made of a high melting point metal material, and the protruding portion is formed on the metal material. It has a structure in which a rare metal is applied to the metal, and then a low melting point brazing material is applied thickly by plating.
【００１１】[0011]
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【００１２】図１は本発明の第１の実施例のＣＣＢ・Ｐ
ＧＡパッケージの断面図、図２はこの第１の実施例の部
分拡大断面図、図３は第２の実施例の部分拡大断面図、
図４は第３の実施例の部分拡大断面図３、図５は第４の
実施例の部分拡大断面図である。FIG. 1 shows a CCB-P according to a first embodiment of the present invention.
A sectional view of the GA package, FIG. 2 is a partially enlarged sectional view of the first embodiment, FIG. 3 is a partially enlarged sectional view of the second embodiment,
FIG. 4 is a partially enlarged sectional view 3 of the third embodiment, and FIG. 5 is a partially enlarged sectional view of the fourth embodiment.
【００１３】図１，図２においてキャップ基板１の中央
部のチップ搭載部３にチップ２を固着し、チップ２の周
辺部から外周に向ってメタライズ導体配線４がセラミッ
ク基板内層を通して設けられその端部がスルーホール９
のメタライズ導体を経由して接続部５になっている。ま
た、キャップ基板１の外周部には約１ｍｍ幅のメタライ
ズ導体による封止部６が接続部５を包囲する様に設けら
れている。外部リード取付基板７は、キャップ基板１の
接続部５と封止部６に対応する様にメタライズ導体を設
ける。接続部５にはタングステンペーストを印刷により
０．１〜０．１５ｍｍの高さにタングステン突起１３を
形成し、高さを揃える為に先端部を軽く研磨して平坦性
を出す。この外部リード取付基板７の接続部５の反対面
には外部リード８がロウ付されており、この外部リード
８と接続部５はスルーホール９とメタライズ導体配線４
を通して電気的接続されている。この外部リード取付基
板７とキャップ基板１との金属導体部にはＮｉメッキ５
〜６μｍ，Ａｕメッキ１〜２μｍが施されている、又、
外部リード取付基板７のみにＰｂ−Ｓｎ，Ａｇ−Ｓｎの
メッキを１５〜２０μｍの厚さに、又、Ａｕ−Ｓｎの２
層メッキを封止部６と接続部５のみに１５〜２０μｍ厚
にメッキする。次に治具にキャップ基板１を下側にして
外部リード取付基板７を上側にして取り付ける。この時
に、両基板の接続部５と封止部６は平坦性が良いのでお
互いに接触している。この時に外部リード取付基板７に
荷重を掛けて接触を維持する。このセットした治工具を
窒素雰囲気のベルト炉又はオーブン中で加熱してメッキ
した金属を溶融して接続部５と封止部６を同時に接続す
るものである。In FIGS. 1 and 2, a chip 2 is fixed to a chip mounting portion 3 in the center of a cap substrate 1, and a metallized conductor wiring 4 is provided from the periphery of the chip 2 to the outer periphery through the inner layer of the ceramic substrate. Part is through hole 9
The connection portion 5 is formed via the metallized conductor. Further, a sealing portion 6 made of a metallized conductor having a width of approximately 1 mm is provided on the outer peripheral portion of the cap substrate 1 so as to surround the connecting portion 5 . The external lead attachment board 7 is provided with metallized conductors corresponding to the connection part 5 and the sealing part 6 of the cap board 1. A tungsten protrusion 13 is formed in the connecting part 5 by printing tungsten paste to a height of 0.1 to 0.15 mm, and the tip is lightly polished to make the height uniform and flatten the protrusion 13. An external lead 8 is soldered to the opposite surface of the external lead mounting board 7 from the connection part 5, and the external lead 8 and the connection part 5 are connected to the through hole 9 and the metallized conductor wiring 4.
electrically connected through. The metal conductor portions of the external lead mounting board 7 and the cap board 1 are plated with Ni.
~6μm, Au plating 1~2μm, and
Only the external lead mounting board 7 is plated with Pb-Sn, Ag-Sn to a thickness of 15 to 20 μm, and Au-Sn is plated with a thickness of 15 to 20 μm.
Layer plating is applied only to the sealing portion 6 and the connecting portion 5 to a thickness of 15 to 20 μm. Next, it is attached to a jig with the cap board 1 facing down and the external lead mounting board 7 facing up. At this time, the connecting portion 5 and the sealing portion 6 of both substrates are in contact with each other because of their good flatness. At this time, a load is applied to the external lead attachment board 7 to maintain contact. The set jigs and tools are heated in a belt furnace or oven in a nitrogen atmosphere to melt the plated metal and connect the connecting portion 5 and the sealing portion 6 at the same time.
【００１４】又、外部リード取付基板７の封止部６と接
続部５への低融点ロウ材の被着方法には上述方法以外に
従来方法のブレージング法，印刷法でも可能である。両
基板の接続状態の空間は、接続部５のタングステンメタ
ライズ導体の厚さ０．１〜０．１５ｍｍだけ必ず確保さ
れている。従って、ブレージング法，印刷法では厚くロ
ウ材が被着されて接続時に隣接部との短絡や作業時の取
扱いがむずかしかったが本発明の方法であるとこれらの
問題が解決された。In addition to the above-mentioned method, conventional methods such as brazing and printing can also be used to apply the low melting point brazing material to the sealing portion 6 and the connecting portion 5 of the external lead mounting board 7. The space where both substrates are connected is always secured by the thickness of the tungsten metallized conductor of the connecting portion 5 of 0.1 to 0.15 mm. Therefore, in the brazing method and the printing method, the brazing material is deposited thickly, resulting in short circuits with adjacent parts during connection and difficulty in handling during work, but the method of the present invention solves these problems.
【００１５】図３は本発明の第２の実施例であり、第１
の実施例と異なる点についてのみ述べる。キャップ基板
１の接続部５，封止部６に対応した外部リード取付基板
７にも封止部６，接続部５が設けられており接続部５に
は０．１〜０．２φ径のコバール合金のボール１４をＡ
ｇ−Ｃｕロウ付けしたものである。そして封止部６と接
続部５のコバール合金１４上にＮｉ＋Ａｕメッキをした
後にＡｇ−Ｓｎ，Ｐｂ−Ｓｎ，Ａｕ−Ｓｎなどをメッキ
法により被着するか、又はブレージング法，印刷法でも
可能である。FIG. 3 shows a second embodiment of the present invention.
Only the points different from the embodiment will be described. The external lead mounting board 7 corresponding to the connection part 5 and sealing part 6 of the cap board 1 is also provided with a sealing part 6 and a connection part 5, and the connection part 5 is made of Kovar with a diameter of 0.1 to 0.2φ. Alloy ball 14 A
It is g-Cu brazed. Then, after plating Ni+Au on the Kovar alloy 14 of the sealing part 6 and the connecting part 5, Ag-Sn, Pb-Sn, Au-Sn, etc. can be applied by a plating method, or a brazing method or a printing method can also be used. be.
【００１６】図４は本発明の第３の実施例である。外部
リード取付基板７の接続部５にはＡｇ−Ｃｕペーストを
印刷により塗布し、外部リード８をＡｇ−Ｃｕロウ付け
すると同時にＡｇ−Ｃｕペーストを融着させてＡｇ−Ｃ
ｕボール１５を形成する。この後の表面処理と低融点ロ
ウ材の被着方法は、第１，第２の実施例と同じである。FIG. 4 shows a third embodiment of the present invention. Ag-Cu paste is applied by printing to the connection part 5 of the external lead mounting board 7, and the Ag-Cu paste is fused at the same time as the external lead 8 is brazed with Ag-Cu.
A u-ball 15 is formed. The subsequent surface treatment and the method of applying the low melting point brazing material are the same as in the first and second embodiments.
【００１７】図５は本発明の第４の実施例であり、接続
部５はタングステン突起１３と封止部６は０．１〜０．
１５ｍｍの高さにタングステンペースト印刷により形成
し、焼成後に平坦度を出す為に軽く研磨した後にＮｉ＋
Ａｕメッキをそれぞれ５〜６μｍと１．５μｍを施す。
その後にＰｂ−Ｓｎ合金メッキを２０〜３０μｍの厚に
メッキする。この構造であると封止部にプリフォームを
使用せずとも接続と封止を行う事ができる。更に、外部
リード取付基板７にＰｂ−Ｓｎ半田メッキをする方法で
あると外部リード８にもＰｂ−Ｓｎ半田メッキがなされ
てプリント板実装時の予備半田が不用になる。FIG. 5 shows a fourth embodiment of the present invention, in which the connection portion 5 has a tungsten protrusion 13 and the sealing portion 6 has a thickness of 0.1 to 0.0.
Formed by tungsten paste printing to a height of 15 mm, and lightly polished to achieve flatness after firing, Ni+
Au plating is applied to a thickness of 5 to 6 μm and 1.5 μm, respectively. After that, Pb-Sn alloy plating is applied to a thickness of 20 to 30 μm. With this structure, connection and sealing can be performed without using a preform for the sealing part. Furthermore, if the external lead mounting board 7 is plated with Pb-Sn solder, the external leads 8 are also plated with Pb-Sn solder, eliminating the need for preliminary soldering when mounting the printed circuit board.
【００１８】[0018]
【発明の効果】以上説明したように、本発明は外部リー
ド取付基板の接続部又は接続部と封止部に突起を設けて
キャップ基板と外部リード取付基板の両基板間にすき間
を設けることができる。このすき間によって接続，封止
作業時の位置決めと荷重を掛けながらの加熱融着におい
てロウ材の広がりによるロウ材流れと隣接接続部の短絡
が防止できる。又、接続部，封止部のロウ材被着方法に
メッキ法を用いる事によって被着工程の簡略化とパッケ
ージのフラックス残り汚染等が解決できる。更に、接続
部にＰｂ−Ｓｎ半田，封止部にＡｕ−Ｓｎロウ材を使い
分ける事によってプリント板へ本半導体装置を半田付け
する時に接続部の信頼性を損なうことがない。又、外部
リードにＰｂ−Ｓｎ半田メッキが施されているので外部
リードの予備半田が省略できると共にプリント板との半
田付け作業が向上する複数の効果を有する。[Effects of the Invention] As explained above, the present invention provides a projection on the connecting portion of the external lead mounting board or the connecting portion and the sealing portion to create a gap between the cap board and the external lead mounting board. can. This gap prevents flow of the brazing material due to spreading of the brazing material during positioning during connection and sealing work, and heat fusing while applying a load, and short-circuiting of adjacent joints. Furthermore, by using a plating method to apply the brazing material to the connecting portion and the sealing portion, the adhesion process can be simplified and the problem of contamination caused by residual flux on the package can be solved. Furthermore, by selectively using Pb--Sn solder for the connecting portion and Au--Sn brazing material for the sealing portion, the reliability of the connecting portion is not impaired when the present semiconductor device is soldered to a printed board. Furthermore, since the external leads are plated with Pb-Sn solder, preliminary soldering of the external leads can be omitted and the soldering work with the printed board can be improved.
【図１】本発明による第１の実施例を示す断面図FIG. 1 is a sectional view showing a first embodiment of the present invention.
【図２
】図１の部分拡大断面図[Figure 2
] Partially enlarged sectional view of Figure 1
【図３】本発明による第２の実施例の部分拡大断面図FIG. 3 is a partially enlarged sectional view of a second embodiment according to the present invention.
【
図４】本発明による第３の実施例の部分拡大断面図[
FIG. 4: Partially enlarged sectional view of a third embodiment according to the present invention
【図
５】本発明による第４の実施例の部分拡大断面図FIG. 5 is a partially enlarged sectional view of a fourth embodiment according to the present invention.
【図６
】それぞれ従来例を示す断面図[Figure 6
】Cross-sectional views showing conventional examples
【図７】それぞれ従来例を示す断面図[Figure 7] Cross-sectional views showing conventional examples
【図８】それぞれ従来例を示す断面図[Fig. 8] Cross-sectional views showing conventional examples
１ キャップ基板 ２ チップ ３ チップ搭載部 ４ メタライズ導体配線 ５ 接続部 ６ 封止部 ７ 外部リード取付基板 ８ 外部リード ９ スルーホール １０ ポリイミド配線 １２ ロウ付パッド １３ タングステン突起 １４ コバールボール １５ Ａｇ−Ｃｕボール 1 Cap board 2 Chip 3 Chip mounting part 4 Metallized conductor wiring 5 Connection part 6 Sealing part 7 External lead mounting board 8 External lead 9 Through hole 10 Polyimide wiring 12 Pad with brazing 13 Tungsten protrusion 14 Kobar Ball 15 Ag-Cu ball
Claims (5)
部と配線層とを有するキャップ基板と、封止部と接続部
と配線層とを有し外部リードガ取付けられた外部リード
取付基板とが封止部同士および接続部同士が接続されて
封止された半導体装置において、外部リード取付基板の
接続部に金属による凸部を形成し、接続用ロウ材で前記
キャップ基板に接続されている事を特徴とする半導体装
置。1. A cap substrate on which a semiconductor element is mounted and has a sealing part, a connection part, and a wiring layer; an external lead mounting board having a sealing part, a connection part, and a wiring layer and having an external lead mounted thereon; In a semiconductor device in which the sealed parts are connected to each other and the connecting parts are connected to each other and sealed, a metal convex part is formed at the connecting part of the external lead mounting board, and is connected to the cap board with a connecting brazing material. A semiconductor device characterized by:
ウ付して形成されている事を特徴とする請求項１記載の
半導体装置。2. The semiconductor device according to claim 1, wherein the metal convex portion is formed by brazing a metal ball.
材により突起を形成したものである事を特徴とする請求
項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the metal convex portion is a protrusion formed from Ag-Cu brazing material.
−Ｓｎ，Ａｕ−Ｓｎ等の合金メッキ又は多層メッキを被
着して形成されたものである事を特徴とする請求項１記
載の半導体装置。4. The brazing material for connection is Pb-Sn, Ag
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed by applying alloy plating such as -Sn or Au-Sn or multilayer plating.
低融点ロウ材で接続し、前記封止部は共晶Ａｕ−Ｓｎプ
リフォームで封止されている事を特徴とする請求項１，
２又は３記載の半導体装置。5. The connecting portion is connected by a low melting point brazing material deposited by plating, and the sealing portion is sealed with a eutectic Au-Sn preform.
3. The semiconductor device according to 2 or 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4716091A JP2730304B2 (en) | 1991-03-13 | 1991-03-13 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4716091A JP2730304B2 (en) | 1991-03-13 | 1991-03-13 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04283951A true JPH04283951A (en) | 1992-10-08 |
| JP2730304B2 JP2730304B2 (en) | 1998-03-25 |
Family
ID=12767331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4716091A Expired - Lifetime JP2730304B2 (en) | 1991-03-13 | 1991-03-13 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2730304B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154642A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device |
| JPS644051A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Formation of bump of hand drum shape |
| JPH01253942A (en) * | 1988-04-04 | 1989-10-11 | Hitachi Ltd | Semiconductor package and computer using the same |
-
1991
- 1991-03-13 JP JP4716091A patent/JP2730304B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154642A (en) * | 1984-01-25 | 1985-08-14 | Hitachi Ltd | Semiconductor device |
| JPS644051A (en) * | 1987-06-26 | 1989-01-09 | Hitachi Ltd | Formation of bump of hand drum shape |
| JPH01253942A (en) * | 1988-04-04 | 1989-10-11 | Hitachi Ltd | Semiconductor package and computer using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2730304B2 (en) | 1998-03-25 |
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