JPH04335542A - Electrode for semiconductor device and mounted body - Google Patents

Electrode for semiconductor device and mounted body

Info

Publication number
JPH04335542A
JPH04335542A JP3105476A JP10547691A JPH04335542A JP H04335542 A JPH04335542 A JP H04335542A JP 3105476 A JP3105476 A JP 3105476A JP 10547691 A JP10547691 A JP 10547691A JP H04335542 A JPH04335542 A JP H04335542A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
solder
circuit board
bonding layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3105476A
Other languages
Japanese (ja)
Other versions
JP2633745B2 (en
Inventor
Yoshihiro Bessho
芳宏 別所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3105476A priority Critical patent/JP2633745B2/en
Publication of JPH04335542A publication Critical patent/JPH04335542A/en
Application granted granted Critical
Publication of JP2633745B2 publication Critical patent/JP2633745B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a mounted body and an electrode for a semiconductor device in which the device can be easily connected to a circuit board with high reliability. CONSTITUTION:A bump electrode 3 having two-stage protrusion shape of a pedestal part and a top part, is provided on an aluminum electrode pad 2 of an IC board 1 of a semiconductor device, an electrode structure in which a solder bonding layer 4 is formed on the top part of the electrode 3, is provided, and a mounting structure in which the device is electrically connected to a terminal electrode 7 on a circuit board 6 through the layer 4, is provided. An extension of the solder bonding layer can be controlled by the electrode 3 having the two-stage protrusion shape, and bonding at a fine pitch can be realized.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、半導体装置を回路基板
に実装する際の電極構造に関するものであり、特にフェ
ースダウンで実装してなる半導体装置用電極と実装体に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode structure for mounting a semiconductor device on a circuit board, and more particularly to an electrode and a mounting body for a semiconductor device mounted face-down.

【0002】0002

【従来の技術】従来、半導体装置の回路基板上への実装
には半田付けがよく利用されていたが、近年、半導体装
置のパッケージの小型化と接続端子数の増加により、接
続端子間隔が狭くなり、従来の半田付け技術で対処する
ことが次第に困難になってきた。
[Prior Art] In the past, soldering was often used to mount semiconductor devices on circuit boards, but in recent years, as semiconductor device packages have become smaller and the number of connection terminals has increased, the spacing between connection terminals has become narrower. It has become increasingly difficult to deal with this problem using conventional soldering techniques.

【0003】そこで、最近では裸の半導体装置を回路基
板上に直付けして実装面積の小型化と効率的使用を図ろ
うとする方法が考案されてきた。
[0003]Recently, therefore, a method has been devised in which a bare semiconductor device is directly attached to a circuit board in order to reduce the mounting area and to achieve efficient use.

【0004】なかでも、半導体装置を回路基板に接続す
るに際し、あらかじめ半導体装置のアルミ電極パッド上
に密着金属や拡散防止金属の蒸着膜とこの上にメッキに
より形成した半田層とからなる電極構造を有する半導体
装置を下向き(フェースダウン)にして、高温に加熱し
て半田を回路基板の端子電極に融着する実装構造が、接
続後の機械的強度が強く、接続が一括にできることなど
から有効な方法であるとされている。(例えば、工業調
査会、1980年1月15日発行、日本マイクロエレク
トロニクス協会編、『IC化実装技術』)以下図面を参
照しながら、上述した従来の半導体装置の電極構造と実
装構造の一例について説明する。
In particular, when connecting a semiconductor device to a circuit board, an electrode structure consisting of a vapor-deposited film of an adhesive metal or a diffusion-preventing metal and a solder layer formed by plating on the aluminum electrode pad of the semiconductor device is prepared in advance. The mounting structure, in which the semiconductor device is placed face down and heated to a high temperature to fuse the solder to the terminal electrodes of the circuit board, is effective because it has strong mechanical strength after connection and can be connected all at once. It is said to be a method. (For example, Kogyo Kenkyukai, January 15, 1980, edited by Japan Microelectronics Association, "IC Mounting Technology") Below is an example of the electrode structure and mounting structure of the conventional semiconductor device mentioned above, with reference to the drawings. explain.

【0005】(図3)は従来の半田バンプ電極を有する
半導体装置の電極構造の概略説明図であり、(図4)は
上記半導体装置の実装構造の概略説明図である。
FIG. 3 is a schematic explanatory diagram of the electrode structure of a semiconductor device having conventional solder bump electrodes, and FIG. 4 is a schematic explanatory diagram of the mounting structure of the semiconductor device.

【0006】(図3)において、8は半導体装置のIC
基板であり、9はアルミ電極パッドである。10は密着
金属膜であり、11は拡散防止金属膜である。12は半
田突起であり、13はパッシベーション膜である。(図
4)において、14は回路基板であり、15は端子電極
である。
In (FIG. 3), 8 is an IC of a semiconductor device.
It is a substrate, and 9 is an aluminum electrode pad. 10 is an adhesive metal film, and 11 is a diffusion prevention metal film. 12 is a solder protrusion, and 13 is a passivation film. In (FIG. 4), 14 is a circuit board, and 15 is a terminal electrode.

【0007】以上のように構成された従来の半田バンプ
電極を有する半導体装置の電極構造と実装構造について
、以下その概略を説明する。
An outline of the electrode structure and mounting structure of a semiconductor device having a conventional solder bump electrode constructed as described above will be explained below.

【0008】まず、半導体装置のIC基板8のアルミ電
極パッド9上にCuなどの密着金属膜10およびCrな
どの拡散防止金属膜11を蒸着により形成する。その後
、電極部以外をフォトレジストで覆い、メッキ法により
半田を拡散防止金属膜11上に析出させて半田リフロー
を行うことにより、半田突起12を形成して(図3)の
半田バンプ電極を得る。
First, an adhesion metal film 10 such as Cu and a diffusion prevention metal film 11 such as Cr are formed by vapor deposition on the aluminum electrode pad 9 of the IC substrate 8 of the semiconductor device. Thereafter, parts other than the electrode part are covered with photoresist, and solder is deposited on the diffusion prevention metal film 11 by a plating method, and solder reflow is performed to form solder protrusions 12 to obtain the solder bump electrode (FIG. 3). .

【0009】さらに、以上のようにして得た半田バンプ
電極を有する半導体装置を、回路基板14の所定の位置
に位置合わせを行ってフェースダウンで積載した後、2
00〜300℃の高温に加熱して半田突起12を溶融し
、端子電極15に融着することによって半導体装置の実
装を行うものである。
Furthermore, after aligning the semiconductor device having the solder bump electrodes obtained as described above to a predetermined position on the circuit board 14 and loading it face down,
The semiconductor device is mounted by heating to a high temperature of 00 to 300° C. to melt the solder projections 12 and fuse them to the terminal electrodes 15.

【0010】0010

【発明が解決しようとする課題】しかしながら上記のよ
うな半田バンプ電極を有する半導体装置の電極構造や実
装構造においては、 1.半導体装置のアルミ電極パッド上に密着金属膜や拡
散防止金属膜が必要で、電極構造が複雑となり、汎用性
に欠ける。
[Problems to be Solved by the Invention] However, in the electrode structure and mounting structure of a semiconductor device having solder bump electrodes as described above, 1. An adhesive metal film or a diffusion prevention metal film is required on the aluminum electrode pad of a semiconductor device, making the electrode structure complicated and lacking in versatility.

【0011】2.高温に加熱して半田を溶融して端子電
極と接続する際に、IC基板と回路基板とのギャップを
維持することが出来ないため、半田が広がって隣接とシ
ョートする危険がある。などといった課題を有していた
2. When heating the IC board to a high temperature to melt the solder and connect it to the terminal electrode, it is not possible to maintain a gap between the IC board and the circuit board, so there is a risk that the solder will spread and cause a short circuit with the adjacent circuit board. There were issues such as these.

【0012】本発明は上記の課題に鑑みてなされたもの
であり、その目的とするところは、半導体装置と回路基
板とを容易に信頼性良く接続することのできる半導体装
置の電極構造と実装構造を提供することにある。
The present invention has been made in view of the above-mentioned problems, and its object is to provide an electrode structure and a mounting structure for a semiconductor device that can easily and reliably connect the semiconductor device and a circuit board. Our goal is to provide the following.

【0013】[0013]

【課題を解決するための手段】本発明は上記の課題を解
決するため、フェースダウンで回路基板に実装する半導
体装置において、半導体装置のアルミ電極パッド部上に
台座部と頂上部の2段突起状のバンプ電極を備え、上記
2段突起状のバンプ電極の頂上部にのみ無機接合層を形
成した電極構造を有し、かつ、半導体装置のアルミ電極
パッド部上の2段突起状のバンプ電極を無機接合層を介
して回路基板上の端子電極に電気的に接続する実装構造
を有することを特徴として、信頼性の高い半導体装置の
回路基板への実装を実現しようとするものである。
[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides, in a semiconductor device mounted face-down on a circuit board, a two-stage protrusion of a pedestal portion and a top portion on an aluminum electrode pad portion of the semiconductor device. The bump electrode has an electrode structure in which an inorganic bonding layer is formed only on the top of the two-step protruding bump electrode, and the two-step protruding bump electrode is on an aluminum electrode pad portion of a semiconductor device. The present invention is characterized by having a mounting structure in which a semiconductor device is electrically connected to a terminal electrode on a circuit board via an inorganic bonding layer, and is intended to realize highly reliable mounting of a semiconductor device on a circuit board.

【0014】[0014]

【作用】本発明は、半導体装置のアルミ電極パッド部上
に直接形成した2段突起形状のバンプ電極の頂上部にの
み無機接合層を形成した電極構造を有することにより、
半導体装置を回路基板の端子電極に接合する際に接合層
が隣接とショートすることなく微細ピッチでの接合が可
能となり、かつ、信頼性の高い半導体装置の実装構造が
実現できる。
[Operation] The present invention has an electrode structure in which an inorganic bonding layer is formed only on the top of a two-step protrusion-shaped bump electrode formed directly on an aluminum electrode pad portion of a semiconductor device.
When a semiconductor device is bonded to a terminal electrode of a circuit board, the bonding layer can be bonded at a fine pitch without shorting with the adjacent layer, and a highly reliable semiconductor device mounting structure can be realized.

【0015】[0015]

【実施例】以下、本発明の一実施例の半導体装置用電極
と実装体について、図面を参照しながら説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An electrode for a semiconductor device and a mounting body according to an embodiment of the present invention will be described below with reference to the drawings.

【0016】(図1)は、本発明の一実施例における半
導体装置の電極構造の概略説明図であり、(図2)は、
上記実施例の電極構造を有する半導体装置の実装構造の
概略説明図である。
(FIG. 1) is a schematic explanatory diagram of the electrode structure of a semiconductor device in one embodiment of the present invention, and (FIG. 2) is a
FIG. 2 is a schematic explanatory diagram of a mounting structure of a semiconductor device having the electrode structure of the above embodiment.

【0017】(図1)において、1は半導体装置のIC
基板であり、2はアルミ電極パッドである。3は台座部
と頂上部からなる2段突起状のバンプ電極であり、4は
2段突起形状のバンプ電極の頂上部にのみ形成した半田
接合層である。5はパッシベーション膜である。(図2
)において、6は回路基板であり、7は端子電極である
In (FIG. 1), 1 is an IC of a semiconductor device.
It is a substrate, and 2 is an aluminum electrode pad. Reference numeral 3 denotes a two-step protruding bump electrode consisting of a base portion and a top portion, and numeral 4 represents a solder bonding layer formed only on the top portion of the two-step protruding bump electrode. 5 is a passivation film. (Figure 2
), 6 is a circuit board, and 7 is a terminal electrode.

【0018】以上のように構成された半導体装置の電極
構造と実装構造について、以下図面を用いて説明する。
The electrode structure and mounting structure of the semiconductor device constructed as above will be explained below with reference to the drawings.

【0019】まず、半導体装置のIC基板1のアルミ電
極パッド2上に通常のワイヤボンディング技術と同様に
Auワイヤの先端のAuボールを固着した後、Auワイ
ヤを切断することにより台座部と頂上部を有する2段突
起状のバンプ電極3を形成する。
First, an Au ball at the tip of an Au wire is fixed onto an aluminum electrode pad 2 of an IC substrate 1 of a semiconductor device in the same manner as in a normal wire bonding technique, and then the pedestal portion and top portion are separated by cutting the Au wire. A bump electrode 3 having a two-stage protrusion shape is formed.

【0020】その後、2段突起状のバンプ電極3の頂上
部にのみ、半田接合層4を転写法や印刷法によって形成
する。この時、必要に応じて半田リフローを行う。
[0020] Thereafter, a solder bonding layer 4 is formed only on the top portion of the two-step protruding bump electrode 3 by a transfer method or a printing method. At this time, solder reflow is performed if necessary.

【0021】上記により、汎用の半導体装置のアルミ電
極パッド2上に2段突起状のバンプ電極3と半田接合層
4からなる電極構造が容易に得られる。
As described above, an electrode structure consisting of a two-step protruding bump electrode 3 and a solder bonding layer 4 can be easily obtained on an aluminum electrode pad 2 of a general-purpose semiconductor device.

【0022】本発明の半導体装置の電極構造は、上記し
た方法により、通常のワイヤボンディング装置で2段突
起形状のバンプ電極を得ることが出来るため、通常のア
ルミ電極パッドを有する汎用の半導体装置を用いること
が可能となり、極めて汎用性が高い。
In the electrode structure of the semiconductor device of the present invention, a bump electrode having a two-stage protrusion can be obtained using a normal wire bonding device by the method described above. It can be used and is extremely versatile.

【0023】さらに、以上のようにして得た電極構造を
有する半導体装置を、回路基板6の所定の位置に位置合
わせを行ってフェースダウンで積載した後、200〜3
00℃の高温に加熱して半田接合層4を溶融し、端子電
極7に融着することによって半導体装置の実装を行う。
Furthermore, after aligning the semiconductor device having the electrode structure obtained as described above to a predetermined position on the circuit board 6 and mounting it face down,
The semiconductor device is mounted by heating to a high temperature of 00° C. to melt the solder bonding layer 4 and fusing it to the terminal electrode 7.

【0024】この高温に加熱して半田接合層4を溶融し
て端子電極7と接続する際に、IC基板1と回路基板6
とのギャップを2段突起状のバンプ電極3により維持す
ることが出来、かつ、頂上部にのみ半田接合層4を形成
しているすることが出来るため、半田の広がりを規制す
ることが可能となって隣接とショートする危険がなく、
微細ピッチでの接続が可能な半導体装置の実装構造が得
られる。
When heating to this high temperature to melt the solder bonding layer 4 and connect it to the terminal electrode 7, the IC board 1 and the circuit board 6
The gap can be maintained by the two-step protruding bump electrode 3, and the solder bonding layer 4 can be formed only at the top, making it possible to restrict the spread of solder. There is no risk of short-circuiting with the adjacent
A semiconductor device mounting structure that allows connection at a fine pitch can be obtained.

【0025】本発明の半導体装置の実装構造は、上記し
た方法により、従来の半田バンプ電極による実装構造で
は不可能であった半田の広がりの規制が2段突起状のバ
ンプ電極を用いることで可能となり、極めて安定で信頼
性良く、かつ、高密度に半導体装置を実装できる。
[0025] In the semiconductor device mounting structure of the present invention, by using the above-described method, it is possible to control the spread of solder, which was impossible with the conventional mounting structure using solder bump electrodes, by using the two-step protruding bump electrodes. Therefore, semiconductor devices can be mounted extremely stably and reliably with high density.

【0026】なお、本実施例では2段突起状のバンプ電
極をワイヤボンディング装置を用いて形成するとしたが
、その形状が2段突起状であればメッキなど他の方法で
形成しても良い。
In this embodiment, the two-step protruding bump electrode is formed using a wire bonding device, but as long as the bump electrode has a two-step protruding shape, it may be formed by other methods such as plating.

【0027】また、バンプ電極をAuからなるものとし
たが、その材質はAuに限られる物でなく、例えば、C
uなど他の金属から形成しても良い。
Furthermore, although the bump electrode is made of Au, the material is not limited to Au; for example, C
It may be formed from other metals such as u.

【0028】さらに、2段突起状のバンプ電極の頂上部
に形成する半田接合層は、半田ペーストを転写や印刷に
よって形成しても良い。
Furthermore, the solder bonding layer formed on the top of the two-stage bump electrode may be formed by transferring or printing a solder paste.

【0029】[0029]

【発明の効果】以上に説明したように、本発明の半導体
装置用電極と実装体によれば、通常のワイヤボンディン
グ装置で半導体装置のアルミ電極パッド部上に直接形成
することができるため、汎用の半導体装置を用いること
が可能となり、極めて汎用性が高い。
Effects of the Invention As explained above, according to the electrode for a semiconductor device and the mounting body of the present invention, it can be formed directly on the aluminum electrode pad portion of a semiconductor device using a normal wire bonding machine, so that it can be used for general purpose use. This makes it possible to use several semiconductor devices, making it extremely versatile.

【0030】さらに、2段突起形状のバンプ電極の頂上
部にのみ無機接合層を形成した電極構造を有することに
より、半導体装置を回路基板の端子電極に接合する際に
無機接合層の広がりの規制が可能となり、無機接合層が
隣接とショートすることなく微細ピッチでの接合が可能
な実装構造となり、極めて安定で信頼性良く、かつ、高
密度に半導体装置を実装できる。
Furthermore, by having an electrode structure in which an inorganic bonding layer is formed only on the top of the bump electrode in the shape of a two-step protrusion, it is possible to control the spread of the inorganic bonding layer when bonding a semiconductor device to a terminal electrode of a circuit board. This makes it possible to create a mounting structure in which the inorganic bonding layer can be bonded at a fine pitch without shorting with the adjacent layer, making it possible to mount semiconductor devices extremely stably, reliably, and with high density.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の一実施例における半導体装置の電極の
概略説明図である。
FIG. 1 is a schematic explanatory diagram of an electrode of a semiconductor device in an embodiment of the present invention.

【図2】本発明の一実施例の電極構造を有する半導体装
置の実装体の概略説明図である。
FIG. 2 is a schematic explanatory diagram of a semiconductor device package having an electrode structure according to an embodiment of the present invention.

【図3】従来の半田バンプ電極を有する半導体装置の電
極の概略説明図である。
FIG. 3 is a schematic explanatory diagram of an electrode of a semiconductor device having a conventional solder bump electrode.

【図4】従来の半田バンプ電極を有する半導体装置の実
装体の概略説明図である。
FIG. 4 is a schematic explanatory diagram of a semiconductor device package having conventional solder bump electrodes.

【符号の説明】[Explanation of symbols]

1  半導体装置のIC基板 2  アルミ電極パッド 3  2段突起状のバンプ電極 4  半田接合層 5  パッシベーション膜 6  回路基板 7  端子電極 8  半導体装置のIC基板 9  アルミ電極パッド 10  密着金属膜 11  拡散防止金属膜 12  半田突起 13  パッシベーション膜 14  回路基板 15  端子電極 1 IC substrate for semiconductor devices 2 Aluminum electrode pad 3. Two-step protruding bump electrode 4 Solder joint layer 5 Passivation film 6 Circuit board 7 Terminal electrode 8 IC substrate of semiconductor device 9 Aluminum electrode pad 10 Adhesive metal film 11 Diffusion prevention metal film 12 Solder protrusion 13 Passivation film 14 Circuit board 15 Terminal electrode

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】  フェースダウンで回路基板に実装する
半導体装置の電極において、半導体装置のアルミ電極パ
ッド部上に台座部と頂上部の2段突起状のバンプ電極を
備え、上記2段突起状のバンプ電極の頂上部にのみ無機
接合層を形成したことを特徴とする半導体装置用電極。
1. An electrode for a semiconductor device that is mounted face-down on a circuit board, comprising a two-step protruding bump electrode having a pedestal portion and a top portion on an aluminum electrode pad portion of the semiconductor device; An electrode for a semiconductor device, characterized in that an inorganic bonding layer is formed only on the top of a bump electrode.
【請求項2】  2段突起状のバンプ電極がAuからな
ることを特徴とする請求項1記載の半導体装置用電極。
2. The electrode for a semiconductor device according to claim 1, wherein the two-step protruding bump electrode is made of Au.
【請求項3】  2段突起状のバンプ電極がワイヤボン
ディング装置でAuワイヤにより形成されることを特徴
とする請求項1項記載の半導体装置の電極構造。
3. The electrode structure for a semiconductor device according to claim 1, wherein the two-step protruding bump electrode is formed of Au wire using a wire bonding device.
【請求項4】  無機接合層が半田からなることを特徴
とする請求項1記載の半導体装置用電極。
4. The electrode for a semiconductor device according to claim 1, wherein the inorganic bonding layer is made of solder.
【請求項5】  フェースダウンで回路基板に実装する
半導体装置の実装体において、半導体装置のアルミ電極
パッド部上の2段突起状のバンプ電極を無機接合層を介
して回路基板上の端子電極に電気的に接続することを特
徴とする半導体装置用実装体。
5. In a semiconductor device mounting body that is mounted face-down on a circuit board, a two-step protruding bump electrode on an aluminum electrode pad portion of the semiconductor device is connected to a terminal electrode on the circuit board via an inorganic bonding layer. A mounting body for a semiconductor device characterized by electrical connection.
【請求項6】  2段突起状のバンプ電極がAuからな
ることを特徴とする請求項5記載の半導体装置用実装体
6. The semiconductor device mounting body according to claim 5, wherein the two-step protruding bump electrode is made of Au.
【請求項7】  2段突起状のバンプ電極がワイヤボン
ディング装置でAuワイヤにより形成されることを特徴
とする請求項5項記載の半導体装置用実装体。
7. The semiconductor device mounting body according to claim 5, wherein the two-step protruding bump electrode is formed of Au wire using a wire bonding device.
【請求項8】  無機接合層が半田からなることを特徴
とする請求項5記載の半導体装置用実装体。
8. The semiconductor device mounting body according to claim 5, wherein the inorganic bonding layer is made of solder.
JP3105476A 1991-05-10 1991-05-10 Semiconductor device package Expired - Fee Related JP2633745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3105476A JP2633745B2 (en) 1991-05-10 1991-05-10 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3105476A JP2633745B2 (en) 1991-05-10 1991-05-10 Semiconductor device package

Publications (2)

Publication Number Publication Date
JPH04335542A true JPH04335542A (en) 1992-11-24
JP2633745B2 JP2633745B2 (en) 1997-07-23

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ID=14408650

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109965A (en) * 2005-10-14 2007-04-26 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method
US8483523B2 (en) 2009-09-14 2013-07-09 Ricoh Company, Ltd. Optical waveguide electro-optic device and process of manufacturing optical waveguide electro-optic device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163950A (en) * 1988-12-16 1990-06-25 Matsushita Electric Ind Co Ltd Mounting of semiconductor device
JPH045844A (en) * 1990-04-23 1992-01-09 Nippon Mektron Ltd Multilayer circuit board for mounting ic and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02163950A (en) * 1988-12-16 1990-06-25 Matsushita Electric Ind Co Ltd Mounting of semiconductor device
JPH045844A (en) * 1990-04-23 1992-01-09 Nippon Mektron Ltd Multilayer circuit board for mounting ic and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109965A (en) * 2005-10-14 2007-04-26 Oki Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP4738971B2 (en) * 2005-10-14 2011-08-03 Okiセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
US8483523B2 (en) 2009-09-14 2013-07-09 Ricoh Company, Ltd. Optical waveguide electro-optic device and process of manufacturing optical waveguide electro-optic device

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