JPH04282867A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH04282867A
JPH04282867A JP4392791A JP4392791A JPH04282867A JP H04282867 A JPH04282867 A JP H04282867A JP 4392791 A JP4392791 A JP 4392791A JP 4392791 A JP4392791 A JP 4392791A JP H04282867 A JPH04282867 A JP H04282867A
Authority
JP
Japan
Prior art keywords
silicon
wafer
type
silicon wafer
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4392791A
Other languages
Japanese (ja)
Inventor
Kiyoshi Irino
清 入野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4392791A priority Critical patent/JPH04282867A/en
Publication of JPH04282867A publication Critical patent/JPH04282867A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To make it possible to manufacture an N-type SOI(Silicon On Insulator) substrate by a method wherein a low-cost P-type silicon wafer is laminated on other low-cost P-type silicon wafer, the other P-type silicon wafer is polished thin, the surfaces of the silicon wafers are respectively covered with silicon oxide films and the wafers are heat-treated. CONSTITUTION:Two sheets of P-type silicon wafers 1 and 2 are prepared, the surface of the wafer 1, for example, is thermally oxidized and a silicon oxide film 3 of a thickness of about 0.5mum is formed. The wafer 1 form with the film 3 is superposed on the wafer 2 and the wafers 1 and 2 are heat-treated at 1100 deg.C, for example, in an oxidizing atmosphere. Thereby, the wafer 1 is jointed on the wafer 2. Then, the wafer 2 is made thin to a thickness of 10mum or thereabouts or thinner by polishing. Then, silicon oxide films 4 and 5 of a thickness of 1000Angstrom are respectively formed on the respective open surfaces of the wafers 1 and 2. Then, when the wafers 1 and 2 are heat-treated at 1100 deg.C in a dry nitrogen atmosphere, for example, the wafer 1 is converted into an N-type.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明はSOI(Silicon
 on Insulator) 構造の半導体装置の製
造方法, とくに,n型の半導体層を有するSOI 基
板を低コストで提供可能とする方法に関する。
[Industrial Application Field] The present invention relates to SOI (Silicon
The present invention relates to a method for manufacturing a semiconductor device having an n-type semiconductor layer (on insulator) structure, and particularly to a method for providing an SOI substrate having an n-type semiconductor layer at low cost.

【0002】0002

【従来の技術】放射線によるソフトエラー, あるいは
,CMOSトランジスタのラッチアップ防止等に関連し
てSOI 構造の半導体装置が期待されている。現在の
ところ, 二枚のシリコンウエハを貼り合わせてSOI
 基板を作製する方法が最も実用化に近い。
2. Description of the Related Art Semiconductor devices having an SOI structure are expected to be used to prevent soft errors caused by radiation or latch-up of CMOS transistors. Currently, SOI is achieved by bonding two silicon wafers together.
The method of manufacturing a substrate is the closest to practical application.

【0003】従来, n型のSOI 基板を作製する場
合には,支持基板となるp型のシリコンウエハにn型の
シリコンウエハを貼り合わせ, このn型シリコンウエ
ハを数10μm以下に研磨する方法が採られている。
[0003] Conventionally, when producing an n-type SOI substrate, there is a method of bonding an n-type silicon wafer to a p-type silicon wafer that serves as a support substrate, and polishing this n-type silicon wafer to a size of several tens of micrometers or less. It is taken.

【0004】0004

【発明が解決しようとする課題】上記のように, 貼り
合わせ方法による従来のSOI 基板は, シリコンウ
エハの少なくとも一方に, n型を用いる必要があり,
 その結果, このようなSOI 基板を用いて製造さ
れる集積回路等の半導体装置も高価になってしまう問題
があった。これは, シリコンウエハの元となる結晶の
引き上げにおいて, n型結晶の方が, p型結晶の2
〜3倍の時間を要するためにコスト高になるからである
[Problems to be Solved by the Invention] As mentioned above, in the conventional SOI substrate using the bonding method, it is necessary to use n-type for at least one of the silicon wafers.
As a result, there is a problem in that semiconductor devices such as integrated circuits manufactured using such an SOI substrate also become expensive. This is because when pulling the crystal that is the source of a silicon wafer, the n-type crystal is better than the p-type crystal.
This is because it requires up to three times as much time, resulting in higher costs.

【0005】本発明は, 安価なp型シリコンウエハを
貼り合わせることによってn型のSOI基板を作製可能
とし, これにより, 上記問題点を解決することを目
的とする。
The present invention aims to solve the above problems by making it possible to fabricate an n-type SOI substrate by bonding together inexpensive p-type silicon wafers.

【0006】[0006]

【課題を解決するための手段】上記目的は, p型の第
1のシリコンウエハの一表面に酸化シリコン膜を形成し
, 該酸化シリコン膜を介して該第1のシリコンウエハ
を第2のシリコンウエハに重ね合わせた状態で熱処理し
て両該シリコンウエハを接合し, 前記第2のシリコン
ウエハと接合された該第1のシリコンウエハを所定厚さ
に薄くし, 少なくとも該薄くされた第1のシリコンウ
エハの開放表面に第2の酸化シリコン膜を形成し, 該
第2の酸化シリコン膜が形成された第1のシリコンウエ
ハおよび該第2のシリコンウエハを所定温度で熱処理し
て該第1のシリコンウエハをn型に転換させるる諸工程
を含むことを特徴とする本発明に係る半導体装置の製造
方法によって達成される。
[Means for Solving the Problems] The above object is to form a silicon oxide film on one surface of a p-type first silicon wafer, and to connect the first silicon wafer to a second silicon wafer through the silicon oxide film. The first silicon wafer bonded to the second silicon wafer is thinned to a predetermined thickness by heat-treating the two silicon wafers while stacked on the wafer, and at least the first silicon wafer bonded to the second silicon wafer is thinned to a predetermined thickness. A second silicon oxide film is formed on the open surface of the silicon wafer, and the first silicon wafer on which the second silicon oxide film is formed and the second silicon wafer are heat-treated at a predetermined temperature to form the first silicon oxide film. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which includes steps of converting a silicon wafer to n-type.

【0007】[0007]

【作用】支持基板となるシリコンウエハに酸化シリコン
膜を介して貼り合わされたp型のシリコンウエハは, 
薄く研磨され, かつ, その表面が酸化シリコンで覆
われた状態で熱処理されることによって, n型に転換
することを見出した。これを利用すれば, n型シリコ
ンウエハを用いることなく, 低コストのSOI 基板
を作製可能となる。
[Operation] A p-type silicon wafer bonded to a silicon wafer as a support substrate via a silicon oxide film,
It was discovered that by polishing a thin layer and heat-treating the surface while covering it with silicon oxide, it converts to n-type. By utilizing this, it becomes possible to manufacture low-cost SOI substrates without using n-type silicon wafers.

【0008】[0008]

【実施例】図1は本発明の一実施例の工程説明図であっ
て, シリコンウエハまたはこれらを接合して成るSO
I 基板の断面を示す。
[Embodiment] Fig. 1 is a process explanatory diagram of an embodiment of the present invention, and shows a silicon wafer or an SO made by bonding these.
I shows a cross section of the substrate.

【0009】同図(a) を参照して, 二枚のp型シ
リコンウエハ1および2を用意し, 例えばシリコンウ
エハ1の表面を熱酸化して, 厚さ約 0.5μm の
酸化シリコン膜3を形成する。酸化シリコン膜3が形成
されたシリコンウエハ1とシリコンウエハ2とを重ね合
わせ, 酸化性雰囲気中で, 例えば1100℃で熱処
理する。これにより, シリコンウエハ1と2とが接合
される。このような貼り合わせは, 周知の方法および
条件を用いて行えばよい。なお, 上記において, シ
リコンウエハ1に対する酸化シリコン膜3の形成は, 
周知のCVD(化学気相成長) 法によって行ってもよ
い。また, 酸化シリコン膜3の厚さには実質的な限定
はなく,例えば数10Å以上から,シリコンウエハ2に
貼り合わされたシリコンウエハ1に歪みを生じさせない
数μm 以下程度の範囲の厚さならば任意でよい。
Referring to FIG. 3(a), two p-type silicon wafers 1 and 2 are prepared, and the surface of the silicon wafer 1 is thermally oxidized to form a silicon oxide film 3 with a thickness of about 0.5 μm. form. A silicon wafer 1 and a silicon wafer 2 on which a silicon oxide film 3 has been formed are stacked and heat treated at, for example, 1100° C. in an oxidizing atmosphere. As a result, silicon wafers 1 and 2 are bonded. Such bonding may be performed using well-known methods and conditions. In the above, the formation of the silicon oxide film 3 on the silicon wafer 1 is as follows:
The well-known CVD (chemical vapor deposition) method may be used. Further, there is no practical limit to the thickness of the silicon oxide film 3, and the thickness may range from several tens of angstroms or more to several micrometers or less that does not cause distortion to the silicon wafer 1 bonded to the silicon wafer 2. It's optional.

【0010】次いで, 例えば周知の化学的研磨法およ
び機械研磨法を用いて, 同図(b) に示すように,
 シリコンウエハ2を10μm 程度またはそれ以下の
厚さまで薄くする。この厚さは, SOI 基板に形成
する半導体素子の種類や,SOI 構造によって達成し
ようとする所望の効果に応じて適当な値に設定すればよ
い。
[0010] Next, as shown in FIG.
The silicon wafer 2 is thinned to a thickness of about 10 μm or less. This thickness may be set to an appropriate value depending on the type of semiconductor element to be formed on the SOI substrate and the desired effect to be achieved by the SOI structure.

【0011】次いで, 例えば周知のウエット雰囲気中
における熱酸化法により, 同図(c) に示すように
, 薄くされたシリコンウエハ1およびシリコンウエハ
2の各々の開放表面に, 厚さ約1000Åの酸化シリ
コン膜4および5を形成する。この熱酸化温度は, 例
えば 900℃とする。 なお, 酸化シリコン膜4および5は, 周知のCVD
 法によって形成されたものでもよく,また,シリコン
ウエハ1に酸化シリコン膜4を形成するのみでもよい。
[0011] Next, as shown in FIG. 2(c), an oxidation film with a thickness of about 1000 Å is applied to the open surfaces of each of the thinned silicon wafers 1 and 2, for example, by a well-known thermal oxidation method in a wet atmosphere. Silicon films 4 and 5 are formed. This thermal oxidation temperature is, for example, 900°C. Note that the silicon oxide films 4 and 5 are formed by the well-known CVD process.
Alternatively, the silicon oxide film 4 may be simply formed on the silicon wafer 1.

【0012】次いで, シリコンウエハ1および2を,
 例えば乾燥窒素雰囲気中, 1100℃で約100 
分間熱処理する。これにより, シリコンウエハ1は,
 n型に転換する。このようにして,n型の薄いシリコ
ン層を有するSOI 基板が作製される。酸化シリコン
膜4は,シリコンウエハ2に半導体素子を形成するため
の絶縁層として使用できる。例えば, 同図(e) に
示すように, 酸化シリコン膜4を選択的にエッチング
して開口を形成し, この開口内に表出するシリコン層
に分離溝6を形成する。このようにして形成された島状
のシリコン領域11に, 通常の工程にしたがってトラ
ンジスタ等の素子を形成して, SOI構造の半導体装
置を作製する。
Next, silicon wafers 1 and 2 were
For example, in a dry nitrogen atmosphere, at 1100℃, about 100
Heat treat for minutes. As a result, silicon wafer 1 becomes
Converts to n-type. In this way, an SOI substrate having an n-type thin silicon layer is manufactured. The silicon oxide film 4 can be used as an insulating layer for forming semiconductor elements on the silicon wafer 2. For example, as shown in FIG. 4(e), an opening is formed by selectively etching the silicon oxide film 4, and a separation groove 6 is formed in the silicon layer exposed within this opening. Elements such as transistors are formed in the thus formed island-shaped silicon region 11 according to a normal process to fabricate a semiconductor device having an SOI structure.

【0013】図2および図3は, シリコンウエハ1の
厚さ方向における抵抗およびキャリヤ濃度の分布を示す
グラフであって, 図2は, 図1(c) に示すよう
に, 開放表面に酸化シリコン膜4が形成された状態に
おける分布, 図3は図1(d) に示すように, p
型をn型に転換させるための熱処理が行われた状態にお
ける分布である。なお, 図2および図3において, 
横軸は酸化シリコン膜3との界面を基準としたときのシ
リコンウエハ1中の距離(x;μm), 縦軸は抵抗(
R;ohm) およびキャリヤ濃度(個/cm3) で
ある。抵抗(R) は, 厚さ方向に平行な断面に間隔
90μm で接触させた二つの探針間の値である。
FIGS. 2 and 3 are graphs showing the distribution of resistance and carrier concentration in the thickness direction of the silicon wafer 1, and FIG. 2 shows the distribution of silicon oxide on the open surface, as shown in FIG. As shown in FIG. 1(d), the distribution in the state where the film 4 is formed, FIG.
This is the distribution after heat treatment to convert the type to n-type. In addition, in Figures 2 and 3,
The horizontal axis is the distance (x; μm) in the silicon wafer 1 with respect to the interface with the silicon oxide film 3, and the vertical axis is the resistance (
R; ohm) and carrier concentration (number/cm3). The resistance (R) is the value between two probes that are in contact with a cross section parallel to the thickness direction with an interval of 90 μm.

【0014】図2に示されるように, 表面に酸化シリ
コン膜4が形成されたのち, 熱処理が行われる前の状
態では, シリコンウエハ1はp型を維持しており, 
キャリヤ濃度(C) は, シリコンウエハ1中の距離
(x) とともに増大し, 酸化シリコン膜4との界面
で急減する。これを反映して, 抵抗(R) は, 距
離(x) とともに減少し, 酸化シリコン膜4との界
面で急増する。言い換えれば, シリコンウエハ1中の
キャリヤ濃度(C) および抵抗(R) は, 酸化シ
リコン膜4との界面近傍では, シリコンウエハ1の初
期値を示し, 酸化シリコン膜3に近づくにしたがって
, キャリヤ濃度(C) は減少し, 抵抗(R) は
増大する。 なお, 図2におけるパラメータは酸化シリコン膜4の
厚さであって, この厚さが 500Å, 4000Å
, 8000Åの場合について,上記キャリヤ濃度(C
) および抵抗(R) の分布に関する傾向はほぼ同じ
である。酸化シリコン膜4との界面近傍における曲線相
互間の離反は, 酸化シリコン膜4の厚さの違いによる
ものである。
As shown in FIG. 2, after the silicon oxide film 4 is formed on the surface but before heat treatment is performed, the silicon wafer 1 maintains p-type.
The carrier concentration (C) increases with distance (x) in the silicon wafer 1, and rapidly decreases at the interface with the silicon oxide film 4. Reflecting this, the resistance (R) decreases with distance (x) and increases rapidly at the interface with the silicon oxide film 4. In other words, the carrier concentration (C) and resistance (R) in the silicon wafer 1 show the initial values of the silicon wafer 1 near the interface with the silicon oxide film 4, and as they approach the silicon oxide film 3, the carrier concentration increases. (C) decreases and resistance (R) increases. Note that the parameter in FIG. 2 is the thickness of the silicon oxide film 4, and this thickness is 500 Å and 4000 Å.
, 8000 Å, the above carrier concentration (C
) and the distribution of resistance (R) are almost the same. The separation between the curves near the interface with the silicon oxide film 4 is due to the difference in the thickness of the silicon oxide film 4.

【0015】これに対して, 窒素雰囲気中,1100
 ℃での熱処理を行ったのちには, 図3に示すように
, シリコンウエハ1はn型に転換しており, キャリ
ヤ濃度(C) は, 酸化シリコン膜3との界面近傍お
よび酸化シリコン膜4との界面近傍で急減するが,これ
らの間の領域では 1013 〜1014個/cm3の
値を維持している。このキャリヤ濃度の分布は, シリ
コンウエハ1の厚さ方向における中央近傍で減少し, 
その両側で極大値を示す。抵抗(R) は, このキャ
リヤ濃度の分布を反映した分布を示している。 上記分布に関する傾向は, 図2の場合と同様に, 酸
化シリコン膜4の厚さによらない。
On the other hand, in a nitrogen atmosphere, 1100
After the heat treatment at ℃, as shown in Figure 3, the silicon wafer 1 has been converted to n-type, and the carrier concentration (C) is as high as that near the interface with the silicon oxide film 3 and in the silicon oxide film 4. The number of particles decreases rapidly near the interface with , but in the area between these, the value of 1013 to 1014 pieces/cm3 is maintained. This carrier concentration distribution decreases near the center of the silicon wafer 1 in the thickness direction, and
It shows maximum values on both sides. The resistance (R) shows a distribution that reflects this carrier concentration distribution. The tendency regarding the above distribution does not depend on the thickness of the silicon oxide film 4, as in the case of FIG.

【0016】上記のようなn型への転換は,酸化シリコ
ン膜を介して接合されたままのp型シリコンウエハの開
放表面を熱酸化しても生じない。また, 図2に示すよ
うに,シリコンウエハ1を薄くして熱処理を行っただけ
でもn型への転換は生じないし,薄くされたシリコンウ
エハ1上に酸化シリコン膜4を形成しただけでもn型へ
の転換は生じない。すなわち,上記p型からn型への転
換は, シリコンウエハ1を薄くし, 表面に酸化シリ
コン膜4を形成し, かつ, 熱処理を行うことにより
生じる。この熱処理は、非酸化性雰囲気であることは必
須ではないが,OSF(酸素による積層欠陥)の発生お
よび酸化による結晶層厚の変化をできるだけ抑止するた
めには,窒素のような非酸化性雰囲気中で行うことが望
ましい。また,上記n型への転換を生じさせるためには
,少なくとも1100℃以上の熱処理が必要である。
The above-mentioned conversion to n-type does not occur even if the open surface of a p-type silicon wafer, which is still bonded through a silicon oxide film, is thermally oxidized. Furthermore, as shown in FIG. 2, even if the silicon wafer 1 is thinned and heat treated, conversion to n-type will not occur, and even if only a silicon oxide film 4 is formed on the thinned silicon wafer 1, n-type conversion will not occur. No conversion occurs. That is, the conversion from p-type to n-type occurs by thinning the silicon wafer 1, forming a silicon oxide film 4 on its surface, and performing heat treatment. Although it is not essential that this heat treatment be performed in a non-oxidizing atmosphere, in order to suppress the occurrence of OSF (oxygen stacking faults) and changes in crystal layer thickness due to oxidation as much as possible, it is recommended to use a non-oxidizing atmosphere such as nitrogen. It is preferable to do it inside. Further, in order to cause the conversion to the n-type, heat treatment at at least 1100° C. or higher is required.

【0017】注目すべきことは, このようなn型への
転換に対して, 酸化シリコン膜4の厚さが関与しない
ことである。この現象を含め, 上記のようなn型への
転換, 図3のようなキャリヤ濃度分布が生じる理由に
ついては目下のところ不明である。
What should be noted is that the thickness of the silicon oxide film 4 has no effect on such conversion to n-type. Including this phenomenon, the reasons why the conversion to n-type as described above and the carrier concentration distribution as shown in FIG. 3 occur are currently unknown.

【0018】なお,上記実施例においては,支持基板と
してp型のシリコンウエハ1を用いたが,本発明におい
て,シリコンウエハ1の導電型ないし抵抗には何らの限
定はない。
In the above embodiment, a p-type silicon wafer 1 was used as the support substrate, but in the present invention, there are no limitations on the conductivity type or resistance of the silicon wafer 1.

【0019】[0019]

【発明の効果】本発明によれば, p型のシリコンウエ
ハを貼り合わせてn型のSOI 基板を作製できるため
, 安価なSOI 基板が提供可能となり, したがっ
て, SOI 構造の半導体装置の実用化を促進する効
果がある。
[Effects of the Invention] According to the present invention, since an n-type SOI substrate can be fabricated by bonding p-type silicon wafers together, it is possible to provide an inexpensive SOI substrate. It has a promoting effect.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明の一実施例の工程説明図[Figure 1] Process explanatory diagram of one embodiment of the present invention

【図2】 
 作製中間段階における本発明のSOI 基板中のキャ
リヤ濃度および抵抗の分布図
[Figure 2]
Distribution diagram of carrier concentration and resistance in the SOI substrate of the present invention at an intermediate stage of fabrication

【図3】  完成段階における本発明のSOI 基板中
のキャリヤ濃度および抵抗の分布図
[Figure 3] Distribution diagram of carrier concentration and resistance in the SOI substrate of the present invention in the completed stage

【符号の説明】[Explanation of symbols]

1, 2  シリコンウエハ 3, 4, 5  酸化シリコン膜 6  分離溝 1, 2 Silicon wafer 3, 4, 5 Silicon oxide film 6 Separation groove

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  p型の第1のシリコンウエハの一表面
に酸化シリコン膜を形成する工程と,該酸化シリコン膜
を介して該第1のシリコンウエハを第2のシリコンウエ
ハに重ね合わせた状態で熱処理して両該シリコンウエハ
を接合する工程と,前記第2のシリコンウエハと接合さ
れた該第1のシリコンウエハを所定厚さに薄くする工程
と,少なくとも該薄くされた第1のシリコンウエハの開
放表面に第2の酸化シリコン膜を形成する工程と,該第
2の酸化シリコン膜が形成された第1のシリコンウエハ
および該第2のシリコンウエハを所定温度で熱処理して
該第1のシリコンウエハをn型に転換させる工程とを含
むことを特徴とする半導体装置の製造方法。
1. A step of forming a silicon oxide film on one surface of a first p-type silicon wafer, and a state in which the first silicon wafer is superimposed on a second silicon wafer with the silicon oxide film interposed therebetween. a step of bonding the two silicon wafers by heat treatment, a step of thinning the first silicon wafer bonded to the second silicon wafer to a predetermined thickness, and a step of thinning at least the thinned first silicon wafer. forming a second silicon oxide film on the open surface of the silicon oxide film; and heat-treating the first silicon wafer on which the second silicon oxide film is formed and the second silicon wafer at a predetermined temperature to form the first silicon oxide film. 1. A method for manufacturing a semiconductor device, comprising the step of converting a silicon wafer to n-type.
JP4392791A 1991-03-11 1991-03-11 Manufacture of semiconductor device Withdrawn JPH04282867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4392791A JPH04282867A (en) 1991-03-11 1991-03-11 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4392791A JPH04282867A (en) 1991-03-11 1991-03-11 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04282867A true JPH04282867A (en) 1992-10-07

Family

ID=12677332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4392791A Withdrawn JPH04282867A (en) 1991-03-11 1991-03-11 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04282867A (en)

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