JPH0427164A - Semiconductor device and manufacture thereof, and flash controller using said device - Google Patents

Abstract

PURPOSE:To enhance a light emitting efficiency and to obtain a high performance flash controller which can be reduced in size and cost of a device by setting first impurity concentration of a first semiconductor region to a value for completely depleting the first region in a state that an actual use voltage is applied between first and second main electrodes at the time of OFF, and setting second impurity concentration of a second semiconductor region to a value in which the threshold voltage of a MOSFET become a predetermined value of an enhancement mode. CONSTITUTION:A depleted layer extended to an n<-> type drift layer 703 side completely depletes in the layer 703 by applying an anode voltage of several hundreds of V. If the anode voltage is raised to the vicinity of a rated voltage, the elongation of a depleted layer is stopped in a state that an n<+> type semiconductor layer having high doner density is slightly depleted. A threshold voltage for conducting channel region 708 is decided according to the impurity concentration of a p-type semiconductor region 705 at the end of an n<+> type semiconductor region 707 side of a channel region 708. This concentration is so set that the threshold voltage becomes a suitable value of an enhancement mode.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a switching semiconductor device for use in devices that require high voltage and high speed switching, such as inverter devices, and a method for manufacturing the same. The present invention relates to a flash control device using the device.

[Conventional technology]

Conventionally, inverter devices up to several hundred KVA were manufactured using bipolar transistors, but as the devices became smaller and
To improve performance, power devices with high switching speed and high switching frequency are required. Insulated gate bipolar transistors (IGBTs) have been proposed for such applications, and I GB
Due to its low gate drive loss characteristics, T can easily realize high voltage and high speed switching control up to several tens of kilohertz.

FIG. 12 is a cross-sectional structural diagram showing a conventional IGBT, and FIG. 13 is a circuit diagram showing its equivalent circuit. Referring to FIG. 12, an n+ type half layer 102 is formed on a p++ semiconductor substrate 101, and an n type drift layer 103 is formed thereon.
is formed. A p-type well region]04 is formed on the surface of the n-type drift layer 103 by selective diffusion, and an n++ emitter region 105 is formed on the surface of the p-type well region 104 by selective diffusion. n type drift layer 103 and n+
+ p-type well region 1 sandwiched between emitter region 105
04 becomes the channel region 106. The channel length is set to about several microns. Channel region 106
A gate electrode 108 is formed thereon via a gate oxide film 107, and an emitter electrode 109 is formed on the p-type well region 104 and the n++ emitter region 105. The electrodes 108 and 109 are insulated by an insulating film 110.

A collector electrode 111 is provided on the back surface of the p++ semiconductor substrate 101.
is formed.

In the equivalent circuit of Fig. 13, n-channel MO3FET
201 represents an MO5FET consisting of a vertical MO3 structure above the n-type drift layer 103 in FIG. 12, and the pnp transistor 202 is formed on the p++ semiconductor substrate 101. pn consisting of an n+ type half body layer 102, an n'' type drift layer 103, and a p type well region 104;
It represents a bipolar transistor with an np structure.

Further, the resistor 203 is connected to the n-type drift layer 103 in FIG.
represents the resistance component of

The voltage between the gate and emitter terminals G and E is sufficiently low, and the MO
When the SFET 201 is off, when a positive bias voltage is applied between the collector and emitter terminals C and E, the np diode between the n-type drift layer 103 and the p-type well region 104 is reverse biased, and the depletion layer is It mainly spreads toward the n″″ type drift layer 103 side to form space charges and can withstand high collector voltage. Further, the surface portion of the n-type drift layer 103 can also have a high breakdown voltage due to the field plate effect due to the MO3 structure. Therefore, in order to obtain a device with high breakdown voltage, the n-type drift layer 103 needs to be designed to have a low donor density (high specific resistance) and be thick. However, as a result, the resistance value of the resistor 203 tends to increase, which becomes a factor in reducing the current carrying capacity.

With MOSFET 201 turned on by applying a sufficient voltage between the gate and emitter terminals G and E, if the voltage between the collector and emitter terminals C and E is increased, the MOSFET
Electrons flow from the emitter electrode 109 to the collector electrode 111 through the channel 201 . This allows pnp
The base and emitter of the transistor 202 are forward biased, and the transistor 202 becomes active and l GB
The collector and emitter terminals C and E of T are electrically connected. At this time, the pnp+ transistor 202 amplifies the drain current of the MOSFET 201 and causes it to flow. Therefore, IGB
The higher the amplification factor of the pnp transistor 202 and the larger the drain current of the MOSFET 201, the higher the current carrying capacity of T becomes, and the lower the on-state voltage becomes. However, p
When the amplification factor of the np transistor 202 is increased, the turn-off characteristics deteriorate. In high frequency inverter applications, a turn-off time of 1 μs or less is required;
In order to achieve this with an IGBT having a high breakdown voltage of about 00V, it is necessary to make the current amplification factor of the pnp transistor 202 considerably low. For this reason, various measures have been taken, such as introducing a lifetime killer by irradiation with electron beams or protons or diffusion of heavy metals, and adding a short emitter resistor to the transistor 202. As a result, in an IGBT with faster turn-off characteristics, the current amplification factor of the pnp (pnp) transistor 202 becomes smaller, and there is a problem that the current density cannot be made high enough to meet the upper limit of the on-voltage specification.

As one method for improving the trade-off between turn-off characteristics and on-voltage, conventionally, as shown at 112 in FIG. Efforts have been made to lower the Further, the function of the low resistance layer 112 suppresses the spread of the depletion layer extending from the junction with the p-type well region 104 when in the on state, so that fine patterning is possible even in a high breakdown voltage device.

That is, according to the structure of FIG. 14, MOSFET 20
Up to now, performance has been improved by increasing the current carrying capacity of the PNP transistor 202 and increasing the drain current, so that a high current density can be obtained even if the amplification factor of the PNP transistor 202 is low.

A device called MOSGTO has been proposed as another method for improving the trade-off between turn-off characteristics and on-voltage. FIG. 15 is a sectional view showing the structure of the MOSGTO, and FIG. 16 is a circuit diagram showing its equivalent circuit. Referring to FIG. 15, there is n on the p++ semiconductor substrate 301.
type semiconductor layer 302, n-type semiconductor layer 303. P-type semiconductor layers 304 are sequentially stacked. An n-type well region 305 is formed on the surface of the p-type semiconductor layer 304 by selective diffusion.
A p-type source region 30 is formed on the surface of the n-type well region 305.
6 is formed by selective diffusion. A surface portion of the n-type well region 305 sandwiched between the p-type semiconductor layer 304 and the p-type source region 306 becomes a channel region 307. A first gate electrode 308 is formed on the p-type semiconductor layer 304,
A second gate electrode 310 is formed on the channel region 307 with a gate insulating film 309 interposed therebetween. Further, a cathode electrode 311 is formed on the n-type well region 305 and the p++ source region 306. These electrodes 308, 310
, 311 are insulated by an insulating film 312. An anode electrode 312 is formed on the back surface of the p++ semiconductor substrate 301.

In the equivalent circuit of Fig. 16, p-channel MO5FET
401 represents a MOSFET having a vertical MO3 structure above the p-type semiconductor layer 304 in FIG.
pnp) run risk 402 is a p++ semiconductor substrate 301.
The n+ type half layer 302 represents a pnnp structure bipolar transistor consisting of an n type semiconductor layer 303 and a p type semiconductor layer 304. In addition, the npn) run risk 403 is the n-type semiconductor layer 303. n-pn consisting of p-type semiconductor layer 304 and n-type well region 305
The structure represents a bipolar transistor.

To turn on this MO3GTO, apply a positive bias between the anode and cathode terminals A, and apply a trigger current to the first gate terminal G1.
A thyrsk consisting of 2,403 latches the anode and cathode terminals A.

Conductivity occurs between K. When a negative voltage is applied to the second gate terminal G2 to make the MO3FET 401 conductive and the thyristor is unlatched, the MO8GTO is turned off.

Since this device has a thyristor structure, its on-state voltage is low even when the withstand voltage is high.

However, turn-off is equivalent to cutting off the GTo without gate reverse bias, and there is a drawback that the anode current that can be cut off cannot be made sufficiently high. In addition, it has two gate electrodes and requires complex gate control for ignition and shutoff, making it not easy to use. A structure in which the firing gate control of this MO5GTO is performed using a MOS gate is the so-called MOS chondral thyristor (MCT), but this also has the same turn-off mechanism as the MO3GTO.
There is a problem similar to O.

By improving the drawbacks of the above devices,
Emitter-switched thyristors (E
ST) has been proposed.

Figure 17 shows rll EE Electron Devi.
ce IetLcrs, V.

1.11. No, 2. February 1990 “Th
e MOS-Gated ELLLer 5w1tc
hed Thyrlstor”, B, Jayant
18 is a cross-sectional view showing the structure of the EST disclosed in Ballga J, and FIG. 18 is a circuit diagram showing its equivalent circuit. Referring to FIG. 17, an n-type buffer layer 502 . n-type drift layer 503°p
Mold base layers 504 are laminated in sequence. p-type base layer 50
4, an n+ type rough floating region 505 and an n++ emitter region 506 are selectively formed. n+
Mold rough floating region 505n++ emitter region 50
The surface portion of the p-type base region 504 sandwiched between the p-type base region 6 and the channel region 507 becomes a channel region 507. Except for the channel region 507,
A p+ type region 508 is provided around the n++ emitter region 506 to reduce base resistance. Channel area 5
A gate electrode 5 is formed on the gate electrode 07 via a gate insulating film 509]
A cathode electrode 511 is formed on the n++ emitter region 506 and the p+ type region 508. p
An anode electrode 512 is formed on the back surface of the semiconductor substrate 50].

In the equivalent circuit of Fig. 18, n-channel MO5FET
601 is the MO above the p-type base region 504 in FIG.
Compatible with MOSFETs consisting of 5 structures (pnp)
Ranjistaro 02 is a p+ type cliff conductor board 501. , n-type buffer layer 502. It corresponds to a bipolar transistor with a p"nnp structure consisting of an n-type drift layer 503 and a p-type base region 504. Also, the npn) transistor 03 has an n-type drift layer 50B, a p-type base layer 5
04, n consisting of n + type rough floating region 505
Compatible with pn+ structure bipolar transistors.

A resistor 604 represents a resistance component of the p-type base layer 504.

To turn on this EST, anode.

With a positive bias applied to the cathode terminal A and a positive voltage applied to the gate terminal G to make the MO8FET 601 conductive, the p-type base layer is used to trigger and latch the thyristor consisting of the transistors 602 and 603. 5
It is necessary to supply a trigger current to 04. For this reason, as described in the above document, a gate terminal GT for trigger current supply, similar to the first gate terminal G1 in FIGS. 15 and 16, is connected to the p-type base layer 504 appropriately. must be established. In the equivalent circuit of FIG. 18, this gate terminal G is indicated by a dotted line. On the other hand, by setting the voltage applied to the gate terminal G to zero and making the MO5FET 601 non-conductive, the thyristor is unlatched and the EST is turned off.

Like the MOSGTO described above, the EST has a thyristor structure, so even if the withstand voltage is high, the on-voltage can be kept low. In addition, MO8FET connected in cascode with the thyristor section
Since the turn-off is controlled by the channel of 601, the anode current that can be cut off is higher than that of MOSGTO. moreover,
Since the amplification factor of transistor 602 can be lowered, high-speed turn-off is possible. However, since it requires two gate electrodes like MOSGTO, there is a problem that gate control is complicated. There is also the problem that the extra gate electrode reduces the packaging density of the device and reduces the current density that can be achieved.

[Problem to be solved by the invention]

As explained above, the semiconductor devices that have been proposed or used in the past have their own problems. In other words, IGBT has high voltage resistance.

There is a trade-off relationship between on-voltage and turn-off speed, and it is difficult to satisfy all of them. Although MOSGTOs and MCTs can achieve high withstand voltage and low on-resistance, they have a problem that the main current density that can be interrupted is low and that gate control is complicated because two gate electrodes are required. Furthermore, although EST can achieve high breakdown voltage, low on-resistance, high-speed turn-off, and high interruptible main current density, there is a problem in that gate control is complicated because two gate electrodes are required. In addition, there is also the problem that the device packaging density cannot be increased due to the extra gate electrode.

Furthermore, as will be described in detail later, when such a conventional semiconductor device is applied to a control device for a flash used as an auxiliary light source for photography, etc., it is possible to improve the luminous efficiency of the flash, reduce the size of the device, reduce the cost, etc. However, there were some drawbacks, and there was a problem in that it was not possible to achieve sufficiently satisfactory performance.

This invention was made to solve the above-mentioned problems, and it is possible to realize high withstand voltage, low on-resistance, high-speed turn-off, and high main current density that can be interrupted, as well as requiring only a single gate electrode. The present invention aims to provide a semiconductor device and a method for manufacturing the same, which can increase device packaging density and realize high current density.

Another object of the present invention is to obtain a high-performance flash control device that has high flash emission efficiency and can be made smaller and less expensive.

[Means to solve the problem]

The semiconductor device according to the first invention includes the first aspect. a first semiconductor layer of a first conductivity type having a second principal surface; a second semiconductor layer of a second conductivity type formed on the first principal surface of the first semiconductor layer; and a surface of the second semiconductor layer. A first semiconductor region of a first conductivity type having a relatively low first impurity concentration selectively formed on the surface of the second semiconductor layer adjacent to the first semiconductor region; a second semiconductor region of a first conductivity type having a high second impurity concentration; a third semiconductor region of a second conductivity type formed on at least a portion of the surface of the first semiconductor region; and a surface of the second semiconductor region. a fourth semiconductor region of the second conductivity type selectively formed apart from the first semiconductor region; A surface portion between the fourth semiconductor regions is defined as a channel, and a gate insulating film formed on this channel, a gate electrode formed on this gate insulating film, and spanning over the second and fourth semiconductor regions. The first formed
a main electrode and a second electrode formed on the second main surface of the first semiconductor layer;
The main electrode is configured such that the first impurity concentration is the first impurity concentration when the main electrode is off. The first semiconductor region is set to a value that completely depletes the first semiconductor region when an actual operating voltage is applied between the second main electrodes, and the second impurity concentration is set to a value that makes the threshold voltage of the channel a predetermined value for enhancement mode. has been done.

Further, the method for manufacturing a semiconductor device according to the second invention includes the method for manufacturing a semiconductor device according to the first invention.
．． a step of preparing a first semiconductor layer of a first conductivity type having a second main surface; a step of forming a second semiconductor layer of a second conductivity type on the first main surface of the first semiconductor layer; selectively forming a first semiconductor region of a first conductivity type having a relatively low first impurity concentration on the surface of the second semiconductor layer; a step of selectively forming a second semiconductor region of the first conductivity type having a high second impurity concentration; and a step of forming a third semiconductor region of the second conductivity type on at least a portion of the surface of the first semiconductor region. and selectively forming a fourth semiconductor region of the second conductivity type on the surface of the second semiconductor region apart from the first semiconductor region, the surface portion between the third and fourth semiconductor regions serving as a channel. a step of forming a gate insulating film on the channel; a step of forming a gate electrode on the gate insulating film; The method further comprises a step of forming a first main electrode over the fourth semiconductor region, and a step of forming a second main electrode on the second main surface of the first 'li conductor layer. 1 impurity concentration is the 1st impurity concentration when off. The second impurity concentration is set to a value that completely depletes the first semiconductor region when an actual operating voltage is applied between the second main electrodes, and the second impurity concentration is set to a value that makes the threshold voltage of the channel a predetermined value for enhancement mode. has been done.

Further, a flash control device according to a third aspect of the present invention includes a flash control device according to a first aspect of the present invention.
．． a second high-voltage power supply terminal; a flash energy storage capacitor connected between the second high-voltage power supply terminal; a series connection body of a flash discharge tube and a switch element connected between second high-voltage power supply terminals, and a series connection body connected to the flash discharge tube;
The device includes a trigger circuit that triggers the flash discharge tube at the start of flash discharge, and the switch element is constructed by forming a cascode-connected thyristor element and a MOSFET on one chip.

Note that the semiconductor device according to the second invention may be used as the switch element according to the third invention.

[Effect]

1st. In the second invention, the first impurity concentration of the first semiconductor region is the first impurity concentration when the first semiconductor region is off. The second impurity concentration of the second semiconductor region is set to a value such that the first semiconductor region is completely depleted when an actual operating voltage is applied between the second main electrodes, and the second impurity concentration of the second semiconductor region is set so that the threshold voltage of the channel is a predetermined value in the enhancement mode. Since the value is set to , the first. When a bias voltage is applied to the gate electrode in a state where an actual operating voltage is applied between the second main electrodes, first main electrode - fourth semiconductor region - channel - third semiconductor region → depleted first semiconductor region → A current is supplied to the second semiconductor layer through the path of the second semiconductor layer, which becomes a trigger current for the thyristor structure, latches the thyristor, and immediately turns on the semiconductor device. When the bias voltage on the gate electrode is removed, the thyristor is unlatched and the semiconductor device is turned off.

Further, the switch element in the third invention is configured such that a cascode-connected thyristor element and a MOSFET are formed on one chip, and in particular, when the switch element is turned off, one terminal of the thyristor element is opened. Therefore, it is possible to block flash discharge current with high current density to the container.

Furthermore, if the semiconductor device according to the first invention is used as a switch element, only one gate electrode is required, and the flash control device can be controlled by human control of tp-.

〔Example〕

FIG. 1 is a cross-sectional structural diagram showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a circuit diagram showing an equivalent circuit thereof. Referring to FIG. 1, p++ as the first semiconductor layer
Semiconductor substrate 70], an n+ type upper semiconductor layer 702 and an n type drift layer 703 as a second semiconductor layer are laminated in this order. For example, the 091978 layer 703 has an impurity concentration of 1.0'' in a 1000 V class semiconductor device.
The depth may be about cm −3 and the depth may be about 60 μm.

A p-type semiconductor region 704 as a first semiconductor region is selectively formed on the surface of the 091978 layer 703. p
- type semiconductor region 704 is, for example, about 1012cITl-3 to 1015c111-8, which has a fairly low impurity concentration.
The depth may be approximately several μm. p-type semiconductor region 7
Adjacent to both sides of 04, on the n-type drift layer 703,
A p-type semiconductor region 705 as a second semiconductor region is selectively formed in a well shape. For example, the p-type semiconductor region 705 may have an impurity concentration of about 1016cn-3 at the end of the channel region 708 on the n++ semiconductor region 707 side, and a depth of about several μm.

On the surface of the p-type semiconductor region 704, an n-type semiconductor region 706 as a third semiconductor region is formed in regions 704 and 705.
selectively formed away from the interface between the two. For example, the n++ semiconductor region 706 has an impurity concentration of 10t at the surface.
The depth may be approximately 0°3 μm. On the surface of the p-type semiconductor region 705, an n-type semiconductor region 707 as a fourth semiconductor region is formed in the regions 704 and 7.
It is selectively formed away from the interface between 05 and 05. For example, the n-type semiconductor region 707 has an impurity concentration of 1 at the surface.
The depth may be about 0.019cn-3 and about 0.3 μm. A surface portion of the p − type semiconductor region 704 and the p type semiconductor region 705 sandwiched between the n++ semiconductor regions 706 and 707 becomes a channel region 708 .

A gate electrode 710 is formed on the channel region 708 with a gate oxide film 709 interposed therebetween. Further, an anode electrode 711 as a first main electrode is formed on the p-type semiconductor region 705 and the n-type semiconductor region 707. These electrodes 710 and 711 are insulated by an insulating film 712. p
A cathode electrode 713 as a second main electrode is formed on the back surface of the type semiconductor substrate 701.

Note that the p-type semiconductor layer 704 has a shallower depth than the p-type semiconductor region 705 in FIG.
As shown in the figure, the depth is approximately the same as that of the p-type semiconductor region 705,
Alternatively, as shown in FIG. 4, the depth may be deeper than the p-type semiconductor region 705.

In the equivalent circuit diagram of Fig. 2, n-channel MO3FET
Reference numeral 801 corresponds to a MOSFET having an MO3 structure above the p-type semiconductor region 704 in FIG. The multi-collector pnp) run lister 802 includes the p++ semiconductor substrate 701 and the n+ type half layer 702n- in FIG.
A bipolar transistor with a pnnp structure consisting of a type drift layer 703 and a p-type semiconductor region 704, and a pnn transistor in which the collector of this bipolar transistor is changed from the p-type semiconductor region 704 to the p-type semiconductor region 705.
Compatible with p-structure bipolar transistors. The npn) run lister 803 corresponds to a bipolar transistor having an npn structure consisting of an n-type drift layer 703, a p-type semiconductor region 704, and an n++ semiconductor region 706 in FIG. A resistor 804 represents a resistance component in the p-type semiconductor region 704.

A portion of the transistor 802 and the transistor 803 are thyristor-connected to form a thyristor section. A MO3FET 801 is connected in cascode to this thyristor section.

In this manner, this semiconductor device uses a cascode drive of GTO silisks using MOSFETs.

Next, the operation will be explained. When the gate voltage applied to the gate terminal G is low and the MO5FET 801 is off, when the voltage applied to the anode terminal A is increased relative to the cathode terminal K, the n-type drift layer 703 and the p″″- and p
The pn junction between the type semiconductor regions 704 and 705 becomes reverse biased, and a depletion layer begins to grow on both sides of this pn junction. The depletion layer is a p-type semiconductor region 70 with low acceptor density.
4, and p-
The inside of type semiconductor region 704 is completely depleted.

When the anode voltage is further increased slightly, the depletion layer stops growing while the p-type semiconductor region 705 with high acceptor density is slightly depleted. The state of elongation of the depletion layer (the end of the depletion layer) during such low voltage blocking is shown by a dashed line in FIG. Note that the edge of the depletion layer also appears around the n++ semiconductor region 706, but is not shown in the drawing.

The depletion layer extending toward the n-type drift layer 703 is completely depleted in the n-type drift layer 703 by applying an anode voltage of several hundred V, and when the anode voltage is further increased to near the rated voltage (for example, 100OV), The depletion layer stops growing when the n-type semiconductor layer with high donor density is slightly depleted. The state of elongation of the depletion layer during such high voltage blocking is represented by a dotted line in FIG. When the anode voltage is increased beyond the rated voltage, the electric field inside the semiconductor device eventually reaches a critical electric field and breakdown begins.

FIG. 6 is a diagram showing the extension of the depletion layer in the voltage blocking state of the semiconductor device having the structure of FIG. 4. Similar to Figure 5,
- The dotted line shows the extension of the depletion layer when blocking a low voltage, and the dotted line shows the extension of the depletion layer when blocking a high voltage. In the case of the structure shown in FIG. 4, the n-type drift layer 703 and the p-type semiconductor region 704
Since the pn junction between is a flat junction with no curvature,
Since electric field concentration occurs, it is desirable to have a high breakdown voltage. This also applies to the semiconductor device having the structure shown in FIG.

When a positive voltage is applied to the gate terminal G, the channel region 70
An inversion layer is formed at 8 and MO3FET 801 is turned on.

The threshold voltage at which the channel region 708 becomes conductive is determined by the impurity concentration of the p-type semiconductor region 705 at the end of the channel region 708 on the n++ semiconductor region 707 side. It is set so that

When the MO3FET 801 is turned on, the n+ type I6 conductor region 706 has almost the same potential as the cathode electrode 711. In this state, the voltage applied to the anode terminal A is changed to the cathode terminal K.
When the voltage rises to 200 nm, the pn junction between the n-type drift layer 703 and the p- and p-type semiconductor regions 704 and 705 is reverse biased, and a depletion layer spreads on both sides of this pn junction in the same manner as described above, resulting in several The p-type semiconductor region 704 is completely depleted by the anode voltage of V. As a result, the n-type drift layer 703. The base region of the npn) run lister 803 consisting of the p-type semiconductor region 704 and the n-type semiconductor region 706 is in a bunch-through state.
This transistor 803 has a low impedance and its collector and emitter are connected (ie, conductive). As a result, from the n++ semiconductor region 707 to the channel region 708
．． n” type semiconductor region 706.N type drift layer 703 (pn
Electrons are injected into the p++ semiconductor substrate 701 (the emitter of the pnp transistor 802), and holes are injected into the n-type drift layer 703 via the n-type semiconductor layer 702 in response. A part of the injected holes generates a voltage drop at the resistor 804 when flowing from the p-type semiconductor region 704 to the cathode electrode 711 via the p-type semiconductor region 705, and the base current of the npn) run lister 803 increases. As a result, transistors 802 and 803 operate as thyristors and are latched.

In this way, this semiconductor device is turned on, and an anode current flows from the anode terminal A to the cathode terminal K. In the on state, the thyristor composed of transistors 802 and 803 operates, and the voltage drop ↑U across the series resistance of MO3FET 801 is significantly reduced. In addition, p+ type semiconductor root plate 701n+ type groove conductor layer 702n
- type drift layer 703 and p-type semiconductor region 705 (pnp) run lister (part of transistor 802)
becomes active and conducts an anode current.

As described above, in the ON state of the semiconductor device according to this embodiment, the current carrying capacity of MO5FET 801 is greatly improved, so even if the amplification factor of pnp) run lister 802 decreases due to the introduction of a lifetime killer, etc. It is still possible to improve the current density (reduce the on-state voltage) even when the current density is increased.

In the on state where an anode current flows between the anode and the cathode terminal A, when the positive voltage of the gate terminal G is removed to cut off the channel region 708 (turn off the MO5FET 801), the emitter of the npn transistor 803 is opened. . This allows transistors 802.803
The silisk consisting of the latches are released. And p
Electrons, which are minority carriers in the - type semiconductor region 704,
The turn-off of this semiconductor device is completed when the holes, which are minority carriers in the n-type drift layer 703, disappear by recombination. Since minority carriers take longer to disappear than holes, this semiconductor device basically exhibits blocking characteristics similar to those of IGET.

When turning off MO3GTOs and MCTs, the thyristor's latch is released by bypassing the gate and cathode of the GTO thyristor using a MOS channel, which makes it difficult to maintain a sufficiently high main current density that can be interrupted. on the other hand,
In the semiconductor device of the above embodiment, since the cathode of the GTO thyristor is turned on and off by the MOS channel, there is an advantage that the main current can be turned on and off to the limit of the current carrying capacity of the MOS channel. Furthermore, since only a single gate terminal G is required for on/off control, the device packaging density is increased and a high current density can be realized.

Furthermore, due to the presence of the p″″-type semiconductor region 704, p
The electric field concentration caused by the curvature of the semiconductor region 705 is alleviated (particularly in the structures of FIGS. 3 and 4). Therefore, the diffusion depth of the p-type semiconductor region 705 can be made shallow, and the channel length of the channel region 708 can also be made short.
8 structure can be made finer, and as a result, on-resistance can be further reduced and current density can be further improved.

Note that the semiconductor device according to the above embodiment also has a p-type semiconductor substrate 701. n+ type half body layer 702
n-type drift layer 703. It contains a parasitic silicon risk consisting of a p-type semiconductor region 705 and an n++ semiconductor region 707. Therefore, when the current density in the p-type semiconductor region 705 increases, this parasitic thyristor latches up and 1. It can get out of control. Therefore, in order to prevent potential rise in the p-type semiconductor region 705, for example, as shown in FIG.
14 is preferably provided to keep the resistivity of the p-type semiconductor region 705 low.

Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 8A to 8E.

First, as shown in FIG. 8A, a p-type semiconductor substrate 701
An n-type semiconductor layer 702 is formed by ion-implanting n-type impurities thereon.
After forming, an n-type semiconductor layer 703 is epitaxially grown thereon. Next, as shown in FIG. 8B, n
A p-type impurity is ion-implanted onto the - type semiconductor substrate 703 to form a p'''' type semi-conductor layer 720 surface. and,
As shown in FIG. 8C, the surface is oxidized to form a silicon oxide film 721 over the entire surface, and polysilicon is deposited thereon and then patterned by selective etching to form a polysilicon film 722. Thereafter, p-type impurities are ion-implanted using the polysilicon film 722 as a mask, and annealing is performed to form a well-shaped p-type semiconductor region 705.
form. At the same time, the p-type impurity of the p-type semiconductor layer 720 is diffused, thereby forming the p-type semiconductor region 704.

Next, as shown in FIG. 8D, the polysilicon film 722 and the oxide film 721 are selectively etched to form the gate electrode 72.
10 and a gate oxide film 709 are formed, and windows are provided on both sides thereof. Then, by selectively introducing n-type impurities through the window, the n++ semiconductor region 7
06,707 are formed in a self-aligned manner. After that, the 8th
As shown in Figure E, the interlayer insulating film 712 connects the gate electrode 71.
The semiconductor device having the structure shown in FIG. 1 is obtained by covering the 0 and n type semiconductor regions 706 and forming an anode electrode 711 thereon by metallization treatment and forming a cathode electrode 713 on the back surface.

FIG. 9 is a cross-sectional structural diagram showing another embodiment of the semiconductor device according to the present invention. In this embodiment, the n++ semiconductor region 706 is formed on the entire surface of the p- type semiconductor region 704 instead of a part of the surface.

Further, the gate electrode 710 is not divided into two, and is a single gate electrode common to the two channel portions. The rest of the structure is the same as the semiconductor device shown in FIG. Even in such a structure, the same effects as in the above embodiment can be obtained.

Furthermore, the lower surface shape of the p''''-type semiconductor region 704 does not necessarily have to be flat, and may be shaped along the well shape of the p-type semiconductor region 705, as shown in FIG. 10, for example.

In the above embodiment, an n-channel type semiconductor device has been described, but it goes without saying that the present invention can also be applied to an n-channel type semiconductor device by reversing the conductivity type of each layer or region.

The semiconductor device according to the present invention described in detail above exhibits excellent performance when applied to a control device for a flash used as an auxiliary light source for photography and the like. A flash control device using a semiconductor device according to the present invention will be described below, but first, a conventional flash control device using an IGBT and its problems will be explained.

FIG. 19 is a circuit diagram showing a conventional flash control device using IGBTs. In FIG. 19, IGBT90
1 and a flash discharge tube 902 are connected in parallel to a flash energy storage capacitor 903 to form a main circuit. This main circuit includes a high voltage power supply V. M is applied. A trigger circuit for triggering the flash discharge tube 902 includes a trigger transformer 904. It consists of a resistor 905 and a trigger capacitor 906. Control human power VIN is applied to the gate of the IGBT 901 via a gate resistor 907.

In operation, first, the control human power VIN applied to the gate of the IGBT 901 is set to a low level, the IGBT 901 is turned off, and the high voltage power supply V is turned off. The flash energy storage capacitor 90B is charged to the polarity shown in the figure (usually around 300 cm) by H. This causes trigger capacitor 906 to be charged through resistor 905 at the same time. In this state,
When a high-level (usually several tens of V) voltage pulse control voltage IN is applied to the gate of IGBT901, IGBT9
01 is turned on, and the charge stored in the trigger capacitor 906 is discharged through the primary winding of the trigger transformer 904. As a result, 2 of the trigger transformer 904
A high voltage pulse of several KV is generated in the next winding, and the flash discharge tube 9
02 is triggered. As a result, the flash discharge tube 902 starts discharging, consuming the charge stored in the flash energy storage capacitor 903 and emitting a flash. When the amount of light necessary for photographing is obtained, the gate voltage of IGBT 901 is lowered to a sufficiently low level and IGBT 90 is turned off, which cuts off the current flowing through flash discharge tube 902 and stops flash discharge. do. At the same time, trigger capacitor 906 is recharged to its original polarity, returning to its initial state.

In this manner, the conventional flash control device controls the amount of flash by applying the energy charged in the flash energy storage capacitor 903 to the flash discharge tube 902 for a desired time using the I GET as a switching element. are doing. An IGBT is a semiconductor device in which a bipolar transistor driven by a MOSFET is integrated into one chip, and can be driven by voltage like a MOSFET, and has a current carrying capacity similar to a bipolar transistor.

However, since the output stage is a bipolar transistor, its current carrying capacity is (MOSFET current carrying capacity) x (
In order to conduct and cut off the large current pulse of 100 to 200 A required by the flash control device, which is limited by the hFE of the transistor, a large silicon chip of about 5 to 7 III 110 is required. As a result, conventional flash control devices using IGBTs are relatively expensive and have not become widely popular at present. Furthermore, since the IGBT is used at a high current density, the on-voltage drop at the IGBT is as high as 6 to IOV, which lowers the luminous efficiency of the flash and increases the size of the integrated circuit package containing the IGBT, making it possible to reduce the size of the flash control device. The problem was that it was not possible to

As a measure to solve such problems, the same inventor as the present inventor proposed a circuit as shown in FIG. 20, which provides an inexpensive flash control device by combining a thyristor and a MOSFET in a cascode connection. (Japanese Unexamined Patent Publication No. 1-24399). This circuit is MO3FE
The thyristor 909 connected to it in cascode can be turned on only when T908 is on, and since a low voltage MO3FET 908 can be used, in combination with the high voltage thyristor 909, it can handle large currents. Density flash discharge current switching becomes possible.

In FIG. 20, thyristor 909 and MOSFE 79
08 are each formed by an individual element. Therefore, there is a difficulty in miniaturizing the flash control device. On the other hand, according to the semiconductor device according to the present invention having the structure shown in FIG. Therefore, by using the semiconductor device according to the present invention, a compact, high-performance flash control device can be easily realized. A flash control device using the semiconductor device according to the present invention as a switch element will be described below.

FIG. 11 is a circuit diagram showing an embodiment of a flash control device according to the present invention. Compared to the conventional flash control device shown in FIG.
The difference is that a semiconductor device 910 according to the present invention having the structure shown in FIG. 1 etc. is used instead of 01. The rest of the configuration is the same as the flash control device shown in FIG. 19. Note that in the equivalent circuit of the semiconductor device 910 shown in FIG. 11, the thyristor 805 corresponds to the transistors 802 and 803 in the equivalent circuit of FIG.

According to the semiconductor device 910 according to the present invention, as described above, it is possible to increase the current density of the device, and large current control can be realized with a silicon chip having a smaller area. Also, at turn-off, the MOS transistor 801
It is sufficient to simply apply an off-level voltage to the gate terminal G so that the channel can be turned off. By turning off the MOS) run resistor 801, the emitter current of the npn) run resistor 803 (FIG. 2) in the thyristor 805 is cut off, so that the transistor 803 is turned off quickly and reliably. This allows thyristor 80
The latch 5 will be released. Gatte, MCT and MO8G
Turn-off failures do not occur as in semiconductor devices such as TO, which are turned off by shunting between the gate and cathode of a thyristor using a MOS gate. Therefore, as described above, the main current density that can be interrupted can be set high. This advantage is particularly important in applications such as flash control devices where it is desired to interrupt large currents of about 100 OA/c or more. It should be noted that IGBTs are also capable of interrupting current to this extent, but as mentioned above, the on-voltage increases, the efficiency of flash discharge decreases, and the instantaneous rise in chip temperature due to energization reduces the interrupting ability. There is a problem of doing something like that. Therefore, the practical limit for IGBTs is a main current density of about 700 A/e-.

As described above, according to the flash control device according to the present embodiment, since the semiconductor device having the excellent characteristics according to the present invention is used, it is possible to control the flash discharge tube current at high speed with higher current density. There is an effect that it can be done. Furthermore, since only one gate terminal is required, it is possible to realize a compact and low-cost flash control device while maintaining high compatibility with flash control devices using conventional IGBTs.

Note that the semiconductor device 910 may have two gate terminals G as long as compatibility with a conventional flash control device using an IGBT is not considered.

Therefore, in the semiconductor device having the structure shown in FIG. 1, for example, the p-type semiconductor region 704 does not punch through when the operating voltage is applied, and instead, an additional charge is added that injects carriers into the p-type semiconductor region 704 for turn-on. A semiconductor device 9 in FIG. 11 is provided with means such as a gate electrode.
It may be used as 10. Further, the EST shown in FIG. 17, which is a semiconductor device in which a cascode connection body of a SIRISK and a MOSFET is formed on one chip like the semiconductor device 910, can be used instead of the semiconductor device 910 in FIG.

〔Effect of the invention〕

As explained above, according to the invention described in claim 1.2, the structure is such that the MOSFET is cascode-connected to one electrode of the thyristor on the equivalent circuit, and the first impurity concentration of the first semiconductor region is turned off. When the actual operating voltage is applied between the first and second main electrodes, the first semiconductor region is set to a value that is completely depleted, and the second semiconductor region of the second semiconductor region is
Since the impurity concentration was set to a value that makes the threshold voltage of the MO3FET a predetermined value for the enhancement mode, the first
．． By applying a bias voltage to the gate electrode while the actual operating voltage is applied between the second main electrodes, the thyristor immediately latches and turns on the semiconductor device, and by removing the bias voltage, the thyristor immediately unlatches and the semiconductor device It becomes possible to turn off the device. As a result, the following various excellent effects can be obtained.

■ Since it has a built-in thyristor, it can satisfy both high breakdown voltage and low on-resistance.

- Since the on/off operation is performed using cascode-connected MOSFETs, it is possible to increase the main current density that can be interrupted.

■ Since electric field concentration in the voltage blocking state is alleviated, it is easy to increase the withstand voltage.

(2) Only one gate ff electrode is required, and only one enhancement mode gate voltage can be applied as the on/off control signal, which simplifies the control circuit.

■ Since the amplification factor of the transistor in the thyristor may be lowered, high-speed turn-off can be achieved.

■ Since there is only one gate electrode, the chip area is small and high current density can be achieved. As a result, products with higher cost performance can be provided.

Further, according to the third aspect of the invention, since a switch element is used in which a cascode-connected thyrisk element and a MOSFET are formed on one chip, a flash discharge current with a high current density can be easily interrupted. In addition, the flash has the effect of maintaining high luminous efficiency.

Furthermore, if the semiconductor device according to claim 1 is used as a switch element as in the invention according to claim 4, only one gate electrode is required, and while maintaining high compatibility with a flash control device using a conventional IGET. This has the effect of realizing a small and low-cost flash control device.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram showing one embodiment of the semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing its equivalent circuit, and FIGS. 3 and 4 show other embodiments of the semiconductor device according to the present invention. 5 and 6 are diagrams showing how the depletion layer extends, and FIG. 7 is a sectional diagram showing still another embodiment of the semiconductor device according to the present invention, and FIGS. 8A to 8E.
The figures are a cross-sectional view showing the manufacturing process of the semiconductor device in Figure 1, and Figure 9.
10 and 10 are cross-sectional structural diagrams showing still another embodiment of a semiconductor device according to the present invention, FIG. 11 is a circuit diagram showing an embodiment of a flash control device according to the present invention, and FIG. 12 is a diagram showing a conventional IGBT. 13 is a circuit diagram showing its equivalent circuit, FIG. 14 is a sectional structure diagram showing another conventional IGBT, FIG. 15 is a sectional structure diagram showing a conventional MO3GTO, and FIG. 16 is its equivalent circuit. A circuit diagram showing an equivalent circuit, FIG. 17 is a cross-sectional structural diagram showing a conventional EST, FIG. 18 is a circuit diagram showing the equivalent circuit, and FIGS. 19 and 20 are circuit diagrams showing a conventional flash control device. be. In the figure, 701 is a p+ type semiconductor substrate, 702 is an n+ type semiconductor substrate, and 702 is an n+ type semiconductor substrate.
703 is an n-type drift layer, 704 is a p-type semiconductor layer, and 703 is an n-type drift layer.
type semiconductor region, 705 is a p-type semiconductor region, 706, 70
7 is an n+ type semiconductor region, 708 is a channel region, 709
is a gate oxide film, 710 is a gate electrode, 711 is a cathode electrode, 713 is an anode electrode, 902 is a flash discharge tube,
903 is a flash energy storage capacitor, 9o4 is a trigger transformer, 910 is a semiconductor device, and 76M is a high voltage power supply. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (4)

[Claims] (1) a first semiconductor layer of a first conductivity type having first and second main surfaces; a second semiconductor layer of a second conductivity type formed on the first main surface of the first semiconductor layer; a first semiconductor region of a first conductivity type having a relatively low first impurity concentration selectively formed on the surface of the second semiconductor layer; a second semiconductor region of a first conductivity type having a relatively high second impurity concentration selectively formed; and a third semiconductor region of a second conductivity type formed on at least a portion of the surface of the first semiconductor region.
a semiconductor region; and a fourth semiconductor region of a second conductivity type selectively formed on a surface of the second semiconductor region apart from the first semiconductor region, the surface between the third and fourth semiconductor regions. The portion is defined as a channel, and includes a gate insulating film formed on the channel, a gate electrode formed on the gate insulating film, and the second and fourth parts.
further comprising: a first main electrode formed over a semiconductor region; and a second main electrode formed on a second main surface of the first semiconductor layer, the first impurity concentration being lower than the first impurity concentration when off. , the first semiconductor region is set to a value that completely depletes the first semiconductor region when a practical voltage is applied between the second main electrodes, and the second impurity concentration is set such that the threshold voltage of the channel reaches a predetermined value in the enhancement mode. A semiconductor device that is set to a value of (2) preparing a first semiconductor layer of a first conductivity type having first and second main surfaces; forming a second semiconductor layer of a second conductivity type on the first main surface of the first semiconductor layer; selectively forming a first conductivity type first semiconductor region having a relatively low first impurity concentration on the surface of the second semiconductor layer; A second semiconductor layer of the first conductivity type having a relatively high second impurity concentration on the surface of the second semiconductor layer.
selectively forming a semiconductor region; forming a third semiconductor region of a second conductivity type on at least a portion of a surface of the first semiconductor region; and forming a third semiconductor region of a second conductivity type on a surface of the second semiconductor region; selectively forming a fourth semiconductor region of a second conductivity type away from the region, a surface portion between the third and fourth semiconductor regions is defined as a channel, and a gate insulating film is formed on the channel. forming a gate electrode on the gate insulating film; forming a first main electrode over the second and fourth semiconductor regions; and forming a first main electrode on the second and fourth semiconductor regions; forming a second main electrode on the surface, and the first impurity concentration is set such that the first semiconductor region is completely in a state where an actual working voltage is applied between the first and second main electrodes in an off state. and the second impurity concentration is set to a value such that the threshold voltage of the channel becomes a predetermined value in an enhancement mode. (3) first and second high-voltage power supply terminals; a flash energy storage capacitor connected between the first and second high-voltage power supply terminals; and a flash energy storage capacitor connected between the first and second high-voltage power supply terminals. a series connection body of a flash discharge tube and a switch element; and a trigger circuit connected to the flash discharge tube to trigger the flash discharge tube when starting a flash discharge, the switch element being a cascode-connected thyristor element. A flash control device consisting of a MOSFET and a MOSFET formed on one chip. (4) The flash control device according to claim 3, wherein the semiconductor device according to claim 1 is used as the switch element.