KR910019251A - Flash control device using the device in parallel with the semiconductor device and its manufacturing method - Google Patents

Flash control device using the device in parallel with the semiconductor device and its manufacturing method Download PDF

Info

Publication number
KR910019251A
KR910019251A KR1019910002062A KR910002062A KR910019251A KR 910019251 A KR910019251 A KR 910019251A KR 1019910002062 A KR1019910002062 A KR 1019910002062A KR 910002062 A KR910002062 A KR 910002062A KR 910019251 A KR910019251 A KR 910019251A
Authority
KR
South Korea
Prior art keywords
semiconductor region
semiconductor
conductivity type
semiconductor layer
forming
Prior art date
Application number
KR1019910002062A
Other languages
Korean (ko)
Other versions
KR940008259B1 (en
Inventor
아끼오 우에니시
히로시 야마구찌
야쓰아끼 후꾸모찌
Original Assignee
시기 모리야
미쓰비시뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 시기 모리야, 미쓰비시뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910019251A publication Critical patent/KR910019251A/en
Application granted granted Critical
Publication of KR940008259B1 publication Critical patent/KR940008259B1/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/53Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
    • H03K3/57Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices
    • H01L29/745Gate-turn-off devices with turn-off by field effect
    • H01L29/7455Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Discharge-Lamp Control Circuits And Pulse- Feed Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

반도체장치 및 그 제조방법에 병행하여 해당장치를 사용한 프래쉬 제어장치Flash control device using the device in parallel with the semiconductor device and its manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 이 발명에 의한 반도체장치의 한실시예를 표시하는 단면구조도, 제 2 도는 그 등가회로를 표시하는 회로도, 제 3 도 및 제 4 도는 이 발명에 의한 반도체장치의 다른 실시예를 표시하는 단면구조도.1 is a cross-sectional structural view showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a circuit diagram showing an equivalent circuit thereof, and FIGS. 3 and 4 show another embodiment of the semiconductor device according to the present invention. Sectional structure diagram.

Claims (4)

제 1, 제 2주면을 가지는 제 1 도전형의 제 1 반도체층과, 상기 제 1 반도체층의 제 1 주면상에 형성된 제 2 도전형의 제 2 반도체층과, 상기 제 2 반도체층의 표면에 선택적으로 형성된 비교적 낮은 제 1 불순물농도를 가지는 제 1 도전형의 제 1 반도체영역과, 상기 제 1 반도체영역에 인접하여 상기 제 2 반도체층의 표면에 선택적으로 형성된 비교적 높은 제 2 불순물농도를 가지는 제 1 도전형의 제 2 반도체영역과, 상기 제 1 반도체영역의 표면이 적어도 일부에 형성된 제2 도전형의 제 3 반도체영역과, 상기 제 2 반도체영역의 표면에 상기 제 1 반도체영역으로부터 떨어져서 선택적으로 형성된 제2도전형의 제4반도체영역과를 구비하고, 상기 제3, 제4반도체영역간의 표면부분은 채널로서 규정되고,상기 채널상에 형성된 게이트절연막과, 상기 게이트 절연막상에 형성된 게이트전극과, 상기 제2, 제4반도체영역상에 걸쳐서 형성된 제1주전극과, 상기 제1반도체층의 제2주면상에 형성된 제2주전극과를 다시금 구비하고, 상기제1불순물농도는 오프시에 상기 제 1, 제 2 주전극간에 실사용전압이 인가된 상태에서 상기 제 1 반도체영역이 완전하게 공핍화하는 값으로 설정되고, 상기 제 2 불순물농도는 상기 채널의 스레숄드전압이 인한 스먼트모드의 소정치로 되는 값으로 설정되는 반도체장치.On the surface of the first semiconductor layer of the first conductivity type having the first and second principal surfaces, the second semiconductor layer of the second conductivity type formed on the first main surface of the first semiconductor layer, and the second semiconductor layer. A first semiconductor region of a first conductivity type having a relatively low first impurity concentration selectively formed, and a second high impurity concentration selectively formed on the surface of the second semiconductor layer adjacent to the first semiconductor region A second semiconductor region of a first conductivity type, a third semiconductor region of a second conductivity type having at least a portion of the surface of the first semiconductor region, and selectively separated from the first semiconductor region on the surface of the second semiconductor region And a fourth semiconductor region of the second conductive type, wherein a surface portion between the third and fourth semiconductor regions is defined as a channel, and a gate insulating film formed on the channel and the gate insulating film. And a first electrode formed over the second and fourth semiconductor regions, and a second main electrode formed on the second main surface of the first semiconductor layer. The concentration is set to a value at which the first semiconductor region is completely depleted in a state in which a real voltage is applied between the first and second main electrodes when the concentration is off, and the second impurity concentration is a threshold voltage of the channel. A semiconductor device which is set to a value which becomes a predetermined value of the resultant segment mode. 제 1, 제 2 주면을 가지는 제 1 도전형의 제 1 반도체층을 준비하는 공정과, 상기 제 1 반도체층의 제 1 주면상에 제 2 도전형의 제 2 반도체층을 형성하는 공정과, 상기 제 2 반도체층의 표면에 비교적 낮은 제 1 불순물농도를 가지는 제 1 도전형의 제 1 반도체영역을 선택적으로 형성하는 공정과, 상기 제 1 반도체영역에 인접하여 상기 제 2 반도체층의 표면에 비교적 높은 제 2 불순물농도를 가지는 제 1 도전층의 제 2 반도체영역을 선택적으로 형성하는 공정과, 상기 제 1 반도체영역의 표면이 적어도 일부에 제 2 도전형의 제 3 반도체영역을 형성하는 공정과, 상기 제 2 반도체영역의 표면에 상기 제 1 반도체영역으로부터 떨어져서 제 2 도전형의 제 4 반도체영역을 선택적으로 형성하는 공정과를 구비하고, 상기 제 3, 제 4 반도체영역간의 표면부분은 채널로서 규정되고, 상기 채널상에 게이트 절연막을 형성하는 공정과, 상기 게이트 절연막상에 게이트전극을 형성하는 공정과, 상기 제 2 , 제 4 반도체 영역상에 걸쳐서 제 1 주전극을 형성하는 공정과, 상기 제 1 반도체층이 제 2 주면상에 제 2 주전극을 형성하는 공정과를 다시금 구비하고, 상기 제 1 불순물농도는 오프시에 상기 제 1, 제 2 주전극간에 실사용전압이 인가된 상태에서 상기 제 1 반도체영역이 완전하게 공핍화하는 값으로 설정되이고, 상기 제 2 불순물농도는 상기 채널의 스레숄드전압이 인한스먼트모드의 소정치로 되는 값으로 설정되는 반도체장치의 제조방법.Preparing a first semiconductor layer of a first conductivity type having a first and a second main surface; forming a second semiconductor layer of a second conductivity type on a first main surface of the first semiconductor layer; and Selectively forming a first semiconductor region of a first conductivity type having a relatively low first impurity concentration on the surface of the second semiconductor layer, and relatively high on the surface of the second semiconductor layer adjacent to the first semiconductor region Selectively forming a second semiconductor region of the first conductive layer having a second impurity concentration, forming a third semiconductor region of the second conductivity type in at least a portion of the surface of the first semiconductor region, and Selectively forming a fourth semiconductor region of a second conductivity type on a surface of the second semiconductor region, wherein the surface portion between the third and fourth semiconductor regions is a channel; Forming a gate insulating film on said channel, forming a gate electrode on said gate insulating film, forming a first main electrode over said second and fourth semiconductor regions, and And again forming a second main electrode on the second main surface, wherein the first impurity concentration is in a state where an actual voltage is applied between the first and second main electrodes. And wherein the first impurity concentration is set to a value at which the first semiconductor region is completely depleted, and the second impurity concentration is set to a value of a segment mode due to the threshold voltage of the channel. 제1, 제2 의 고압전원단자와, 상기 제 1, 제 2 의 고압전원단자간에 접속된 철광에너지 측적용 컨덴서와, 상기 제1, 제2 의 고압전원단자간에 접속된 첨광방전관과 스위치 소자와의 직렬접속체와, 상기 첨광방정전곤에 접속되고, 첨광방전의 개시에 즈음하여 상기 첨광방전관을 트리거하는 트리거회로와를 구비하고, 상기 스위치소자는 캐스코드 접속된 사이리스터소자와 MOSFET와가 1칩상에 형성되어서 이루어지는 프래쉬 제어장치.An iron ore energy measurement capacitor connected between the first and second high voltage power terminals, the first and second high voltage power terminals, a sharp discharge tube and a switch element connected between the first and second high voltage power terminals; And a trigger circuit connected to the sharpening discharge circuit and triggering the sharpening discharge tube upon the start of the sharpening discharge, wherein the switch element comprises a cascode-connected thyristor element and MOSFET with Flash control device formed in the. 상기 스위치소자로서 제1항의 반도체장치를 사용한 제3항의 프래쉬 제어장치.The flash control device according to claim 3, wherein the semiconductor device according to claim 1 is used as the switch element. ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910002062A 1990-04-12 1991-02-07 Semiconductor device and manufacturing method thereof KR940008259B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP9802190 1990-04-12
JP2-98021 1990-04-12
JP2111119A JP2579378B2 (en) 1990-04-12 1990-04-26 Semiconductor device, method of manufacturing the same, and flash control device using the device
JP2-111119 1990-04-26

Publications (2)

Publication Number Publication Date
KR910019251A true KR910019251A (en) 1991-11-30
KR940008259B1 KR940008259B1 (en) 1994-09-09

Family

ID=26439178

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002062A KR940008259B1 (en) 1990-04-12 1991-02-07 Semiconductor device and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP2579378B2 (en)
KR (1) KR940008259B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752102A (en) * 1992-04-16 1998-05-12 Nikon Corporation Electronic flashing device
JP4934929B2 (en) 2001-08-27 2012-05-23 株式会社ニコン Electronic flash device
JP2010092056A (en) * 2009-10-14 2010-04-22 Hitachi Ltd Pdp display device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132645A (en) * 1983-01-19 1984-07-30 Nissan Motor Co Ltd Semiconductor device
JPH0620127B2 (en) * 1984-04-11 1994-03-16 株式会社明電舍 GTO thyristor
JPS6424399A (en) * 1987-07-20 1989-01-26 Mitsubishi Electric Corp Flashing discharge bulb control circuit

Also Published As

Publication number Publication date
JPH0427164A (en) 1992-01-30
JP2579378B2 (en) 1997-02-05
KR940008259B1 (en) 1994-09-09

Similar Documents

Publication Publication Date Title
KR870008340A (en) Electric device
JPS5754370A (en) Insulating gate type transistor
KR900019261A (en) Semiconductor device
KR900013652A (en) High voltage semiconductor device with SOI structure with reduced on resistance
KR890001199A (en) Semiconductor devices and circuits
JPS5637683A (en) Semiconductor rectifying device
JPS564290A (en) Superconductive element
KR910019251A (en) Flash control device using the device in parallel with the semiconductor device and its manufacturing method
JPS5458378A (en) Semiconductor device and its usage
JPS57208177A (en) Semiconductor negative resistance element
JPS57176781A (en) Superconductive device
JPS5753944A (en) Semiconductor integrated circuit
JPS5745975A (en) Input protecting device for semiconductor device
KR920010950A (en) Manufacturing Method of Semiconductor Device
JPS6467966A (en) Semiconductor device
SE8005703L (en) DIELECTRICALLY ISOLATED SEMICONDUCTOR SWITCH
JPS5483781A (en) Semiconductor control element
JPS5796568A (en) Semiconductor device and high-voltage circuit using said device
JPS5727052A (en) Semiconductor device
JPS572574A (en) Insulated gate type field effect transistor
KR830004678A (en) High voltage solid state switch
JP2907504B2 (en) Semiconductor device
JPS56133870A (en) Mos field effect semiconductor device with high breakdown voltage
JPS5376675A (en) High breakdown voltage field effect power transistor
JPS5524433A (en) Composite type semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020822

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee