JPH08316457A - Insulated gate power semiconductor device and its driving method - Google Patents

Abstract

PURPOSE: To improve turn-off capability by a method wherein the first conductive layer, which is not used conventionally, is formed on the surface of the second conductivity type base layer, and a base electrode, to be connected to a drain electrode, is provided on the first conductivity type layer and the second conductive type base layer. CONSTITUTION: A drain electrode 115 is integrally formed with a base electrode 108 to be electrically connected to the base electrode 108, and a source electrode 117 is integrally formed with a cathode electrode 105 to be electrically connected to the cathode electrode 105. The base electrode 108, which is used as a hole suction electrode when turned off, is formed in such a manner that it is in direct contact with a P-type base layer 102 in the immediate neighborhood of an n-type emitter layer 103. Accordingly, the transverse resistance of the P-type base layer 102 is decreased in the bias path of the hole current, and as a result, voltage drop by the biased hole current can be made small when compared with the conventional structure, and high turn-off capability can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate power semiconductor device in which turn-off control is performed by an insulated gate.

[0002]

2. Description of the Related Art In a high breakdown voltage, high current insulated gate power semiconductor element, a gate drive type is used for gate drive.
The current drive type is available, but the former is preferable. This is because the voltage control type can drive the gate with a smaller current than the current driving type.

FIG. 32 is a sectional view showing an element structure of an insulated gate type turn-off thyristor which is one of conventional voltage controlled type insulated gate power semiconductor elements.

In the figure, reference numeral 701 denotes a high resistance n-type base layer, and a p-type base layer 702 is selectively formed on the surface of the n-type base layer 701. An n-type emitter layer 703 is selectively formed on the surface of the p-type base layer 702.

On the other hand, a high-concentration p-type emitter layer 704 is formed on the back surface of the n-type base layer 701. A cathode electrode 705 is provided on the n-type emitter layer 703, and an anode electrode 706 is provided on the p-type emitter layer 704.
A thyristor body having a pnpn structure is formed by these four layers.

An n-type drain layer 714 is formed on the surface of the p-type base layer 702 at a position separated from the n-type emitter layer 703 by a predetermined distance.
4 and the n-type emitter layer 703 between the p-type base layer 702
A gate electrode 710 is formed over the gate insulating film 709.
Is provided.

The gate electrode 710 is for turn-off, and the n-type emitter layer 703 is used as a source for the region C.
N-channel turn-off MO with H1 as n-channel
The SFET is configured.

The drain electrode 715 contacting the n-type drain layer 714 is simultaneously formed with the p-type base layer 702.
The p-type base layer 702 and the n-type drain layer 714 are short-circuited by such a drain electrode 715.

On the other hand, on the p-type base layer 702 between the n-type base layer 701 and the n-type emitter layer 703, a gate electrode 712 is provided via a gate insulating film 711.

This gate electrode 712 is for turning off, and this n-type emitter layer 703 is used as a source and the region C is used.
N-channel turn-off MO with H2 as n-channel
The SFET is configured.

The operating principle of the insulated gate turn-off thyristor having such a structure is as follows.

First, to turn on the device, a positive voltage is applied to the turn-on gate electrode 712 with respect to the cathode. Accordingly, the turn-on gate electrode 712
The n-channel CH2 immediately below is brought into a conductive state, electrons are injected from the n-type emitter layer 703 to the n-type base layer 701, and holes corresponding to it are injected from the p-type emitter layer 704, and the device is turned on. .

On the other hand, in order to turn off the device, a positive voltage is applied to the turn-off gate electrode 710 with respect to the cathode. Accordingly, the turn-off gate electrode 710
A part of the hole current flowing directly from the p-type base layer 702 to the n-type emitter layer 703 is drained from the drain electrode 715 as shown by a broken line in FIG. , N-type drain layer 714, n
The n-type emitter layer 703 is bypassed to the cathode electrode 705 through the channel CH1. By bypassing the hole current in this manner, the injection of electrons from the n-type emitter layer 703 to the p-type base layer 702 is stopped, and the device is turned off.

However, the insulated gate type turn-off thyristor of this type has a problem that a sufficient turn-off ability cannot be obtained. This is due to the resistance of the hole current bypass path shown by the broken line in FIG.

The resistance of the hole current bypass path is mainly the resistance (R1, R2) of the p-type base layer 702 and the on-resistance of the n-channel 710 below the turn-off gate electrode 710.

A voltage drop determined by these resistances and bypass currents causes an n-type emitter layer 703 and a p-type base layer 70.
When the voltage exceeds the built-in voltage of 2, the n-type emitter layer 70
The electron injection from 3 does not stop. In particular, according to the research by the inventor, it has been found that the resistance R2 in the lateral diffusion portion of the p-type base layer 702 among the bypass resistances is very large.

Therefore, the insulated gate type turn-off thyristor of the conventional structure has a problem that when the anode current (main current) becomes large, the voltage drop easily exceeds the built-in voltage and cannot be turned off.

FIG. 33 is a sectional view showing the structure of a conventional lateral insulated gate turn-off thyristor (T. Ogura a.
nd A. Nakagawa, IEDM92, p.241, 1992).

In the figure, reference numeral 801 denotes a silicon substrate, and a high resistance n-type base layer 803 is provided on the silicon substrate 801 via a silicon oxide film 802. A p-type base layer 8 is selectively formed on the surface of the n-type base layer 803.
04 are formed. On the surface of the p-type base layer 804, an n-type emitter layer 807, an n-type drain layer 808, n
A mold source layer 809 is formed.

A cathode electrode 8 is formed on the n-type emitter layer 807.
11 is provided. A turn-on gate electrode 814 is provided on the p-type base layer 804 between the n-type emitter layer 807 and the n-type base layer 803 via a gate insulating film 816.

The n-type source layer 809 has a cathode electrode 81.
A source electrode 812 connected to 1 is provided. n
The type drain layer 808 is short-circuited with the p-type base layer 804 by the base electrode 813. n-type drain layer 808 and n
The gate electrode 81 for turn-off is formed on the p-type base layer 804 between the gate electrode 81 and the source layer 809 via the gate insulating film 816.
5 are provided.

An n-type buffer layer 805 is formed on the surface of the n-type base layer 803, and the n-type buffer layer 80 is formed.
A p-type emitter layer 806 is formed on the surface of No. 5.
An anode electrode 810 is provided on the p-type emitter layer 806. In addition, 817 has shown the insulating film.

The operating principle of the insulated gate turn-off thyristor having such a structure is as follows.

First, to turn on the device, a positive voltage is applied to the turn-on gate electrode 814 with respect to the cathode. As a result, the n-type emitter layer 807 is short-circuited with the n-type base layer 803 via the n-channel formed on the surface of the p-type base layer 4 below the turn-on gate electrode 814, and electrons are stored in the n-type base layer 803. Injected. Then, holes of an amount corresponding to the p-type emitter layer 806 are injected into the n-type base layer 803, and the device is turned on.

On the other hand, to turn off the device, a positive voltage is applied to the cathode to the turn-off gate electrode 815 while a positive voltage is applied to the turn-on gate electrode 814.

At this time, the electron current is, as shown by the solid line in FIG. 33, the n-type emitter layer 807, the p-type base layer 804,
It flows in order of the n-type base layer 803. 33, the hole current flows to the n-type base layer 803 and the p-type base layer 804, and then is drained to the base electrode 813 in the immediate vicinity of the n-type emitter layer 807 to turn off the gate electrode. It is discharged to the source electrode 812 through the n channel below 815.

Such a current path is a so-called IGB.
This is the same as T (insulated gate bipolar transistor). Therefore, if a voltage is not applied to the turn-on insulated gate electrode 814 after a certain time has elapsed after applying a positive voltage to the turn-off insulated gate electrode 815, the injection of electrons is stopped and the device is turned off.

However, even with such an insulated gate type turn-off thyristor, there is a problem that a sufficient turn-off ability cannot be obtained like the insulated gate type turn-off thyristor.

That is, when the anode current increases,
At the time of turn-off, if the voltage drop due to the hole bypass current exceeds the built-in voltage of the p-type base layer 804 and the n-type emitter layer 807, the electron injection from the n-type emitter layer 804 does not stop and the latch-up state remains. , Gate control becomes impossible.

By the way, one of the insulated gate power semiconductor elements is a GTO (Gate Turn-Off thyristor). The GTO is based on an npnp four-layer structure thyristor, in which the n-type emitter layer is provided with a cathode electrode, the p-type base layer is provided with a gate electrode, and the p-type emitter layer is provided with an anode electrode. It has a structure provided.

To turn on this element, a positive voltage is applied to the gate electrode with respect to the cathode. As a result, electrons are injected from the n-type emitter layer into the n-type base layer, and a corresponding amount of holes are injected from the p-type emitter layer into the n-type base layer. Turn on.

On the other hand, in order to turn off the device, a negative voltage is applied to the gate electrode with respect to the cathode. As a result, the anode current (main current) is bypassed to the gate circuit, the electron injection from the n-type emitter layer is stopped, and the element is turned off.

Since the GTO causes conductivity modulation, it has an advantage that the on-state voltage is lower than that of a power MOSFET, and since it can be self-extinguished by a gate circuit, it can be widely used as a power semiconductor element. .

However, since the GTO is a current-driven element, it has drawbacks such as a large gate circuit and a high switching speed because it is turned on by conductivity modulation. In addition, there is a drawback that current concentration is likely to occur particularly at turn-off, and the breakdown resistance is small.

An EST (Emitter Switched Thyristor) has been proposed as an element for controlling the turn-on and turn-off of a thyristor with a MOS gate electrode structure.

FIG. 34 is a sectional view showing the element structure of the EST. p-type emitter layer 941, n-type base layer 940,
The p-type base layer 938 and the n-type emitter layer 937 are pn
A pn thyristor structure is formed. p-type base layer 93
8 is connected to the cathode electrode 935 through the high-concentration p-type contact layer 934. In addition, the p-type emitter layer 94
1 is provided with an anode electrode (not shown).

On the surface of the p-type base layer 938, an n-type source layer 939 short-circuited with the p-type base layer 938 is formed in contact with the high-concentration p-type contact layer 934 by the cathode electrode 935. A p-type base layer 938 between the n-type emitter layer 937 and the n-type source layer 939, and a p-type base layer 9 between the n-type emitter layer 937 and the n-type base layer 940.
A gate electrode 936 is provided on each of the electrodes 38 via a gate insulating film.

According to the insulated gate turn-off thyristor of this type, the voltage applied to the gate electrode 936 causes
Since the turn-on and turn-off of the thyristor can be controlled, there is no problem that the gate circuit becomes large and the switching speed becomes slow unlike the case of the GTO.

However, since the p-type base layer 938 and the cathode electrode 935 are short-circuited, there is a problem that the on-voltage becomes high.

Further, since the p-type contact layer 934 is formed, when the anode current increases, the p-type contact layer 934 and the n-type source layer 93 are turned off at the time of turn-off.
There is a problem that the parasitic thyristor composed of the n-type base layer 940 and the p-type emitter layer 941 latches up and cannot be turned off.

[0041]

As described above, in the conventional insulated gate type turn-off thyristor, when the anode current becomes large, the electron injection cannot be stopped due to the voltage drop caused by the hole bypass current, and the parasitic thyristor is not generated. Since it latches up, there is a problem that it cannot be turned off.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an insulated gate type power semiconductor device having a better turn-off capability than ever before.

[0043]

[Means for Solving the Problems]

[Outline] In order to achieve the above-mentioned object, an insulated gate power semiconductor device according to the present invention (claim 1) has a first conductive type base layer and a surface directly or directly on the first conductive type base layer. A second conductive type emitter layer that is indirectly in contact with the second conductive type emitter layer;
First and second second conductivity type base layers selectively formed on the surface of the first conductivity type base layer opposite to the conductivity type emitter layer, and the surface of the first second conductivity type base layer A first conductive type emitter layer selectively formed on the first conductive type emitter layer, a first conductive type emitter layer formed on a surface of the first second conductive type base layer and separated from the first conductive type emitter layer, 2nd of 2
A first conductivity type source layer selectively formed on the surface of the conductivity type base layer and a first conductivity type formed on the surface of the second second conductivity type base layer away from the first conductivity type source layer. -Type drain layer, and a turn-off gate electrode provided on the second second-conductivity-type base layer between the first-conductivity-type drain layer and the first-conductivity-type source layer via a gate insulating film. A turn-on gate electrode provided on the first second conductivity type base layer between the first conductivity type base layer and the first conductivity type layer via a gate insulating film, and the second conductivity type. The first main electrode provided on the emitter layer of the first conductivity type, the second main electrode provided on the emitter layer of the first conductivity type, the base layer of the first conductivity type and the first conductivity type layer. The base electrode provided and the second conductive type source layer, A main electrode and electrically connected to the source electrode, provided on the first conductivity type drain layer, characterized in that it includes a said base electrode electrically connected to a drain electrode.

Here, the second base layer of the second conductivity type may be the same layer as the first base layer of the second conductivity type. In this case, the first conductivity type source layer is the same layer as the first conductivity type emitter layer, and the source electrode is the same electrode as the second main electrode.

Further, another insulated gate type power semiconductor device according to the present invention (claim 2) comprises a first conductivity type base layer,
A second conductivity type emitter layer that is in direct or indirect contact with the surface of the first conductivity type base layer and a surface of the first conductivity type base layer opposite to the second conductivity type emitter layer. A second conductivity type base layer, a first conductivity type emitter layer selectively formed on a surface of the second conductivity type base layer, and a first conductivity type emitter layer on a surface of the second conductivity type base layer. A first conductivity type source layer formed apart from
A first conductivity type drain layer formed on the surface of the second conductivity type base layer away from the first conductivity type source layer and the first conductivity type emitter layer, the first conductivity type drain layer and the first conductivity type drain layer. Between the turn-off gate electrode provided on the second conductive type base layer between the conductive type source layer and the gate insulating film, and between the first conductive type base layer and the first conductive type emitter layer. Turn-on gate electrode provided on the second conductivity type base layer via a gate insulating film, a first main electrode provided on the second conductivity type emitter layer, and the first conductivity type emitter layer A second main electrode provided on the first conductive type source layer and the second main electrode provided on the first conductive type source layer;
A source electrode electrically connected to the main electrode of the
A drain electrode of a conductive type and a base electrode provided on the base layer of the second conductive type, and between the first conductive type emitter layer and the first conductive type base layer on the turn-on gate electrode side. A part of the second conductive type base layer is
It is characterized in that it is recessed toward the first conductivity type emitter layer side.

In another insulated gate type power semiconductor device according to the present invention (claim 3), a first wafer having a thyristor portion provided with a first main electrode and an integrated body with the first wafer are provided. And a second wafer provided with a second main electrode and having a current control section for controlling a current flowing through the thyristor section, the insulated gate power semiconductor device comprising: The part includes a second conductivity type emitter layer provided with the first main electrode, a first conductivity type base layer selectively formed on a surface of the second conductivity type emitter layer, and the first conductivity type. A second conductivity type base layer selectively formed on the surface of the base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, and a first conductivity type emitter layer Selectively short-circuits the first conductive type base layer And a first conductive type drain layer connected to the first conductive type emitter layer, and a first conductive type source layer connected to the second main electrode. And a second selectively short-circuiting the first conductivity type source layer and the first conductivity type drain layer.
An insulated gate type FET having the above-mentioned insulated gate structure, and a first conductive type cathode layer which is separated from the first conductive type drain layer and is connected to the second conductive type base layer,
Formed in contact with the first conductivity type cathode layer,
A zener diode including a second conductivity type anode layer connected to the second main electrode.

Here, the insulated gate structure is, for example, one in which a semiconductor layer is provided with a gate electrode via a gate insulating film, one in which a semiconductor layer is provided with a light irradiation means via a gate insulating film, and the like. This structure allows carriers to be injected from the emitter to the base.

More specifically, the insulated gate power semiconductor layer according to the present invention (claim 3) is a first wafer having a thyristor portion provided with a first main electrode, and the first wafer. An insulated gate power semiconductor device comprising: a second wafer which is integrally formed with a wafer, is provided with a second main electrode, and has a current control section for controlling a current flowing through the thyristor section. And the thyristor portion has a second conductivity type emitter layer provided with the first main electrode,
A first conductivity type base layer selectively formed on the surface of the second conductivity type emitter layer, and a first connection electrode provided on the surface of the first conductivity type base layer and provided with a first connection electrode. Two
A conductive type base layer, a first conductive type emitter layer selectively formed on the surface of the second conductive type base layer and provided with a second connection electrode, the first conductive type emitter layer and the first conductive type emitter layer.
A first conductivity type drain layer comprising a first MOS structure electrode for selectively short-circuiting the conductivity type base layer and the current control section connected to the second connection electrode via a third connection electrode. And a first conductivity type source layer connected to the second main electrode through a fourth connection electrode, and a first conductivity type drain layer and the first conductivity type source layer are selectively short-circuited. Two
And a first conductivity type cathode layer connected to the first connection electrode via a fifth connection electrode and separated from the first conductivity type drain layer by a separation layer, A zener diode formed of a second conductivity type anode layer formed in contact with the first conductivity type cathode layer and connected to the second main electrode via a sixth connection electrode.

Another insulated gate type power semiconductor device according to the present invention (claim 4) is a first conductivity type base layer and a second conductivity type which is in direct or indirect contact with the surface of the first conductivity type base layer. Type emitter layer, a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer opposite to the second conductivity type emitter layer, and a surface of the second conductivity type base layer. A first conductive type emitter layer selectively formed, a first conductive type source layer formed on the surface of the second conductive type base layer and separated from the first conductive type emitter layer, and the first conductive type A first layer formed on the surface of the second conductive type base layer away from the source layer and the first conductive type emitter layer;
A conductive type drain layer, and a turn-off gate electrode disposed on the second conductive type base layer between the first conductive type drain layer and the first conductive type emitter layer via a gate insulating film, A first turn-on gate electrode provided on the second conductive type base between the first conductive type base layer and the first conductive type source layer via a gate insulating film;
It is formed on the second conductive type base layer between the first conductive type source layer and the first conductive type emitter layer via a gate insulating film, and is electrically connected to the first turn-on gate electrode. A second turn-on gate electrode, a first main electrode formed on the second conductivity type emitter layer, and a second main electrode formed on the first conductivity type emitter layer,
A base electrode formed on the surface of the second conductive type base layer in a position close to the first conductive type source layer and the first conductive type emitter layer, the first conductive type drain layer and the second conductive type A drain electrode provided on the base layer and electrically connected to the base electrode is provided.

Another insulated gate type power semiconductor device according to the present invention (claim 5) is the above-mentioned insulated gate type power semiconductor device (claim 4), in which the width of the second conductivity type source layer is The width is less than or equal to the width of the second conductivity type emitter layer.

A method for driving an insulated gate power semiconductor device according to the present invention (claim 6) is the method for driving the above insulated gate power semiconductor device (claim 4). A first turn-on MOS formed by the first turn-on gate electrode by applying a predetermined voltage to each of the turn-on gate electrode, the second turn-on gate electrode, and the turn-off gate electrode.
The FET is turned on, the second turn-on MOSFET formed by the second turn-on gate electrode is turned on, and the turn-off MOSFET formed by the turn-off gate electrode is turned off. A thyristor composed of a conductive type emitter layer, the second conductive type base layer, the first conductive type base layer and the second conductive type emitter layer was turned on to turn on the first and second turn-on MOSFETs. In this state, a predetermined voltage is applied to the turn-off gate electrode to turn on the turn-off MOSFET, and after this state, a predetermined voltage is applied to each of the first and second turn-on gate electrodes. The thyristor by turning off the turn-on MOSFET. Characterized in that it-off.

[Operation] In the insulated gate power semiconductor device according to the present invention (claim 1), the first conductivity type layer which has not been heretofore formed is formed on the surface of the second conductivity type base layer. A base electrode connected to the drain electrode is provided on the first conductivity type layer and the second conductivity type base layer.

Therefore, when a voltage of a predetermined level or more is applied to the turn-off gate electrode at the time of turn-off to form a channel on the surface of the second-conductivity-type base layer below the turn-off gate electrode, the majority carriers of the second-conductivity-type emitter layer are formed. A carrier having the same polarity as (hereinafter, referred to as a first polar carrier) is
By-pass, which is a first conductivity type base layer, a first second conductivity type base layer, a base electrode, a drain electrode, a first conductivity type drain layer, the channel, a first conductivity type source layer, a source electrode, and a second main electrode. Since it is discharged to the outside of the element through the path, the lateral resistance of the second conductivity type base layer in the current bypass path at the time of turn-off is reduced as compared with the conventional case.

According to the present invention, the turn-on MOSFET is turned on for a certain period at turn-off, and
By causing a current of carriers having the same polarity as the majority carriers of the conductivity type emitter layer (hereinafter referred to as a second polarity carrier) to flow, the current concentration of the second polarity carriers due to the reduction of the conduction region of the current of the second polarity carriers is prevented. be able to.
Further, according to the present invention, the turn-on MOSF is formed by the first conductivity type layer formed separately from the first conductivity type emitter layer.
Since the ET is formed, the first conductivity type emitter layer does not exist in the lateral diffusion portion of the second conductivity type base layer having the highest potential in the second conductivity type base layer at turn-off. Therefore, unlike the prior art, even if the potential of the lateral diffusion portion of the second conductivity type base layer becomes equal to or higher than the built-in voltage between the first conductivity type emitter layer and the second conductivity type base layer, The injection of the second polar carrier from the one conductivity type emitter layer does not occur.

Therefore, according to the present invention, the resistance of the bypass path of the first polarity carrier at the time of turn-off can be reduced, and the injection of the second polarity carrier from the first conductivity type emitter layer can be suppressed at the time of turn-off. The turn-off characteristic can be greatly improved.

Further, in the insulated gate power semiconductor device according to the present invention (claim 2), the second conductivity type between the first conductivity type emitter layer and the first conductivity type base layer on the turn-on gate electrode side is provided. A part of the base layer is recessed toward the first conductivity type emitter layer side.

For this reason, at the time of turn-off, of the discharge path of the current of the second polarity carrier discharged to the base electrode through the second conductivity type base layer, the second part of the portion without the depression on the turn-on gate electrode side. The first conductivity type emitter layer does not exist above the discharge path of the current of the second polarity carrier discharged to the base electrode through the conductivity type base layer.

Therefore, in this discharge route, the potential of the lateral diffusion portion of the second conductivity type base layer becomes equal to or higher than the built-in voltage between the first conductivity type emitter layer and the second conductivity type base layer, The problem that the injection of the second polar carrier from the conductive type emitter layer to the second conductive type base layer is not stopped does not occur.

Therefore, according to the present invention, the second discharge path from the first conductivity type emitter layer is turned off at the time of turn-off by the discharge path.
Since the injection of polar carriers can be suppressed, the turn-off characteristic can be improved.

Further, in the insulated gate power semiconductor device according to the present invention (claim 3), the first thyristor portion is provided.
Wafer and a second wafer having a current control section for controlling the current flowing through the thyristor section.
That is, the thyristor section and the current control section for controlling the current flowing through the thyristor section are formed on separate wafers, respectively, and as a result, compared with the element in which the current control section is incorporated in the conventional main thyristor, The turn-off characteristic and turn-on characteristic can be improved. The reason is as follows.

The first conductivity type drain layer of the current control portion is connected to the first conductivity type emitter layer of the thyristor portion, and a current flows from this first conductivity type drain layer to the first conductivity type emitter layer.

The turn-on is performed by selectively short-circuiting the drain layer of the first conductivity type to the base layer of the first conductivity type by the first insulated gate structure. That is, the thyristor portion can be turned off with a structure in which the first conductivity type base layer is not connected to the second main electrode.

Therefore, unlike the case of an element such as EST in which the first conductivity type base layer is connected to the second main electrode, the turn-on characteristic is improved because the on-voltage does not increase.

Further, unlike the case of the element such as EST, since the contact layer does not exist, the parasitic thyristor due to this contact layer does not latch up at the time of turn-off, so that the turn-off characteristic is improved.

The insulated gate power semiconductor device according to the present invention (claim 4) is provided with a base electrode which is not in the conventional structure of FIG. As a result, at the time of turn-off, if a predetermined voltage is applied to the turn-off gate electrode to form a channel on the surface of the second conductivity type base layer below the turn-off gate electrode, the first polar carriers in the device are A first conductivity type base layer, a second conductivity type base layer, a base electrode (= drain electrode), a first conductivity type drain layer, the above channel,
It is discharged to the outside of the device by a bypass path of the first conductivity type emitter layer and the second main electrode. Therefore, compared to the conventional
The lateral resistance of the p-type base layer in the current bypass path at turn-off is reduced, and the turn-off characteristic is improved.

According to the present invention, the current for the second polarity carrier is reduced by reducing the conduction region of the current for the second polarity carrier by turning on the turn-on MOSFET and turning on the current for the second polarity carrier at the time of turn-off. The concentration phenomenon can be prevented.

Further, according to the present invention, a turn-on MOS is provided.
The FET is composed of a first conductivity type source layer different from the first conductivity type emitter layer. That is, the first conductivity type emitter layer does not exist in the lateral diffusion portion of the second conductivity type base layer having the highest potential in the second conductivity type base layer at turn-off. A base electrode 413b is provided between the first and second turn-on gate electrodes, and the current of the first polarity carrier is discharged from the base electrode 413b at the time of turn-off. As a result, at the time of turn-off, the second conductivity type base layer immediately below the first conductivity type emitter layer does not serve as a bypass path for the hole current.

Therefore, the potential of the lateral diffusion portion of the second conductivity type base layer becomes equal to or higher than the built-in voltage between the first conductivity type emitter layer and the second conductivity type base layer due to the current of the first polarity carrier at the time of turn-off. Even so, the injection of the second polarity carrier from the first conductivity type emitter layer does not occur, so that the turn-off characteristic is significantly improved.

In the insulated gate power semiconductor device according to the present invention (claim 5), the width of the first conductivity type source layer is set to be equal to or less than the width of the first conductivity type emitter layer. Therefore, even when the turn-on MOSFET is turned on for a certain period at the time of turn-off to allow the current of the second polarity carrier to flow, the first conductivity type source layer, the second conductivity type base layer, the first conductivity type base layer, and the second conductivity type base layer. It is possible to prevent the latch-up of the parasitic thyristor composed of the emitter layer. Further, by reducing the width of the first-conductivity-type source layer, integration becomes advantageous.

According to the method for driving an insulated gate power semiconductor device according to the present invention (claim 6), the turn-on MOSFET is turned on to pass the current of the second polarity carrier at the time of turn-off. It is possible to prevent the current concentration phenomenon of the second polar carrier due to the reduction of the conduction region of the polar carrier current.

In the case of the present invention, when the thyristor is in the on state, the first turn-on MOS which is in the on state.
A second polar carrier is injected into the first conductivity type source layer by the FET, and a parasitic thyristor composed of the first conductivity type source layer, the second conductivity type base layer, the first conductivity source layer and the second conductivity type emitter layer is formed. It may latch up.

However, even if the parasitic thyristor latches up, the first turn-on MO is turned off at turn-off.
Since the SFET is turned off, the first conductivity type source is electrically opened and the latch-up can be released. Therefore, the injection of the first polar carrier is stopped, and the device is surely turned off.

[0073]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor according to the embodiment of FIG. FIG. 4 is an equivalent circuit diagram of the insulated gate turn-off thyristor of FIG.
It shows a structure in which an IGBT connected in series with a MOSFET and a main thyristor are integrally formed.

In FIG. 1, reference numeral 101 denotes a high resistance n-type base layer, and a first p-type base layer 102 and a second p-type base layer 113 are formed on the surface of the n-type base layer 101. There is. A high-concentration n-type emitter layer 103 is formed on the surface of the first p-type base layer 102, and a cathode electrode 105 is provided on the n-type emitter layer 103.

Further, n on the first p-type base layer 102
The base electrode 10 is provided at a position adjacent to the mold emitter layer 103.
8 is provided, and the high-concentration n-type semiconductor layer 10 is short-circuited with the first p-type base layer 102 by the base electrode 108.
7 are formed.

The n-type semiconductor layer 107 and the n-type base layer 1
The turn-on gate electrode 112 is provided on the first p-type base layer 102 between the first and second electrodes 01 and 01 via the gate insulating film 111. That is, the gate electrode 112, the gate insulating film 111, the n-type base layer 101, the p-type base layer 10
2. Turn-on MOSF by n-type semiconductor layer 107
ET is configured.

On the other hand, a high-concentration n-type source layer 116 is formed on the surface of the second p-type base layer 113, and a high-concentration n-type drain layer 114 is formed at a predetermined distance from the n-type source layer 116. Has been done.

N-type drain layer 114 and n-type source layer 11
A turn-off gate electrode 110 is provided on the second p-type base layer 113 between the gate electrode 6 and the gate insulating film 109 via a gate insulating film 109. That is, the gate electrode 110, the gate insulating film 109, the n-type drain layer 114, the p-type base layer 11
3. Turn-off MOSF by n-type source layer 116
ET is configured.

Further, a drain electrode 115 is provided on the n-type drain layer 114, and a source electrode 117 is provided on the n-type source layer 116 so as to be in contact with the second p-type base layer 113 at the same time. There is.

Here, the drain electrode 115 is integrally formed with the base electrode 108 and electrically connected to the base electrode 108. Similarly, the source electrode 117 is the cathode electrode 1.
05 is formed integrally and is electrically connected to the cathode electrode 105.

On the other hand, a high-concentration p-type emitter layer 104 is formed on the back surface of the n-type base layer 101.
An anode electrode 106 is provided on the mold emitter layer 104.

The n-type base layer 1 as in the present embodiment is used.
In place of forming the p-type emitter layer 104 directly in contact with 01, an n-type buffer layer is provided between the n-type base layer 101 and the p-type emitter layer 104, and the p-type emitter indirectly in contact with the n-type base layer 101. The layer 4 may be formed.

The insulated gate turn-off thyristor of this embodiment can be switched by the gate driving method according to the time chart as shown in FIG. That is, at the time of turn-on, a positive voltage is applied to both the turn-on gate electrode 112 and the turn-off gate electrode 110 with respect to the cathode, and then a zero or negative voltage is applied to both after a fixed time (Δt ₁ ).

[0085] In FIG 1 shows an electronic current period △ t ₁ by a solid line and the hole current by a broken line. The electron current is
As shown in FIG.
SFET, n-type semiconductor layer 107, turn-on MOSF
It is injected into the n-type base layer 101 through the n channel of ET.

As a result, a hole current of an amount commensurate with the electron current is injected from the p-type emitter layer 104 into the n-type base layer 101, is sucked out into the base electrode 108, passes through the n-channel of the turn-off MOSFET, and is the source electrode. 117, that is, the cathode electrode 105.

Such a current path is a so-called IGB.
This is the same as T (insulated gate bipolar transistor). Then, after the lapse of the period Δt ₁ , the turn-off MOSF is turned on.
When ET is turned off, the escape route for holes remaining in the n-type base layer 101 is lost, the potential of the p-type base layer 102 rises, and the thyristor turns on.

On the other hand, at the time of turn-off, first, in order to turn on the turn-on MOSFET, a positive voltage is applied to the turn-on gate electrode 112 with respect to the cathode, and then the turn-off MOSFET is turned off after a fixed time (Δt ₃ ). A positive voltage is applied to the gate electrode 110 with respect to the cathode.

In FIG. 1, the electron current in the period Δt ₂ is shown by a solid line, and the hole current bypass path is shown by a broken line.

The hole current is drained to the base electrode 108 in the immediate vicinity of the n-type emitter layer 103, as shown in the figure,
n-type drain layer 114, turn-off gate electrode 110
It is discharged to the outside of the device from the source electrode 117, that is, the cathode electrode 105, through the lower n-channel (CH1) and the n-type source layer 116.

The path of such a current is the same as that of the IGBT and is in a transistor state. Therefore, after a positive voltage is applied to the turn-off gate electrode 110 with respect to the cathode, and a certain time (Δt ₂ ) is applied, zero or a negative voltage is applied to the turn-on gate electrode 112 with respect to the cathode to turn on. When the power MOSFET is turned off, electron injection is stopped and the device is turned off.

At this time, in the structure shown in FIG. 1, as is apparent from comparison with the conventional structure shown in FIG. 15, the base electrode 108, which is a hole-extracting electrode at the time of turn-off, is located immediately above the n-type emitter layer 3. It is formed in direct contact with the p-type base layer 102 in the vicinity.

Therefore, the lateral resistance of the p-type base layer 102 is reduced in the bypass path of the hole current, and thus the voltage drop due to the bypassed hole current is smaller than that in the conventional structure, and the high turn-off capability is achieved. can get.

Further, since the turn-on MOSFET is temporarily turned on at the time of turn-off, the electron current flows uniformly, which is different from the turn-off in the conventional insulated gate type turn-off thyristor, and the turn-off due to the reduction of the conduction path of the electron current. There is no reduction in current.

Further, in this embodiment, the M for turn-on is used.
The OSFET has a high-concentration n-type semiconductor layer 107 closer to the turn-on gate electrode 112 than the n-type emitter layer 103.
It consists of.

Therefore, in the IGBT period at turn-off, the p-type base layer 1 immediately below the n-type emitter layer 103 is formed.
Since 02 does not serve as a bypass path for the hole current, the turn-off characteristic is significantly improved.

FIG. 3 is a time chart showing another gate driving method applied to the insulated gate type turn-off thyristor of the present invention. The driving method is basically the same as that shown in FIG. 2, but different in the following points.

That is, the turn-on gate electrode 112
, A positive voltage is applied from the turn-on to the turn-off, and a positive voltage is applied to the turn-off gate electrode 110 during the turn-off period. According to this gate driving method, malfunction can be prevented, and more reliable switching operation can be performed as compared with the previous driving method.

(Second Embodiment) FIG. 5 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor of the embodiment. In the following figures, the same reference numerals as those used in the preceding figures indicate the same or corresponding parts, and detailed description thereof will be omitted.

The feature of this embodiment is that the high-concentration p-type base layer 102a is formed in the first p-type base layer 102 so as not to cover the channel region of the turn-on MOSFET, and the second p-type base layer 113 is formed. Turn-off MOS
This is because the high-concentration p-type base layers 113a and 113b were formed so as not to cover the channel region of the FET. According to this embodiment, the lateral resistances of the first p-type base layer 102 and the second p-type base layer 113 can be reduced without changing the threshold voltages of the turn-on MOSFET and the turn-off MOSFET. Higher turn-off capability can be obtained without deteriorating the characteristics of the turn-on MOSFET and the turn-off MOSFET.

(Third Embodiment) FIG. 6 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor of the embodiment.

The feature of this embodiment is that the n-type emitter layer 10 is provided.
3 and n-type semiconductor layer 107 and base electrode 108
the base electrode 1 on the p-type base layer 102 at a position facing a
08b is provided.

According to this embodiment, when the thyristor state shifts to the IGBT state (transistor state), n
Type base electrode 108a, 10 on both sides of the emitter layer 103
Hole current is discharged from 8b.

Therefore, the hole current flowing through each hole current path becomes smaller than that of the first and second embodiments, and the lateral resistance and hole of the p-type base layer 102 below the n-type emitter layer 103 are reduced. The voltage drop due to the current is reduced and a higher turn-off capability is obtained.

(Fourth Embodiment) FIG. 7 shows a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor of the embodiment.

The feature of this embodiment is that the n-type semiconductor layer 10 is provided.
7, base electrode 108 and turn-on gate electrode 1
The twelve pairs are formed on both sides of the n-type emitter layer 103 with the n-type emitter layer 103 sandwiched therebetween.

According to this embodiment, when the thyristor state is switched to the IGBT state (transistor state), n
Since the hole current is discharged from both sides of the type emitter layer 103 and the channel width of the turn-on MOSFET can be increased, the on-resistance in the IGBT state is reduced and at the same time, more uniform electron injection is performed. The turn-off ability is much higher than that of the above embodiment.

(Fifth Embodiment) FIG. 8 shows the fifth embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor of the embodiment.

The main structure of this embodiment is the same as that of FIG. 7, but in this embodiment, the n-type drain layer 114,
A turn-on MOSFET composed of the p-type base layer 113, the n-type base layer 101, etc. is added. As a result, the total channel width of the turn-on MOSFET becomes wider, and the on-resistance in the IGBT state can be further reduced.

(Sixth Embodiment) FIG. 9 shows a sixth embodiment of the present invention.
FIG. 3 is a cross-sectional view showing an element structure of an insulated gate turn-off thyristor of the embodiment.

The main structure of this embodiment is the same as that of FIG. 8, but in this embodiment, the n-type source layers 116 and p are formed.
A turn-on MOSFET composed of the type base layer 113, the n-type base layer 101, etc. is added.
As a result, as in the case of the fifth embodiment, the total channel width of the turn-on MOSFET becomes wider, and I
The ON resistance in the GBT state can be further reduced.

(Seventh Embodiment) FIG. 10 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a seventh embodiment of the present invention.

In the present embodiment, the n-type emitter layer 103 and the n-type source layer 116 are arranged so as to be adjacent to each other with the insulating film 118 interposed therebetween.
The type drain layer 114 is the turn-on gate electrode 112.
They are arranged so as to be adjacent to each other with a pinch in between.

The cathode electrode 105 and the source electrode 117 are integrally formed so as to straddle the insulating film 118, and the base electrode 108 and the drain electrode 115 are integrally formed so as to straddle the turn-on gate electrode 112.

According to this embodiment, the cathode electrode 105
Since the source electrode 117, the base electrode 108, and the drain electrode 115 are integrally formed, it is not necessary to use a microfabrication technique for forming the electrodes 105, 117, 108, 115.

Further, the cathode electrode 105 and the source electrode 1
17. Since the length of the wiring connecting the base electrode 108 and the drain electrode 115 is shortened and the wiring resistance is reduced, a large turn-off capability can be obtained.

(Eighth Embodiment and Ninth Embodiment) FIG.
1 and 12 are cross-sectional views showing the element structure of an insulated gate turn-off thyristor according to an eighth embodiment and a ninth embodiment of the present invention, respectively. FIG. 14 is an equivalent circuit diagram of the insulated gate turn-off thyristor of these embodiments, and shows a structure in which a MOSFET and a resistor are connected in series to an IGBT, and the IGBT and the main thyristor are integrally formed.

The eighth and ninth embodiments are different from the embodiments shown in FIGS. 1 and 6 in that a resistor having a predetermined size is provided between the cathode electrode terminal K and the base electrode 108. The body 120 is inserted.

The insulated gate turn-off thyristor of this embodiment can be switched by the gate driving method according to the time chart as shown in FIG. This gate driving method is basically the same as that of FIG. 2, except that it is not necessary to apply a positive voltage to the turn-off gate electrode 110 at turn-on.

That is, in the case of the present embodiment, when a positive voltage is applied to the turn-on gate electrode 112 at the time of turn-on with respect to the cathode, the resistor 120, the base electrode 108, the n-type semiconductor layer 107 from the cathode electrode terminal K, Electrons are injected into the n-type base layer 101 through the turn-on MOSFET, and the thyristor turns on.

The turn-on gate electrode 112 is
As indicated by the broken line in FIG. 13, a positive voltage may be kept applied from the turn-on to the turn-off. This enables a more uniform and reliable turn-on operation.

(Tenth Embodiment) FIG. 15 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a tenth embodiment of the present invention.

The insulated gate turn-off thyristor of this embodiment is similar to that of FIG. 1 except that the second p-type base layer 1 is used.
13 is the same layer as the first p-type base layer 102, the n-type source layer 116 is the same layer as the n-type emitter layer 103, and the source electrode 117 is the same electrode as the cathode electrode 105. is there.

In the present embodiment as well, at the time of turn-off, holes in the device are discharged through the base electrode 108b, so that the p-type base layer 102 below the n-type emitter layer 103 is discharged.
It is possible to effectively prevent the latch-up due to the hole current flowing in.

Therefore, also in the insulated gate type turn-off thyristor of the present embodiment, the turn-off capability is higher than in the conventional case, as in the case of FIG.

(Eleventh Embodiment) FIG. 16 is a sectional view showing the element structure of an insulated gate turn-off thyristor according to the eleventh embodiment of the present invention.

The insulated gate turn-off thyristor of this embodiment is similar to that of FIG. 6 except that the second p-type base layer 1 is used.
13 is the same layer as the first p-type base layer 102. Accordingly, the n-type source layer 116 becomes the same layer as the n-type emitter layer 103, and the source electrode 117 becomes the same electrode as the cathode electrode 105.

In the present embodiment as well, at the time of turn-off, holes in the element are discharged through the base electrode 108b, so that the turn-off ability is higher than in the conventional case as in the case of FIG.

(Twelfth Embodiment) FIG. 17 is a plan view showing an element structure of an insulated gate turn-off thyristor according to a twelfth embodiment of the present invention. 18 and 19 are an AA ′ sectional view and an BB ′ sectional view of the insulated gate turn-off thyristor of FIG. 17, respectively.

In the figure, reference numeral 203 denotes a high resistance n-type base layer, and a p-type base layer 204 is selectively formed on the surface of the n-type base layer 203. An n-type emitter layer 207 is selectively formed on the surface of the p-type base layer 204. On the other hand, a high-concentration p-type emitter layer 207 is formed on the back surface of the n-type base layer 203.

N-type emitter layer 207 and n-type base layer 20
On the p-type base layer 204 between the gate insulating film 2 and
A turn-on gate electrode 214 is provided via 16
An n-channel turn-on MOSFET whose source is the n-type emitter layer 207 is configured.

A base electrode 213 is formed on the p-type base layer 204.
However, the cathode electrode 211 is formed on the n-type emitter layer 207.
However, the p-type emitter layer 206 is provided with the anode electrode 210.

Here, the base electrode 213 on the side opposite to the turn-on gate electrode 214 is connected to the p-type base layer 204 via the contact hole 218 as in the conventional case.

Unlike the prior art, the turn-on gate electrode 214 is provided with depressions at regular intervals in the portion overlapping the n-type emitter layer 207 (two depressions are shown in FIG. 17). The base electrode 213 is connected to the p-type base layer 204 through a contact hole 218 ′ provided in the hollow portion.

The p-type base layer 204 where the turn-on gate electrode 214 is recessed protrudes to the right side as shown in FIG. 17 so that it can make contact with the base electrode 213.

In other words, the turn-on gate electrode 21
The p-type base layer 204 on the fourth side is a turn-on MOSFE.
Indentations are provided at regular intervals in the channel width direction of T (concavo-convex portions are provided), and p of a portion without a depression (convex portion) is formed.
A recess of the gate electrode 214 is formed in the mold base layer 204.

Although not shown, a turn-off MOSFET similar to the conventional insulated gate turn-off thyristor of FIG. 33 is formed in the p-type base layer 204.

That is, the p-type base layer 204 located at a predetermined distance from the n-type source layer and the type emitter layer 207.
Has an n-type drain layer formed on its surface, and a turn-off gate electrode is disposed on the p-type base layer 204 between the n-type drain layer and the n-type emitter layer 207 via a gate insulating film. An n-channel turn-off MOSFET having the n-type emitter layer 207 as a source is formed.

The drain electrode contacting the n-type drain layer is also in contact with the p-type base layer 204 at the same time, and the p-type base layer 204 and the n-type drain layer are short-circuited by this drain electrode.

To turn on this element, a positive voltage is applied to the turn-on gate electrode 217 with respect to the cathode. As a result, the turn-on MOSFET is turned on, and the n-type emitter layer 207 to the n-type base layer 20 are turned on.
Electrons are injected into 3 and the device is turned on.

On the other hand, to turn off, the turn-off MOSFET is turned on and the base electrode 213 and the cathode electrode 211 are short-circuited.

At this time, as shown by the broken line in FIG. 17, the holes h are generated in the p-type base layer 20 below the n-type emitter layer 207.
4 does not pass through, but is sucked to the base electrode 213 through the p-type base layer 204 where there is no depression, and discharged outside the element.

Therefore, even when the anode current is large, the voltage drop due to the hole current and the resistance of the p-type base layer 204 exceeds the built-in voltage between the p-type base layer 204 and the n-type emitter layer 207, and the device latches up. However, it is possible to prevent the problem of being unable to turn off.

The holes do not pass through the p-type base layer 204 below the n-type emitter layer 207 because the resistance of the p-type base layer 204 is increased due to the presence of the n-type emitter layer 207.

(Thirteenth Embodiment) FIG. 20 is a plan view showing the element structure of an insulated gate turn-off thyristor according to the thirteenth embodiment of the present invention. In addition, FIG.
CC 'of the insulated gate type turn-off thyristor of FIG.
It is sectional drawing.

The insulated gate turn-off thyristor of this embodiment is different from that of the twelfth embodiment in that the n-type emitter layer 207 is not straightly extended in a stripe shape, but is formed in the recessed portion of the turn-on gate electrode 214. The n-type emitter layer 207 is not provided, and the base electrode 213 is laterally extended to this recessed portion, so that three sides (upper side, lower side, left side) of the n-type emitter layer 207 are surrounded by the base electrode 213. Especially.

According to this embodiment, the n-type emitter layer 20
Since the number of holes discharging holes that do not pass through the p-type base layer 204 under 7 increases (becomes longer), a higher turn-off capability than that in the twelfth embodiment can be obtained.

(Fourteenth Embodiment) FIG. 22 is a plan view showing the element structure of an insulated gate turn-off thyristor according to the fourteenth embodiment of the present invention.

The basic structure of the insulated gate type turn-off thyristor of this embodiment is the structure of the insulated gate type turn-off thyristor of FIG. 20 in which the depression of the turn-on gate electrode 214 is removed.

That is, the turn-on gate electrode 214
Has a stripe shape parallel to the channel width direction of the turn-on MOSFET. Further, the turn-on gate electrode 214 extending in the lateral direction is shortened corresponding to the disappearance of the depression.

Also in this embodiment, the holes h are sucked out to the base electrode without passing through the p-type base layer 204 below the n-type emitter layer 207. Therefore, at the time of turn-off as in the twelfth and thirteenth embodiments. It is possible to prevent latch-up due to the hole current in the.

At the time of turn-off, by applying a negative voltage to the turn-on gate electrode 214 with respect to the cathode, the p-type base layer 204 immediately below the turn-on gate electrode 214 from which holes are absorbed is in the accumulation mode. Therefore, the hole discharge resistance can be further lowered.

(Fifteenth Embodiment) FIG. 23 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a fifteenth embodiment of the present invention. The plan view of this insulated gate turn-off thyristor is the same as that of FIG. 17, and the sectional view of FIG. 23 corresponds to the AA ′ section of FIG.

The insulated gate turn-off thyristor of this embodiment differs from that of FIG. 18 in that the n-type emitter layer 2
This is because the low-concentration p-type well layer 219 is provided on the p-type base layer 204 immediately below 07.

In the case of the conventional structure, since the p-type base layer 204 immediately below the n-type emitter layer 207 serves as a hole bypass path, if the concentration of the p-type base layer 204 is lowered,
Since the resistance becomes high and the voltage drop due to the hole current becomes large, there is a problem that latch-up easily occurs and the controllable current becomes small.

However, in the present embodiment, holes can be discharged without passing through the p-type base layer 204 directly below the n-type emitter layer 207, so that the p-type base layer 204 directly below the n-type emitter layer 207 has a low concentration of p. A mold well layer 219 can be provided.

Therefore, according to the present embodiment, the low-concentration p-type well layer 219 makes it possible to increase the electron injection efficiency when the thyristor is in the on-state, so that not only the turn-off capability but also the device in the on-state can be obtained. The resistance can be lowered.

(Sixteenth Embodiment) FIG. 24 is a sectional view showing the element structure of an insulated gate turn-off thyristor according to the sixteenth embodiment of the present invention. The plan view of this insulated gate turn-off thyristor is the same as that of FIG. 17, and the sectional view of FIG. 24 corresponds to the BB ′ section of FIG.

The insulated gate turn-off thyristor of this embodiment differs from that of FIG. 19 in that the p-type base layer 20 is used.
This is because a low-concentration p-type well layer 219 is provided in the No. 4 structure. The p-type well layer 219 is formed on the turn-on gate electrode 214 side so as to be in contact with the n-type emitter layer 207.

According to this embodiment, the p-type well layer 219 is used.
As a result, as in the fifteenth embodiment, the electron injection efficiency can be increased and the threshold voltage of the turn-on MOSFET can be lowered, so that a low on-voltage can be obtained. Therefore, similar to the fifteenth embodiment, not only the turn-off ability but also the on-characteristics can be improved.

(Seventeenth Embodiment) FIG. 25 is a sectional view showing the structure of an insulated gate power semiconductor device according to the seventeenth embodiment of the present invention.

This insulated gate type power semiconductor device comprises a lower first wafer on which a thyristor portion is formed and an upper second wafer on which a current control portion for controlling the current flowing through this thyristor portion is formed. Are stacked in two layers.

The thyristor portion of the first wafer is pnpn.
The thyristor has a structure and an insulated gate structure for selectively short-circuiting the n-type emitter layer and the n-type base layer of the thyristor.

The thyristor has a high resistance n-type base layer 314, a p-type base layer 315 formed on the surface of the n-type base layer 314, and an n-type base layer 315 formed on the surface of the p-type base layer 315. Emitter layer 316 and n-type base layer 3
It is composed of a p-type emitter layer 313 formed on the back surface of 14.

The p-type emitter layer 313 is provided with an anode electrode 318, and the p-type base layer 315 is provided with a base electrode 319. In addition, the n-type emitter layer 31
6 and the n-type base layer 314, a gate electrode 317 is provided on the p-type base layer 315 via a gate insulating film 309, and the n-type emitter layer 316 and the n-type base layer are formed by the MOS structure gate electrode. The layer 314 can be selectively short-circuited.

On the other hand, the current control section of the second wafer is composed of a MOSFET for controlling the current flowing through the thyristor and a Zener diode for discharging holes in the thyristor at turn-off.

The MOSFET has the n-type drain layer 30.
2, the n-type semiconductor layer 306 provided on the n-type drain layer 302, the p-type well layer 304 formed in the n-type semiconductor layer 306, and the p-type well layer 304. The n-type source layer 307 and the n-type source layer 3
07 and the n-type semiconductor layer 306 between the p-type well layer 304
It is composed of a gate electrode 308 provided on the gate insulating film 309.

P-type well layer 304 and n-type source layer 3
07 is the cathode electrode 3 via the cathode connection electrode 310
Connected to 00. A drain electrode 311 is provided on the n-type drain layer 302, and the n-type drain layer 302 is connected to the emitter electrode 320 via the drain electrode 311.

The Zener diode has the p-type isolation layer 3
The n-type cathode layer 303 is separated from the n-type drain layer 302 by 01, and the p-type anode layer 305 is formed in contact with the n-type cathode layer 303.

The p-type anode layer 305 is connected to the cathode electrode 300 via the cathode connecting electrode 310. The n-type cathode layer 303 is the base connection electrode 31.
2 to the base electrode 319.

To turn on this element, a positive voltage is applied to the gate electrodes 308 and 317 with respect to the cathode.

As a result, the MOSFET of the current control section is turned on, current is supplied to the n-type emitter layer 316 of the thyristor, and the n-type emitter layer 316 and n-type base layer 314 of the thyristor are short-circuited. Electrons are injected from the n-type emitter layer 316 to the n-type base layer 314. As a result, the thyristor becomes conductive and the anode current (main current) flows between the anode electrode 318 and the cathode electrode 300.

At this time, since the thyristor is conductive, the base potential of the thyristor does not rise so much. Therefore, the Zener diode of the current control unit does not operate, the holes in the thyristor are not discharged to the outside of the element through the base electrode 319, the base connection electrode 312, and the Zener diode, and the thyristor has a sufficiently low ON voltage. Operate.

On the other hand, to turn off, the gate electrode 3
A zero or negative voltage is applied to the cathodes 08 and 317.

As a result, the supply of current from the MOSFET of the current controller to the n-type emitter layer 316 of the thyristor is stopped. As a result, the base potential of the thyristor rises and the Zener diode becomes conductive, holes in the thyristor are discharged to the outside of the element through the base electrode 319, the base connection electrode 312, and the Zener diode, and the element is turned off.

In this embodiment, the thyristor section and the current control section for controlling the current flowing through the thyristor section are formed on different wafers, and the cathode to the thyristor n are formed.
The current flowing through the type emitter layer 316 is basically controlled by the dedicated MOSFET of the current control unit. Therefore, the channel resistance of the MOSFET can be determined without considering the thyristor, and high-speed switching is possible.
Furthermore, since the MOSFET can be minutely formed separately from the thyristor, the voltage drop due to the MOSFET is extremely small.

Further, since the thyristor takes charge of the main withstand voltage, the MOSFET of the current control section needs almost no withstand voltage, and only the current conduction characteristic needs to be secured. For this reason, the breakdown voltage of the entire element is determined by the thyristor and is high.

Therefore, according to the insulated gate power semiconductor element of the present embodiment, unlike the conventional EST, the MOSFET (current control section) is not incorporated in the thyristor, so that high breakdown voltage and high speed operation are possible. become.

Further, unlike the conventional EST, since the p-type base layer 315 is not in contact with the anode electrode 300, the on-voltage can be easily reduced. In addition, since the on-voltage decreases, the problem of heat generation (heat dissipation) can be easily solved.

Further, unlike the conventional EST, since there is no contact layer, there is no problem that the parasitic thyristor due to the contact layer latches up and turn-off becomes impossible.

By reducing the channel resistance, reducing the on-resistance, and preventing the parasitic thyristor from latching up, the turn-on characteristic (conduction characteristic) of the thyristor can be greatly improved.

Further, unlike the case of the GTO, since the voltage is controlled, there is no problem that the gate circuit (current control section) becomes large, and the miniaturization is easy.

When the first and second wafers are overlapped with each other, the alignment accuracy between the wafers seems to be a problem, but what is important in this device is that the electrodes to be connected (base connecting electrode 312 and Base electrode 319, drain electrode 3
11 and the position of the emitter electrode 320) are only important,
Usually, these electrodes are much larger than the structures of other parts of the device, so that there is almost no problem in alignment accuracy.

FIG. 26 is a plan view of the first and second wafers. The same figure (a) is the 2nd wafer, the same figure (b)
Indicates the first wafer.

The reason for using the circular wafer as shown in FIG. 26 is as follows. That is, in consideration of incorporation into a system with a high breakdown voltage element, a pressure contact structure is often adopted, but in that case, from the viewpoint of preventing a stress problem, if a circular shape having good symmetry is used, This is because it is often advantageous.

Since the first wafer has thyristors,
It is necessary to have pressure resistance. For this reason, as shown in FIG. 26B, a junction termination portion 325 having a structure for withstanding voltage such as RESURF is provided in the range of the first wafer. Further, it is better that the base electrode pad 324 that discharges holes at the time of turn-off also has high symmetry. Therefore, it is easy to dispose the base electrode pad 324 at the center of the first wafer.

Although not shown because it becomes fine in FIG. 26B, in order to sufficiently improve the turn-off characteristic, holes are exhausted by radially extending the base electrode from the base electrode pad 324. It is effective to lower the resistance sufficiently.

At this time, the base electrodes do not have to be connected to each other and may be formed in an island shape. This is because the base electrodes are connected to each other by stacking the second wafer and connecting the drain electrode and the base electrode.

(Eighteenth Embodiment) FIG. 27 is a sectional view showing the structure of an insulated gate power semiconductor element according to the eighteenth embodiment of the present invention.

The insulated gate power semiconductor device of this embodiment differs from that of the seventeenth embodiment in that the first wafer is connected to the second wafer via spacers 326 and 327.

When the first wafer and the second wafer are stacked, it is of course possible to directly stack them. For example,
In the case of pressing and stacking, stress concentration occurs, which causes problems such as destruction of the wafer.

However, if the spacers 326 and 327 are overlapped with each other as in this embodiment, the problem due to stress concentration can be prevented. Further, by connecting the gate wiring connecting the gate electrodes to the inside of the spacer, the gate electrodes can be easily connected.

(Nineteenth Embodiment) FIG. 28 is a sectional view showing the essential structure of an insulated gate power semiconductor element according to the nineteenth embodiment of the present invention.

The feature of this embodiment is that, instead of applying a voltage to the gate electrode to turn on the thyristor, the gate insulating film 309 is irradiated with light to form a channel and turn on the thyristor. According to the present embodiment, since light is used, noise-resistant switching is possible. In the figure, reference numeral 328 denotes an optical fiber 328 for guiding light to the gate insulating film 309.

(Twentieth Embodiment) Next, a method for forming a second wafer having the current control section will be described. FIG. 29 is a process cross-sectional view showing the method for forming the first wafer.

First, as shown in FIG. 29A, a high-concentration n-type semiconductor substrate 340 is prepared, and then FIG.
As shown in FIG. 29C, the p-type impurity 330 is selectively ion-implanted from the back surface and the front surface of the n-type semiconductor substrate 340, and the p-type impurity 330 is activated / diffused by an annealing treatment, as shown in FIG. As described above, the p-type separation layer (p-type diffusion layer) 301 is formed, and the n-type semiconductor substrate 340 is formed as an M
The n-type drain layer 302 of the OSFET and the n-type cathode layer 303 of the Zener diode are separated.

Here, the p-type separation layer 301 is formed on both sides of the n-type semiconductor substrate 303. Generally, a certain thickness is required when handling a wafer, and diffusion from one side is an n-type. This is because there is a possibility that the drain layer 302 and the n-type cathode layer 303 of the Zener diode cannot be separated.

As long as a sufficiently high separation can be obtained, of course, diffusion from one side is sufficient, and even if diffusion is from both sides, it is not necessary that the p-type separation layers 301 be connected and integrated.

Next, as shown in FIG. 29D, after the n-type semiconductor layer 331 is formed on the entire surface by epitaxial growth or adhesion, as shown in FIG. 29E, the surface of the n-type semiconductor layer 331 is formed. The p-type anode layer 305 is formed in contact with the n-type cathode layer 303.

Next, as shown in FIG. 29F, after the p-type well layer 304 and the n-type source layer 307 are formed on the surface of the n-type semiconductor layer 331, the gate insulating film 309 and the gate electrode 308 are sequentially formed. To do.

Finally, as shown in FIG. 29G, the cathode connecting electrode 310, the drain electrode 311, and the base connecting electrode 312 are formed to complete the first wafer.

As described above, the first wafer can be easily obtained by the conventional process technique. Further, as the thyristor of the second wafer, the processes of thyristor, MOS thyristor, and GTO that are normally performed can be used as they are.

(Twenty-first Embodiment) FIGS. 30A to 30C are process sectional views showing a method for forming a second wafer according to a twenty-first embodiment of the present invention.

First, as shown in FIG. 30A, a high resistance n-type semiconductor substrate 332 is used. Then, as shown in FIG. 30B, an n-type impurity 330 is formed on the n-type semiconductor substrate 332.
After ion-implanting a and 330b, the n-type impurities 330a and 330b are activated and diffused by an annealing process, so that the high-concentration n-type drain layer 302 and the Zener diode of the MOSFET are formed as shown in FIG. Forming a high-concentration n-type cathode layer 303.

The reason for forming the n-type drain layer 302 and the n-type cathode layer 303 on both sides of the substrate in this manner is the 20th.
It is the same as that of the p-type separation layer 301 of the above embodiment.

Here, the remaining high-resistance n-type semiconductor substrate 332 plays the role of a separation layer. However, if this is not sufficient, the p-type separation layer 3 is formed as shown in FIG.
01 may be formed. The subsequent steps are the same as those in the twentieth embodiment. (Twenty-second Embodiment) FIGS. 31A to 31D are process sectional views showing a method for forming a second wafer according to a twenty-second embodiment of the present invention.

First, as shown in FIG.
The substrate shown in (d) is bonded to another substrate having a high-concentration p-type diffusion layer as the p-type anode layer 305 formed on the surface thereof. Next, as shown in FIG. 31B, the surface of the other substrate is polished to expose the surface of the p-type anode layer 305. Finally, the first wafer shown in FIG. 31C is completed by the same steps as those in FIGS. 29F and 29G.

When the first wafer is formed by adhering two substrates to each other as in this embodiment,
There is an advantage that various diffusion layers can be previously formed on each substrate. (Twenty-third Embodiment) FIG. 35 is a sectional view showing the element structure of an insulated gate turn-off thyristor according to the twenty-third embodiment of the present invention.

In the figure, reference numeral 401 denotes a high resistance n-type base layer, and a p-type base layer 402 is selectively formed on the surface of the n-type base layer 401. On the surface of the p-type base layer 402, a high concentration n-type emitter layer 403a,
403b are formed so as to be separated from each other by a predetermined distance, and cathode electrodes 405a and 405b are provided on the n-type emitter layers 403a and 403b, respectively.

A high concentration n-type source layer 407a is formed on the surface of the p-type base layer 402 at a position separated from the n-type emitter layer 403b by a predetermined distance. This n-type source layer 4
A first turn-on gate electrode 410 is provided on the p-type base layer 402 between the 07a and the n-type emitter layer 403b via a gate insulating film 409. That is,
The gate electrode 410, the n-type emitter layer 403b, the n-type source layer 407a, and the like form a first turn-on FOSFET having the region CH3 as a channel region.

Further, a high concentration of n is formed on the surface of the p-type base layer 402 at a position separated from the n-type source layer 407a by a predetermined distance.
The mold source layer 407b is formed. n-type source layer 4
07a and 407b have base electrodes 408a and 4
08b is provided, and the base electrodes 408a and 408b are electrically connected to each other. Then, the n-type source layer 4
07b and the n-type base layer 401 between the p-type base layer 40
A second turn-on gate electrode 412 is provided on the second insulating film 411 via a gate insulating film 411. That is, the gate electrode 412, the n-type source layer 407b, the n-type base layer 401, and the like form a second turn-on MOSFET having the region CH1 as a channel region.

Here, the second turn-on gate electrode 4
12 is integrally formed with the first turn-on gate electrode 410 and electrically connected thereto, and these turn-on gate electrodes 410 and 412 are connected to the same turn-on gate input terminal G1.

On the other hand, a high-concentration n-type drain layer 414 is formed on the surface of the p-type base layer 402 at a predetermined distance from the n-type emitter layer 403a and the n-type source layers 407a and 407b. A turn-off gate electrode 417 is provided on the p-type base layer 402 between the n-type drain layer 414 and the n-type emitter layer 403a via a gate insulating film 416. That is, the gate electrode 4
17, n-type emitter layer 403a, n-type drain layer 414
As a result, a turn-off MOSFET having the region CH2 as a channel region is configured.

Further, the n-type emitter layers 403a and 403b of the p-type base layer 402 and the n-type source layers 407a and 407a.
Base electrodes 421a and 413 at positions close to 07b.
b is provided. Specifically, the n-type emitter layer 40
A base electrode 413a is provided in contact with the p-type base layer 402 between 3a and 403b.
A base electrode 413b is provided in contact with the p-type base layer 402 between 7a and 407b.

A drain electrode 415 is arranged on the n-type drain layer 414 so as to be in contact with the p-type base layer 402 at the same time. Here, the drain electrode 415 is integrally formed with the base electrodes 413a and 413b and electrically connected to the base electrodes 413a and 413b.

On the other hand, a high-concentration p-type emitter layer 404 is formed on the back surface of the n-type base layer 401.
An anode electrode 406 is provided on the mold emitter layer 404.

It should be noted that p directly contacting the n-type base layer 401
Instead of forming the type emitter layer 404, an n type buffer layer is provided between the n type base layer 401 and the p type emitter layer 404, and the p type emitter layer 404 indirectly contacting the n type base layer 401 is formed. May be.

The insulated gate thyristor of this embodiment can be switched by the gate driving method according to the time chart shown in FIG.

That is, at the time of turn-on, zero or a negative voltage is applied to the turn-off gate electrode 417 with respect to the cathode, and a positive voltage is applied to the turn-on gate electrodes 410 and 412 with respect to the cathode.

As a result, from the n-type emitter layer 403b to the n-channel CH3 below the gate electrode 410, the n-type source layer 4 is formed.
07a, electrodes 408a and 408b, n-type source layer 407
b, n through the n-channel CH1 under the gate electrode 412
Electrons are injected into the type base layer 401, and holes corresponding to the injection amount of the electrons are injected from the p type emitter layer 404 into the n type base layer 401, so that the thyristor is turned on.

On the other hand, at the time of turn-off, first, in order to turn on the turn-on MOSFET, a positive voltage is applied to the turn-on gate electrodes 410 and 412 with respect to the cathode, and after a certain time (Δt1), the turn-off gate is turned on. A positive voltage is applied to the electrode 417 with respect to the cathode.

The turn-on gate electrodes 410, 4
12 may be applied with a positive voltage from the turn-on to the turn-off, and the turn-off gate electrode 417 may be applied with a positive voltage during the off-period.

FIG. 35 shows the turn-on gate electrode 41.
Turn on MOSF by applying positive voltage to 0,412
The electron current when ET is turned on is a solid line, and
A dashed line indicates a bypass path of the hole current when a positive voltage is applied to the turn-off gate electrode 417 to turn on the turn-off MOSFET.

The hole current is the n-type source layers 408a, 40
8b, it is sucked out to the base electrode 413b, and is discharged to the outside of the element through the drain electrode 415, the n-type drain layer 414, the n-channel CH2 under the turn-off gate electrode 417, and the n-type emitter layer 403a.

The path of such a current is the same as that of the IGBT and is in a transistor state. Therefore, after a positive voltage is applied to the turn-off gate electrode 417 with respect to the cathode, zero or negative voltage is applied to the turn-on gate electrodes 410 and 412 with respect to the cathode after a predetermined time (after Δt2). Then, when the turn-on MOSFET is turned off, the injection of electrons is stopped and the element is turned off.

Here, in the present embodiment, the hole current is discharged to the outside of the element through the above-mentioned bypass path, so that the side of the p-type base layer 402 in the bypass path of the hole current at the turn-off is compared to the conventional case. Directional resistance is reduced. As a result, the potential drop due to the bypassed hole current becomes smaller than in the conventional case, and a high turn-off capability can be obtained. Also, when turning off, the MOSF for turning on is temporarily
Since ET is turned on, the electron current flows uniformly,
Unlike the case of the turn-off in the conventional insulated gate turn-off thyristor, the turn-off current does not decrease due to the reduction of the conduction path of the electron current.

In the present embodiment, the second turn-on MOSFET has an n-type emitter layer 403b different from the n-type emitter layer 403b.
It is composed of the mold source layer 407b. That is,
The n-type emitter layers 403a and 403b do not exist in the lateral diffusion portion of the p-type base layer 402 which has the highest potential in the p-type base layer 402 at the time of turn-off. A base electrode 413b is provided between the first turn-on gate electrode 410 and the second turn-on gate electrode 412, and a hole current is discharged from the base electrode 413b at the time of turn-off. As a result, the IGBT at turn-off
During the period, the p-type base layer 402 immediately below the n-type emitter layers 403a and 403b does not serve as a bypass path for the hole current.

Therefore, even if the potential of the lateral diffusion portion of the p-type base layer 402 is changed by the hole current at the time of turn-off, the n-type emitter layers 403a and 403b and the p-type base layer 40.
Even if the voltage becomes higher than the built-in voltage between 2 and 2, electron injection from the n-type emitter layers 403a and 403b does not occur, so the turn-off characteristic is significantly improved.

In the case of the driving method of this embodiment, the n-type source layer 40 is turned on during the ON period or the IGBT period.
7a, 407b, p-type base layer 402, n-type base layer 4
01 and the p-type emitter layer 404 may cause a parasitic thyristor to latch up.

However, even if the parasitic thyristor latches up, the first and second turn-on MOSFETs are turned off at the time of turn-off, so the n-type source layer 4
07a and 407b are electrically opened, and latch-up can be released. Therefore, electron injection is stopped and the main thyristor is reliably turned off.

FIG. 37 shows an equivalent circuit of the insulated gate turn-off thyristor of this embodiment. A turn-off MOSFET is inserted between the n-type emitter and the p-type base of the main thyristor Thy, and two series-connected turn-on MOSFs are connected between the n-type emitter and the p-type base.
ET is inserted. Parasitic thyristor Th consisting of n-type source, p-type base, n-type base and p-type emitter
The y2 is connected in series with the turn-on MOSFET, and when turned off, the turn-off MOSFET is turned off to surely turn off.

(Twenty-fourth Embodiment) FIG. 38 is a plan view of an insulated gate turn-off thyristor according to a twenty-fourth embodiment of the present invention. 39 and 40 are sectional views taken along the lines AA 'and BB' of FIG. 38, respectively.

In this embodiment, the n-type emitter layer 403 is divided and arranged in a rectangular shape, and the first turn-on gate electrode 410 and the turn-off gate electrode 417 are provided along the pair of opposite sides. Then, the n-type emitter layer 403
And the n-type source layer 407 so as to sandwich the base electrode 4
13 is formed.

Therefore, according to this embodiment, holes are discharged from both sides of the n-type emitter layer 403 and the n-type source layer 407, so that the bypass resistance is reduced and a higher turn-off capability is obtained.

In addition, in the embodiment, the n-type emitter layer 40
3 has a width L1 set to be equal to or smaller than the width L2 of the n-type source layer 407. Therefore, the MO for turn-on at turn-off
Even when the SFET is turned on for a certain period of time to allow an electron current to flow, it is possible to prevent the parasitic thyristor composed of the n-type source layer 107, the p-type base layer 402, the n-type base layer 401 and the p-type emitter layer 404 from latching up. . Further, by reducing the width L2 of the n-type source layer 107, integration becomes advantageous.

(Twenty-fifth Embodiment) FIG. 41 is a plan view of an insulated gate turn-off thyristor according to a twenty-fifth embodiment of the present invention. 42 and 43 are sectional views taken along the lines AA 'and BB' of FIG. 418, respectively.

The insulated gate turn-off thyristor of this embodiment is different from that of the 24th embodiment in that
In the above embodiment, the MOSFET is formed in a region which is not used as the MOSFET, and the channel width of the MOSFET is made sufficiently large. Therefore, according to this embodiment, the resistance of the hole current bypass path is further reduced, and a higher turn-off capability is obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type. .

Besides, various modifications can be made without departing from the scope of the present invention.

[0240]

As described above in detail, the present invention (Claim 1)
According to this, the resistance of the bypass path of the first polarity carrier at the time of turn-off can be reduced, and further, the injection of the second polarity carrier from the first conductivity type emitter layer at the time of turn-off can be suppressed, so that the turn-off characteristic can be greatly improved. Like

Further, according to the present invention (claim 2), since the second polar carrier can be discharged through the second conductive type base layer on which the first conductive type emitter layer does not exist, the second polar carrier and the second polar carrier can be discharged. The voltage drop with the second conductivity type base layer becomes equal to or higher than the built-in voltage between the first conductivity type emitter layer and the second conductivity type base layer, and the injection of the second polarity carrier from the first conductivity type emitter layer is stopped. Since the problem of disappearance does not occur, the turn-off characteristic can be improved.

Further, according to the present invention (claim 3), since the thyristor section and the current control section for controlling the current (main current) flowing through the thyristor section are formed on different wafers, the turn-off characteristic is improved. And turn-on characteristics can be improved.

According to the present invention (claims 4 and 5),
Since the resistance of the bypass path of the first polarity carrier at the time of turn-off can be reduced, the turn-off characteristic can be greatly improved.

Further, according to the present invention (claim 6), since the turn-on MOSFET is turned on to pass the current of the second polarity carrier at the time of turn-off, the conduction region of the current of the second polarity carrier is reduced. The current concentration phenomenon of the second polarity carriers can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a first embodiment of the present invention.

FIG. 2 is a time chart showing a gate driving method of the insulated gate turn-off thyristor of FIG.

3 is a time chart showing another gate driving method of the insulated gate turn-off thyristor of FIG.

4 is an equivalent circuit diagram of the insulated gate turn-off thyristor of FIG.

FIG. 5 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a second embodiment of the present invention.

FIG. 6 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a third embodiment of the present invention.

FIG. 7 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a seventh embodiment of the present invention.

FIG. 11 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to an eighth embodiment of the present invention.

FIG. 12 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a ninth embodiment of the present invention.

FIG. 13 is a time chart showing a gate driving method of the insulated gate turn-off thyristor of FIGS. 11 and 12.

FIG. 14 is an equivalent circuit of the insulated gate turn-off thyristor of FIGS. 11 and 12.

FIG. 15 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a tenth embodiment of the present invention.

FIG. 16 is a sectional view showing an element structure of an insulated gate type turn-off thyristor according to an eleventh embodiment of the present invention.

FIG. 17 is a plan view showing an element structure of an insulated gate turn-off thyristor according to a twelfth embodiment of the present invention.

FIG. 18 is a sectional view of the insulated gate turn-off thyristor of FIG. 17, taken along the line AA ′.

19 is a cross-sectional view of the insulated gate turn-off thyristor of FIG. 17, taken along the line BB ′.

FIG. 20 is a plan view showing an element structure of an insulated gate type turn-off thyristor according to a thirteenth embodiment of the present invention.

21 is a cross-sectional view taken along line CC ′ of the insulated gate turn-off thyristor of FIG.

FIG. 22 is a plan view showing an element structure of an insulated gate turn-off thyristor according to a fourteenth embodiment of the present invention.

FIG. 23 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a fifteenth embodiment of the present invention.

FIG. 24 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a sixteenth embodiment of the present invention.

FIG. 25 is a sectional view showing the structure of an insulated gate power semiconductor element according to the seventeenth embodiment of the present invention.

FIG. 26 is a plan view of a first wafer and a second wafer.

FIG. 27 is a sectional view showing the structure of an insulated gate power semiconductor element according to the eighteenth embodiment of the present invention.

FIG. 28 is a cross-sectional view showing the main structure of an insulated gate power semiconductor element according to a nineteenth embodiment of the present invention.

FIG. 29 is a process sectional view showing the method of forming the second wafer according to the twentieth embodiment of the present invention.

FIG. 30 is a process sectional view showing the method of forming the second wafer according to the twenty first embodiment of the present invention.

FIG. 31 is a process sectional view showing the method of forming the second wafer according to the twenty-second embodiment of the present invention.

FIG. 32 is a sectional view showing an element structure of a conventional insulated gate turn-off thyristor.

FIG. 33 is a sectional view showing an element structure of another conventional insulated gate turn-off thyristor.

FIG. 34 is a sectional view showing an element structure of another conventional insulated gate turn-off thyristor.

FIG. 35 is a sectional view showing an element structure of an insulated gate turn-off thyristor according to a 23rd embodiment of the present invention.

FIG. 36 is a time chart showing a gate driving method of the insulated gate type turn-off thyristor.

FIG. 37 is an equivalent circuit diagram of an insulated gate type turn-off thyristor.

FIG. 38 is a plan view of an insulated gate type turn-off thyristor according to a twenty-fourth embodiment of the present invention.

39 is a cross-sectional view of the insulated gate turn-off thyristor of FIG. 38 taken along the line AA ′.

40 is a cross-sectional view taken along the line BB ′ of the insulated gate turn-off thyristor of FIG. 38.

FIG. 41 is a plan view of an insulated gate type turn-off thyristor according to a twenty-fifth embodiment of the present invention.

42 is a cross-sectional view of the insulated gate turn-off thyristor of FIG. 41 taken along the line AA ′.

43 is a cross-sectional view taken along the line BB ′ of the insulated gate turn-off thyristor of FIG. 41.

[Explanation of symbols]

101 ... N-type base layer (first conductivity type base layer), 102
... first p-type base layer (first second-conductivity-type base layer),
103 ... N-type emitter layer (first conductivity type emitter layer), 1
04 ... p-type emitter layer (second conductivity type emitter layer), 10
5 ... Cathode electrode (second main electrode), 106 ... Anode electrode (first main electrode), 107 ... N-type semiconductor layer (first conductivity type layer), 108 ... Base electrode, 109 ... Gate insulating film, 110 ... turn-off gate electrode, 111 ... gate insulating film, 112 ... turn-on gate electrode, 113 ... second p-type base layer (second second-conductivity-type base layer), 11
4 ... N-type drain layer (first conductivity type drain layer), 115
... drain electrode, 116 ... n-type source layer (first conductivity type source layer), 117 ... source electrode 203 ... n-type base layer (first conductivity type base layer), 204
... p-type base layer (second conductivity type base layer), 206 ... p-type emitter layer (second conductivity type emitter layer), 207 ... n-type emitter layer (first conductivity type emitter layer), 210 ... anode electrode (first 1 main electrode), 211 ... Cathode electrode (second main electrode), 213 ... Base electrode, 214 ... Turn-on gate electrode, 216 ... Gate insulating film, 217 ... Turn-on gate electrode, 218 ... Contact hole, 218 '...
Contact hole, 219 ... P-type well layer 300 ... Cathode electrode (second main electrode), 301 ... P-type separation layer, 302 ... N-type drain layer (first conductivity type drain layer), 303 ... N-type cathode layer ( 1st conductivity type cathode layer), 304 ... p type well layer, 305 ... p type anode layer (second conductivity type anode layer), 306 ... n type semiconductor layer, 3
07 ... n-type source layer (first conductivity type source layer), 308 ...
Gate electrode, 309 ... Gate insulating film, 310 ... Cathode connection electrode, 311 ... Drain electrode, 312 ... Base connection electrode, 313 ... P-type emitter layer (second conductivity type emitter layer), 314 ... N-type base layer (first Conductive type base layer),
315 ... P-type base layer (second conductivity type base layer), 316
... n-type emitter layer (first conductivity type base layer), 317 ... gate electrode, 318 ... anode electrode (first main electrode), 3
19 ... Base electrode, 320 ... Emitter electrode 401 ... N-type base layer (first conductivity type base layer), 402
... P-type base layer (second conductivity type base layer), 403a, 4
03b ... n type emitter layer (first conductivity type emitter layer), 4
05a, 405b ... Cathode electrode (second main electrode), 4
06 ... Anode electrode (first main electrode), 407a, 40
7b ... n type source layer (first conductivity type source layer), 408
a, 408 ... Base electrode, 409 ... Gate insulating film, 41
0 ... First turn-on gate electrode, 411 ... Gate insulating film, 412 ... Second turn-on gate electrode, 413
a, 413b ... Base electrode, 414 ... N-type drain layer (first conductivity type drain layer), 415 ... Drain electrode, 4
16 ... Gate insulating film, 417 ... Gate electrode for turn-off

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Kazuya Nakayama 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Incorporated Toshiba Research and Development Center

Claims (6)

[Claims] 1. A first-conductivity-type base layer, a second-conductivity-type emitter layer that is in direct or indirect contact with the surface of the first-conductivity-type base layer, and the first-conductivity-type emitter layer opposite to the second-conductivity-type emitter layer. First and second second conductivity type base layers selectively formed on the surface of the first conductivity type base layer, and first conductivity selectively formed on the surface of the first second conductivity type base layer Type emitter layer, a first conductivity type layer formed on the surface of the first second conductivity type base layer away from the first conductivity type emitter layer, and a surface of the second second conductivity type base layer A first conductivity type source layer selectively formed on the first conductivity type source layer, and a first conductivity type drain layer formed on the surface of the second second conductivity type base layer away from the first conductivity type source layer. The second second conductivity type layer between the first conductivity type drain layer and the first conductivity type source layer. A turn-off gate electrode provided on the base layer via a gate insulating film, and on the first second conductivity type base layer between the first conductivity type base layer and the first conductivity type layer. A turn-on gate electrode provided via a gate insulating film, a first main electrode provided on the second conductivity type emitter layer, and a second main electrode provided on the first conductivity type emitter layer. A base electrode provided on the first second-conductivity-type base layer and the first-conductivity-type layer, and provided on the first-conductivity-type source layer and electrically connected to the second main electrode. An insulated gate power semiconductor device comprising a source electrode and a drain electrode provided in the first conductivity type drain layer and electrically connected to the base electrode. 2. A first-conductivity-type base layer, a second-conductivity-type emitter layer that is in direct or indirect contact with the surface of the first-conductivity-type base layer, and the first-conductivity-type emitter layer opposite to the second-conductivity-type emitter layer. A second conductivity type base layer selectively formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, and the second conductivity type A first conductivity type source layer formed on the surface of the type base layer away from the first conductivity type emitter layer, and a second conductivity type away from the first conductivity type source layer and the first conductivity type emitter layer. A first conductivity type drain layer formed on the surface of the base layer, and a gate insulation film on the second conductivity type base layer between the first conductivity type drain layer and the first conductivity type source layer. A turn-off gate electrode provided, and the first conductivity type A turn-on gate electrode provided on the second conductive type base layer between the base layer and the first conductive type emitter layer via a gate insulating film; and a turn-on gate electrode provided on the second conductive type emitter layer. No. 1 main electrode, a second main electrode provided on the first conductivity type emitter layer, and a source electrode provided on the first conductivity type source layer and electrically connected to the second main electrode. And a base electrode provided on the first conductivity type drain layer and the second conductivity type base layer, the first conductivity type emitter layer on the turn-on gate electrode side and the first conductivity type. An insulated gate power semiconductor device, wherein a part of the second conductive type base layer between the base layer and the base layer is recessed toward the first conductive type emitter layer side. 3. A first wafer having a thyristor portion provided with a first main electrode, and a second main electrode formed integrally with the first wafer and provided with a thyristor portion. Second having a current controller for controlling the current flowing through
An insulated gate power semiconductor device comprising: a second conductive type emitter layer provided with the first main electrode; and a second conductive type emitter layer. A first conductivity type base layer selectively formed on the surface, a second conductivity type base layer selectively formed on the surface of the first conductivity type base layer, and a surface of the second conductivity type base layer And a first insulated gate structure that selectively short-circuits the first conductivity type emitter layer and the first conductivity type base layer, the current control unit Is a first conductivity type drain layer connected to the first conductivity type emitter layer, a first conductivity type source layer connected to the second main electrode, the first conductivity type source layer and the first conductivity type. A second insulated gate structure for selectively shorting the drain layer And an insulated gate FET formed of the same, a first conductivity type cathode layer separated from the first conductivity type drain layer and connected to the second conductivity type base layer, and formed in contact with the first conductivity type cathode layer. And a zener diode composed of a second conductivity type anode layer connected to the second main electrode, and an insulated gate power semiconductor device. 4. A first-conductivity-type base layer, a second-conductivity-type emitter layer that is in direct or indirect contact with the surface of the first-conductivity-type base layer, and the first-conductivity-type emitter layer opposite to the second-conductivity-type emitter layer. A second conductivity type base layer selectively formed on the surface of the first conductivity type base layer, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, and the second conductivity type A first conductivity type source layer formed on the surface of the type base layer away from the first conductivity type emitter layer, and a second conductivity type away from the first conductivity type source layer and the first conductivity type emitter layer. A first conductivity type drain layer formed on the surface of the base layer, and a gate insulation film on the second conductivity type base layer between the first conductivity type drain layer and the first conductivity type emitter layer. A disposed turn-off gate electrode, and the first conductive material A first turn-on gate electrode provided on the second conductive type base between the positive type base layer and the first conductive type source layer via a gate insulating film, and the first conductive type source layer. A second turn-on gate which is formed on the second-conductivity-type base layer between the first-conductivity-type emitter layer and a gate insulating film, and is electrically connected to the first turn-on gate electrode. An electrode, a first main electrode formed on the second conductivity type emitter layer, a second main electrode formed on the first conductivity type emitter layer, and a surface of the second conductivity type base layer A base electrode formed in a position close to the first conductivity type source layer and the first conductivity type emitter layer; and a base electrode provided on the first conductivity type drain layer and the second conductivity type base layer and electrically connected to the base electrode. With the drain electrode electrically connected Insulated gate power semiconductor device characterized by comprising comprises. 5. The insulated gate power semiconductor device according to claim 4, wherein the width of the second conductive type source layer is less than or equal to the width of the second conductive type emitter layer. 6. The method for driving an insulated gate type power semiconductor device according to claim 4, wherein the first turn-on gate electrode, the second turn-on gate electrode and the turn-off gate electrode are respectively formed. A first turn-on MO formed by the first turn-on gate electrode is applied with a predetermined voltage.
The SFET is turned on, the second turn-on MOSFET formed by the second turn-on gate electrode is turned on, and the turn-off MOSFET formed by the turn-off gate electrode is turned off. A thyristor including a conductive type emitter layer, the second conductive type base layer, the first conductive type base layer and the second conductive type emitter layer was turned on, and the first and second turn-on MOSFETs were turned on. In this state, a predetermined voltage is applied to the turn-off gate electrode to turn on the turn-off MOSFET, and after this state, a predetermined voltage is applied to each of the first and second turn-on gate electrodes. The thyristor by turning off the turn-on MOSFET. A method for driving an insulated gate power semiconductor device, which is characterized by turning off.