JPH04261090A - Printed-wiring board and packaging structure for semiconductor element - Google Patents

Printed-wiring board and packaging structure for semiconductor element

Info

Publication number
JPH04261090A
JPH04261090A JP3016370A JP1637091A JPH04261090A JP H04261090 A JPH04261090 A JP H04261090A JP 3016370 A JP3016370 A JP 3016370A JP 1637091 A JP1637091 A JP 1637091A JP H04261090 A JPH04261090 A JP H04261090A
Authority
JP
Japan
Prior art keywords
semiconductor element
conductor
wiring board
substrate
foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3016370A
Other languages
Japanese (ja)
Inventor
Shigenari Takami
茂成 高見
Mitsuhiro Kani
充弘 可児
Yoshimasa Himura
檜村　芳正
Takeshi Kano
武司 加納
Toru Higuchi
徹 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP3016370A priority Critical patent/JPH04261090A/en
Publication of JPH04261090A publication Critical patent/JPH04261090A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Abstract

PURPOSE:To make possible a bonding of Cu wires on a printed-wiring board, on which a semiconductor element can be directly mounted. CONSTITUTION:An Ni foil 12 is bonded on a substrate 11 as a conductor, a through hole Cu plating 4 for making an electrical continuity between the side of the substrate surface and the side of the substrate rear is applied to the foil 12 and the substrate 11 is formed into a board for bonding use. The board is used, a semiconductor element 17 is die bonded on the board and the element 17 is wire bonded on the conductor on the substrate 11 using Cu wires 19. Even if the board is softened by heating during the bonding of the Cu wires, the hardness of the foil 12 acts, the hardness of the conductor can be kept and the bonding of the Cu wires becomes possible.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は、半導体素子を直接実装
できるプリント配線基板及びその基板を用いた半導体素
子の実装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board on which semiconductor elements can be directly mounted, and a structure for mounting semiconductor elements using the printed wiring board.

【０００２】0002

【従来の技術】半導体素子を直接実装する従来のプリン
ト配線基板、例えば、金（Ａｕ）ワイヤボンディング用
ＣＯＢ（ｃｈｉｐ　ｏｎ　ｂｏａｒｄ）は、図３に示す
ように、基材１上に導体として銅（Ｃｕ）箔２が設けら
れ、Ｃｕ箔２の上に基板表面側と裏面側の導通をとるた
めのスルーホール３にメッキ（通常はＣｕメッキ）４が
施され、さらにその上にＮｉメッキ５、Ａｕメッキ６が
施されている。 この配線基板上に、図４に示すように、半導体素子７を
接着剤（Ａｇペースト等）８によりダイボンディングし
、さらに基板導体との電気的接続を金（Ａｕ）線９を用
いてワイヤボンディングにより行う。2. Description of the Related Art A conventional printed wiring board on which a semiconductor element is directly mounted, such as a COB (chip on board) for gold (Au) wire bonding, has copper (copper) as a conductor on a base material 1, as shown in FIG. A Cu) foil 2 is provided, and plating (usually Cu plating) 4 is applied to the through hole 3 for establishing conduction between the front side and the back side of the board on the Cu foil 2, and furthermore, Ni plating 5, Au plating 6 is applied. On this wiring board, as shown in FIG. 4, a semiconductor element 7 is die-bonded using an adhesive (Ag paste, etc.) 8, and electrical connection to the board conductor is made by wire bonding using a gold (Au) wire 9. This is done by

【０００３】一方、Ｃｕワイヤボンディングを行う場合
、理論的には、上記Ａｕワイヤボンディング用基板のよ
うに、導体にメッキ処理を施す必要はなく、Ｃｕ箔２に
直接Ｃｕワイヤボンディングが可能であるため、コスト
ダウンが図れるメリットがある。On the other hand, when performing Cu wire bonding, it is theoretically possible to perform Cu wire bonding directly to the Cu foil 2 without plating the conductor as in the case of the above-mentioned Au wire bonding substrate. , which has the advantage of reducing costs.

【０００４】0004

【発明が解決しようとする課題】しかしながら、Ｃｕ箔
２に直接ワイヤボンディングした場合、通常の基材１で
は、ボンディング中の加熱により軟化し、Ｃｕ箔２上の
見かけの硬度も低下してしまい、ボンディング中にキャ
ピラリーが沈み込み、ボンディングが不可能となる。[Problems to be Solved by the Invention] However, when wire bonding is performed directly to the Cu foil 2, the normal base material 1 is softened by heating during bonding, and the apparent hardness on the Cu foil 2 is also reduced. The capillary sinks during bonding, making bonding impossible.

【０００５】本発明は、上記問題点に鑑みなされたもの
で、その目的とするところは、導体上の見かけ上の硬度
を上げ、Ｃｕワイヤボンディングが可能なプリント配線
基板及びその基板を用いた半導体素子の実装構造を提供
することにある。The present invention was made in view of the above-mentioned problems, and its purpose is to improve the apparent hardness of the conductor and to provide a printed wiring board that can be bonded with Cu wire, and a semiconductor using the board. The object of the present invention is to provide a mounting structure for an element.

【０００６】[0006]

【課題を解決するための手段】上記課題を解決するため
本発明は、基材上に形成した導体に半導体素子を直接実
装するプリント配線基板において、前記導体をニッケル
（Ｎｉ）箔で形成するとともに、ニッケル箔上に銅（Ｃ
ｕ）メッキを施したことを特徴とするものであり、また
、このプリント配線基板に半導体素子をダイボンディン
グし、基板導体との電気的接続を銅（Ｃｕ）ワイヤボン
ディングにより行ったことを特徴とするものである。[Means for Solving the Problems] In order to solve the above problems, the present invention provides a printed wiring board in which a semiconductor element is directly mounted on a conductor formed on a base material, in which the conductor is formed of nickel (Ni) foil, and , copper (C) on nickel foil
u) It is characterized in that it has been plated, and it is also characterized in that the semiconductor element is die-bonded to this printed wiring board, and the electrical connection with the board conductor is made by copper (Cu) wire bonding. It is something to do.

【０００７】[0007]

【作用】本発明によれば、Ｃｕワイヤボンディング中の
加熱により、たとえ基板が軟化したとしても、Ｎｉ箔の
硬度が作用して導体の硬度を保つことができ、Ｃｕワイ
ヤボンディングが可能となる。According to the present invention, even if the substrate is softened by heating during Cu wire bonding, the hardness of the Ni foil acts to maintain the hardness of the conductor, making Cu wire bonding possible.

【０００８】[0008]

【実施例】図１は本発明に係るプリント配線基板の一実
施例を示すもので、その製法は、まず、基材１１上に導
体としてニッケル（Ｎｉ）箔１２を、従来Ｃｕ箔２を基
材１に接着するのと同様に、プリプレグを用いて接着す
る。次に、基板表面側と裏面側の電気的導通をとるため
のスルーホール１３を明ける。これに無電解または電解
のＣｕメッキ１４を施し、スルーホール１３部分の信頼
性を向上させる。その後、必要に応じてパターンのエッ
チングを行い、ボンディング用基板が完成する。[Embodiment] Fig. 1 shows an embodiment of the printed wiring board according to the present invention.The manufacturing method is as follows: First, a nickel (Ni) foil 12 is placed as a conductor on a base material 11, and a conventional Cu foil 2 is used as a conductor. In the same way as material 1, prepreg is used for adhesion. Next, a through hole 13 is made to establish electrical continuity between the front side and the back side of the substrate. Electroless or electrolytic Cu plating 14 is applied to this to improve the reliability of the through hole 13 portion. Thereafter, a pattern is etched as necessary, and a bonding substrate is completed.

【０００９】その基板上に半導体素子１７を、図２に示
すように、Ａｇペースト等の接着剤１８によりダイボン
ディングし、半導体素子１７と基板導体とをＣｕワイヤ
１９を用いてワイヤボンディングにより電気的接続を行
う。As shown in FIG. 2, the semiconductor element 17 is die-bonded onto the substrate using an adhesive 18 such as Ag paste, and the semiconductor element 17 and the substrate conductor are electrically connected by wire bonding using a Cu wire 19. Make the connection.

【００１０】このように構成することにより、Ｃｕワイ
ヤボンディング中の加熱により、たとえ基板が軟化した
としても、Ｎｉ箔１２の硬度が作用して導体の硬度を保
つことができ、Ｃｕワイヤボンディングが可能となる。With this configuration, even if the substrate is softened by heating during Cu wire bonding, the hardness of the Ni foil 12 acts to maintain the hardness of the conductor, making Cu wire bonding possible. becomes.

【００１１】[0011]

【発明の効果】本発明によれば、下記のような効果を奏
する。[Effects of the Invention] According to the present invention, the following effects can be achieved.

【００１２】■　　Ｃｕワイヤボンディングが可能であ
るため、コストダウンが図れる。■　　貴金属（例えば
Ａｕ）メッキが不要であるためコストダウンが図れる。[0012] Since Cu wire bonding is possible, costs can be reduced. ■ Cost reduction can be achieved because precious metal (eg Au) plating is not required.

【００１３】■　　パターンのエッチング後に電解メッ
キする工程が無いため、メッキ用リードが不要となり、
パターンの高密度化が図れる。■ Since there is no electrolytic plating process after pattern etching, plating leads are not required.
Pattern density can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明に係るプリント配線基板の一実施例を示
す断面図である。FIG. 1 is a sectional view showing an embodiment of a printed wiring board according to the present invention.

【図２】本発明に係る半導体素子の実装構造の一実施例
を示す断面図である。FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor element mounting structure according to the present invention.

【図３】従来例に係るプリント配線基板の一例を示す断
面図である。FIG. 3 is a sectional view showing an example of a conventional printed wiring board.

【図４】従来例に係る半導体素子の実装構造の一例を示
す断面図である。FIG. 4 is a cross-sectional view showing an example of a conventional semiconductor element mounting structure.

【符号の説明】[Explanation of symbols]

１１　　基材 １２　　ニッケル（Ｎｉ）箔 １３　　スルーホール １４　　銅（Ｃｕ）メッキ １７　　半導体素子 １８　　接着剤 １９　　銅（Ｃｕ）ワイヤ 11 Base material 12 Nickel (Ni) foil 13 Through hole 14 Copper (Cu) plating 17 Semiconductor element 18 Adhesive 19 Copper (Cu) wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】　　基材上に形成した導体に半導体素子を
直接実装するプリント配線基板において、前記導体をニ
ッケル箔で形成するとともに、ニッケル箔上に銅メッキ
を施したことを特徴とするプリント配線基板。1. A printed wiring board in which a semiconductor element is directly mounted on a conductor formed on a base material, characterized in that the conductor is formed of nickel foil, and the nickel foil is plated with copper. substrate. 【請求項２】　　請求項１記載のプリント配線基板に半
導体素子をダイボンディングするとともに、基板導体と
の電気的接続を銅ワイヤボンディングにより行ったこと
を特徴とする半導体素子の実装構造。2. A mounting structure for a semiconductor element, characterized in that the semiconductor element is die-bonded to the printed wiring board according to claim 1, and electrical connection to the board conductor is made by copper wire bonding.
JP3016370A 1991-02-07 1991-02-07 Printed-wiring board and packaging structure for semiconductor element Pending JPH04261090A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3016370A JPH04261090A (en) 1991-02-07 1991-02-07 Printed-wiring board and packaging structure for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3016370A JPH04261090A (en) 1991-02-07 1991-02-07 Printed-wiring board and packaging structure for semiconductor element

Publications (1)

Publication Number Publication Date
JPH04261090A true JPH04261090A (en) 1992-09-17

Family

ID=11914420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3016370A Pending JPH04261090A (en) 1991-02-07 1991-02-07 Printed-wiring board and packaging structure for semiconductor element

Country Status (1)

Country Link
JP (1) JPH04261090A (en)

Similar Documents

Publication Publication Date Title
US6291271B1 (en) Method of making semiconductor chip package
JPS62158338A (en) Semiconductor device
JP3937993B2 (en) Wiring board manufacturing method
US6348416B1 (en) Carrier substrate for producing semiconductor device
US5531860A (en) Structure and method for providing a lead frame with enhanced solder wetting leads
JPH09129779A (en) Semiconductor package with a hyperfine conduction electrode
JPH0232558A (en) Resin-sealed multi-chip hybrid integrated circuit
JPH04261090A (en) Printed-wiring board and packaging structure for semiconductor element
JP2798108B2 (en) Hybrid integrated circuit device
JP3051570B2 (en) Lead frame and semiconductor device
JP2784248B2 (en) Method for manufacturing semiconductor device
JPH10340925A (en) Semiconductor device and manufacture thereof
JPH02121359A (en) Electronic component mounting substrate
JP3810155B2 (en) Wire bonding method
JP2830221B2 (en) Mounting structure of hybrid integrated circuit
JP3006523B2 (en) Laminated circuit board
JP2784209B2 (en) Semiconductor device
JP2865166B1 (en) Resin-sealed electronic components
JP3095857B2 (en) Substrate for mounting electronic components
JP2001291800A (en) Package for electronic component
JP2782374B2 (en) Electronic component mounting apparatus and manufacturing method thereof
JP2942401B2 (en) Jig for plating
JPH10189846A (en) Heat slug for semiconductor device and semiconductor device
JP2819321B2 (en) Electronic component mounting substrate and method of manufacturing the electronic component mounting substrate
JP2000200848A (en) Electronic component mounting circuit board and semiconductor device