JP2000200848A - Electronic component mounting circuit board and semiconductor device - Google Patents

Electronic component mounting circuit board and semiconductor device

Info

Publication number
JP2000200848A
JP2000200848A JP11000773A JP77399A JP2000200848A JP 2000200848 A JP2000200848 A JP 2000200848A JP 11000773 A JP11000773 A JP 11000773A JP 77399 A JP77399 A JP 77399A JP 2000200848 A JP2000200848 A JP 2000200848A
Authority
JP
Japan
Prior art keywords
substrate
mounting
electronic component
circuit board
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11000773A
Other languages
Japanese (ja)
Inventor
Shigeji Muramatsu
茂次 村松
Michio Horiuchi
道夫 堀内
Takuya Kazama
拓也 風間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP11000773A priority Critical patent/JP2000200848A/en
Publication of JP2000200848A publication Critical patent/JP2000200848A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15182Fan-in arrangement of the internal vias
    • H01L2924/15184Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a highly reliable mounting structure which effectively relaxes a thermal stress induced when an electronic component such as a semiconductor device or the like is mounted on a mounting board. SOLUTION: An electronic component mounting circuit board is interposed between the surface of a surface-mounting electronic component where connecting terminals are formed and the surface of a mounting board where connecting electrodes are formed so as to electrically connect the connecting terminals of the electronic component to the electrodes of the mounting board, where pads 12a where connection terminals are joined are provided to the one surface of an insulating board 10 corresponding to the two-dimensional arrangement of the electrodes, and pads 12b where connection electrodes are joined, are arranged corresponding to the two-dimensional arrangement of the electrodes. Through holes 14 are bored in the insulation board 10 and provided between the pads 12a formed on its one side and the pads 12b formed on its other side, connecting wires 16 are each connected inside the through-holes 14 between the pads 12a formed on the one surface of the board 10 and the pads 12b formed on the other surface of the board 10, so that the pads 12a and 12b each provided to both the sides of the board 10 are electrically connected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子あるいは
チップサイズパッケージ等の面実装型の電子部品を搭載
する電子部品用実装基板及びこれを用いた半導体装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component mounting board for mounting a surface mount type electronic component such as a semiconductor element or a chip size package, and a semiconductor device using the same.

【0002】[0002]

【従来の技術】フリップチップ型の半導体装置あるいは
チップサイズパッケージ等の面実装型の電子部品を実装
基板に実装した場合の問題として、実装基板と半導体素
子との熱膨張係数が相違することによる熱応力の問題が
ある。すなわち、半導体素子を実装基板に実装した際
に、半導体素子と実装基板との間で生じた熱応力により
半導体素子にクラックが生じたり、実装基板と半導体素
子との接合部が剥離したりするといった問題がある。
2. Description of the Related Art A problem in mounting a surface-mount type electronic component such as a flip-chip type semiconductor device or a chip size package on a mounting board is a problem due to a difference in thermal expansion coefficient between the mounting board and the semiconductor element. There is a stress problem. That is, when a semiconductor element is mounted on a mounting substrate, cracks may occur in the semiconductor element due to thermal stress generated between the semiconductor element and the mounting substrate, or a joint between the mounting substrate and the semiconductor element may peel off. There's a problem.

【0003】このような半導体素子等の電子部品を実装
した際に生じる熱応力の問題を解消する方法としては半
導体素子を搭載するパッケージ側に熱応力を緩和する緩
衝部分を設けて半導体素子に過大な熱応力が作用しない
ようにする方法、半導体素子を実装した後、半導体素子
と実装基板との接合部分にアンダーフィル材を充填して
半導体素子を固定することによって接合部で剥離等が生
じないようにするといった方法がある。また、半導体素
子を搭載するパッケージ側に熱応力を緩和する緩衝部分
を設ける方法としては、エラストマー等の緩衝材によっ
て形成した緩衝層を介して半導体素子を基板に搭載する
方法、半導体素子の電極に接続される接続端子をワイヤ
によって形成し、接続端子に弾性を付与して接続端子が
変形できるようにするといった方法がある。
As a method for solving the problem of thermal stress generated when electronic components such as semiconductor elements are mounted, a buffer portion for relaxing thermal stress is provided on a package side on which the semiconductor element is mounted, so that the semiconductor element becomes excessively large. A method for preventing the thermal stress from acting, after mounting the semiconductor element, filling the joint between the semiconductor element and the mounting board with an underfill material and fixing the semiconductor element does not cause separation at the joint. There is a method to do so. Further, as a method of providing a buffer portion for relaxing thermal stress on a package side on which a semiconductor element is mounted, a method of mounting a semiconductor element on a substrate via a buffer layer formed of a buffer material such as an elastomer, a method of forming an electrode on a semiconductor element, There is a method in which a connection terminal to be connected is formed by a wire, and elasticity is given to the connection terminal so that the connection terminal can be deformed.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、半導体
素子やチップサイズパッケージ等の面実装型の半導体装
置に実装時における熱応力を緩和するための緩衝構造を
設けることは、製造工程が複雑になるという問題があ
る。また、フリップチップタイプの半導体素子を実装す
る場合は、構造上、有効な緩衝構造を設けることができ
ないという問題がある。
However, providing a buffer structure for relaxing thermal stress during mounting on a surface-mount type semiconductor device such as a semiconductor element or a chip size package requires a complicated manufacturing process. There's a problem. Further, when a flip-chip type semiconductor element is mounted, there is a problem that an effective buffer structure cannot be provided due to its structure.

【0005】本発明はこれらの課題を解決すべくなされ
たものであり、フリップチップタイプの半導体素子やチ
ップサイズパッケージ等の面実装型の電子部品を実装し
た際に生じる熱応力を効果的に緩和して信頼性の高い実
装構造を可能にする電子部品実装用回路基板及びこれを
用いた半導体装置を提供することを目的とする。
The present invention has been made to solve these problems, and effectively alleviates the thermal stress generated when mounting a surface-mounted electronic component such as a flip-chip type semiconductor device or a chip size package. It is an object of the present invention to provide a circuit board for mounting electronic components and a semiconductor device using the same, which enable a highly reliable mounting structure.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明は次の構成を備える。すなわち、面実装型の
電子部品の接続端子が形成された面と実装基板の接続用
の電極が形成された面との間に介在して、電子部品の接
続端子と実装基板の電極とを電気的に接続する電子部品
実装用回路基板において、電気的絶縁性を有する基板の
一方の面に前記接続端子の平面配列に対応して接続端子
が接合されるパッドが設けられると共に、基板の他方の
面に前記電極の平面配列に対応して電極が接合されるパ
ッドが設けられ、前記一方の面に設けられた各パッドと
他方の面に設けられた各パッドとの間に、基板の両面間
を貫通する貫通孔が形成され、該貫通孔内で基板の一方
の面に設けられたパッドと他方の面に設けられたパッド
との間に接続ワイヤが接続されて基板の両面に設けられ
たパッドが電気的に接続されていることを特徴とする。
また、前記接続ワイヤが、S字形等の変形可能な形状に
形成されていることは、パッドと接続端子との接合部で
効果的な緩衝作用を得る上で有効である。また、前記貫
通孔内に絶縁材料あるいは導電材料からなる緩衝材が充
填されていることを特徴とする。また、前記緩衝材が、
ヤング率10MPa〜10GPa、好ましくは10MP
a〜1GPaの低弾性材料からなることにより、接続端
子等との接合部が好適な緩衝作用を奏することができ
る。
To achieve the above object, the present invention comprises the following arrangement. That is, the connection terminals of the electronic component and the electrodes of the mounting board are interposed between the surface of the surface-mounted electronic component on which the connection terminals are formed and the surface of the mounting board on which the connecting electrodes are formed. In the electronic component mounting circuit board to be electrically connected, a pad to which a connection terminal is joined corresponding to the planar arrangement of the connection terminal is provided on one surface of an electrically insulating substrate, and the other surface of the substrate is provided. A pad to which an electrode is bonded corresponding to the plane arrangement of the electrodes is provided on a surface, and between each pad provided on the one surface and each pad provided on the other surface, between both surfaces of the substrate. A connecting wire is connected between a pad provided on one surface of the substrate and a pad provided on the other surface in the through hole, and provided on both surfaces of the substrate. The pads are electrically connected. .
The fact that the connection wire is formed in a deformable shape such as an S-shape is effective in obtaining an effective buffering action at the joint between the pad and the connection terminal. Further, the through hole is filled with a buffer material made of an insulating material or a conductive material. Further, the cushioning material is
Young's modulus 10 MPa to 10 GPa, preferably 10 MP
By being made of a low elastic material of a to 1 GPa, a joint portion with a connection terminal or the like can exhibit a suitable buffering action.

【0007】また、面実装型の電子部品の接続端子が形
成された面と実装基板の接続用の電極が形成された面と
の間に介在して、電子部品の接続端子と実装基板の電極
とを電気的に接続する電子部品実装用回路基板におい
て、電気的絶縁性を有する基板の一方の面に前記接続端
子の平面配列に対応して接続端子が接合されるパッドが
設けられると共に、基板の他方の面に前記電極の平面配
列に対応して電極が接合されるパッドが設けられ、前記
一方の面に設けられた各パッドと他方の面に設けられた
各パッドとの間に、基板の両面間を貫通する貫通孔が形
成され、該貫通孔内に導電体が充填されて基板の両面に
設けられたパッドが電気的に接続されていることを特徴
とする。また、前記導電体が、緩衝性を有する導電材料
からなることを特徴とする。また、前記基板が、ヤング
率10MPa〜10GPa、好ましくは10MPa〜1
GPaの低弾性材料からなることにより、緩衝性にすぐ
れた電子部品実装用回路基板として得られる。
Also, the connection terminals of the electronic component and the electrodes of the mounting substrate are interposed between the surface of the surface-mount type electronic component on which the connection terminals are formed and the surface of the mounting substrate on which the connection electrodes are formed. And an electronic component mounting circuit board for electrically connecting the connection terminals to one surface of the substrate having electrical insulation, the pad being provided with connection terminals corresponding to the planar arrangement of the connection terminals. A pad to which an electrode is joined corresponding to the planar arrangement of the electrodes is provided on the other surface of the substrate, and a substrate is provided between each pad provided on the one surface and each pad provided on the other surface. A through-hole penetrating between the two surfaces of the substrate is formed, and a conductive material is filled in the through-hole, and pads provided on both surfaces of the substrate are electrically connected. Further, the invention is characterized in that the conductor is made of a conductive material having a buffering property. Further, the substrate has a Young's modulus of 10 MPa to 10 GPa, preferably 10 MPa to 1 GPa.
By using a low elastic material of GPa, it is possible to obtain a circuit board for mounting electronic components having excellent buffering properties.

【0008】また、半導体装置として、前記電子部品実
装用回路基板が、被実装品である電子部品の接続端子が
形成された面と実装基板の電極が形成された面との間に
介在し、前記接続端子が基板の一方の面に設けられたパ
ッドと接合され、前記電極が基板の他方の面に設けられ
たパッドと接合されていることを特徴とする。
Further, as a semiconductor device, the electronic component mounting circuit board is interposed between a surface on which connection terminals of an electronic component to be mounted is formed and a surface of the mounting substrate on which electrodes are formed, The connection terminal is bonded to a pad provided on one surface of the substrate, and the electrode is bonded to a pad provided on the other surface of the substrate.

【0009】[0009]

【発明の実施の形態】以下、本発明の好適な実施形態を
添付図面に基づいて詳細に説明する。図1は本発明に係
る電子部品実装用回路基板の実施形態を示す断面図であ
る。本実施形態の電子部品実装用回路基板は、低弾性材
料によって形成した電気的絶縁性を有する基板10の両
面に、半導体素子等の被実装品の接続端子と実装基板に
設けられた電極の平面配置に対応した配置でパッド12
a、12bを設け、パッド12a、12bに位置合わせ
して基板10を厚さ方向に貫通して設けられた貫通孔1
4内で、基板10の両面に設けたパッ12a、12bの
内面間を接続ワイヤ16によって接続し、緩衝材18に
よって貫通孔14を充填して成るものである。
Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing an embodiment of a circuit board for mounting electronic components according to the present invention. The circuit board for mounting electronic components according to the present embodiment has a structure in which connection terminals of a mounting target such as a semiconductor element and electrodes provided on a mounting board are provided on both surfaces of an electrically insulating board 10 formed of a low elastic material. Pad 12 in an arrangement corresponding to the arrangement
a, 12b are provided, and the through-holes 1 are provided through the substrate 10 in the thickness direction in alignment with the pads 12a, 12b.
In 4, the inner surfaces of the pads 12a and 12b provided on both surfaces of the substrate 10 are connected by connecting wires 16, and the through holes 14 are filled with a buffer material 18.

【0010】電子部品実装用回路基板は半導体素子等の
被実装品と実装基板との間に介在して被実装品と実装基
板との間を電気的に接続するものである。したがって、
基板10の両面に形成するパッド12a、12bは各々
被実装品の接続端子の平面配置と実装基板に設けられた
電極の平面配置と一致する配置となっている必要があ
る。図1に示した実施形態の電子部品実装用回路基板は
半導体素子等の被実装品の接続端子の平面配置と実装基
板に設けられた電極の平面配置がまったく同一の場合の
例であるが、基板10の両面に配置するパッド12a、
12bの平面配置が相互に若干変位していることは可能
である。
[0010] The circuit board for mounting electronic components is interposed between a mounted product such as a semiconductor element and the mounting substrate, and electrically connects the mounted product and the mounting substrate. Therefore,
The pads 12a and 12b formed on both surfaces of the substrate 10 need to be arranged so as to coincide with the plane arrangement of the connection terminals of the mounted product and the plane arrangement of the electrodes provided on the mounting board. The circuit board for mounting electronic components of the embodiment shown in FIG. 1 is an example in the case where the plane arrangement of connection terminals of a mounting object such as a semiconductor element and the plane arrangement of electrodes provided on the mounting board are exactly the same. Pads 12a arranged on both sides of the substrate 10,
It is possible that the plane arrangements of 12b are slightly displaced from each other.

【0011】基板10を低弾性材料によって形成するの
は、電子部品を実装した際に生じる熱応力が好適に緩和
されるようにするためである。このため、基板10には
実装時の熱応力を緩和するに十分な緩衝性を有する材
料、たとえばシリコーン樹脂、シリコーンゴム等の緩衝
性の優れた材料が好適に使用できる。緩衝性を備えた基
板10としては、ヤング率10MPa〜10GPa程度
の材料が好適に使用でき、より好ましくはヤング率10
MPa〜1GPa程度の材料が使用できる。
The reason why the substrate 10 is formed of a low-elastic material is to appropriately reduce the thermal stress generated when electronic components are mounted. For this reason, a material having a sufficient buffering property to alleviate the thermal stress during mounting, for example, a material having an excellent buffering property such as a silicone resin or a silicone rubber can be suitably used for the substrate 10. As the substrate 10 having a buffering property, a material having a Young's modulus of about 10 MPa to 10 GPa can be suitably used.
A material of about MPa to 1 GPa can be used.

【0012】なお、基板10を低弾性材料によって形成
することにより、実装時の熱応力を効果的に緩和するこ
とができるが、本実施形態の電子部品用回路基板では、
基板10を厚さ方向に貫通する貫通孔14を設け、貫通
孔14内で接続ワイヤ16によってパッド12a、12
bを接続するようにしているから、被実装部品の接続端
子と実装基板の電極が接合されるパッド12a、12b
部分でも緩衝作用が奏される。したがって、基板10を
低弾性材料によって形成しない場合であっても一定の緩
衝効果を得ることが可能である。
Although the substrate 10 is made of a low-elastic material, the thermal stress during mounting can be effectively reduced. However, in the circuit board for electronic components of the present embodiment,
A through-hole 14 is provided to penetrate the substrate 10 in the thickness direction, and the pads 12a, 12
b, the pads 12a and 12b to which the connection terminals of the component to be mounted and the electrodes of the mounting board are joined.
A buffering action is also exerted on the part. Therefore, even when the substrate 10 is not formed of a low elastic material, a certain buffering effect can be obtained.

【0013】基板10の両面に設けたパッド12a、1
2bは貫通孔14内でパッド12aとパッド12bの内
面間を接続ワイヤ16によって接続することにより電気
的に接続される。接続ワイヤ16は半導体装置の製造工
程で一般に使われているワイヤボンディング法を利用し
て設けることができる。図示したように、接続ワイヤ1
6をS字形あるいは螺旋形等の柔軟に曲げられる形状に
設ければ、実装時の熱応力によって基板10等が変形し
た場合でも容易に追随できて効果的である。もちろん、
直線形、円弧形等に接続ワイヤ16を設けても所要の作
用を得ることが可能である。
The pads 12a, 1 provided on both sides of the substrate 10
2b is electrically connected by connecting the inner surfaces of the pad 12a and the pad 12b in the through hole 14 by the connection wire 16. The connection wire 16 can be provided by using a wire bonding method generally used in a semiconductor device manufacturing process. As shown, connecting wire 1
If 6 is provided in a shape that can be flexibly bent, such as an S-shape or a spiral shape, even if the substrate 10 or the like is deformed due to thermal stress during mounting, it can be effectively followed. of course,
Even if the connection wires 16 are provided in a linear shape, an arc shape, or the like, the required action can be obtained.

【0014】本実施形態では貫通孔14の内部に緩衝材
18を充填して、貫通孔14の部分でも熱応力を緩和で
きるようにした。緩衝材18は基材10と同一の材料で
あっても異なる材料であってもよい。緩衝材18と基材
10が同一の材料であって、緩衝材18としてペースト
状のものが使用できるような場合には、ペースト状の緩
衝材18を貫通孔14に充填するとよい。ペースト状あ
るいはゼリー状等の緩衝材18による緩衝効果は大きい
からである。また、緩衝材18は電気的絶縁性を有する
ものに限られない。導電性を有する緩衝材18であって
も低弾性材料を使用して所要の緩衝作用を得ることがで
きる。緩衝材18としては、ヤング率10MPa〜10
GPa程度の材料が好適に使用され、より好ましくはヤ
ング率10MPa〜1GPa程度の材料が使用される。
In the present embodiment, the buffer material 18 is filled in the through hole 14 so that the thermal stress can be reduced even in the through hole 14. The buffer material 18 may be the same material as the base material 10 or a different material. If the cushioning material 18 and the base material 10 are the same material and a paste-like material can be used as the cushioning material 18, the paste-like cushioning material 18 may be filled in the through hole 14. This is because the buffering effect of the paste-like or jelly-like buffering material 18 is large. Further, the cushioning member 18 is not limited to a material having electrical insulation. Even if the cushioning material 18 has conductivity, a required cushioning effect can be obtained by using a low elasticity material. The buffer material 18 has a Young's modulus of 10 MPa to 10
A material having about GPa is suitably used, and a material having a Young's modulus of about 10 MPa to 1 GPa is more preferably used.

【0015】このように、半導体素子等の電子部品と実
装基板との間で電気的に接続する部位およびこれらを支
持する基板10を熱応力を効果的に緩和する構成とした
ことにより、半導体素子等の電子部品を実装した際の熱
応力を効果的に緩和することが可能となる。図2は上記
実施形態の電子部品実装用回路基板を使用して半導体素
子20を実装基板30に実装した状態を示す。半導体素
子20の接続端子形成面に形成された接続端子22と基
板10の一方の面に形成したパッド12aとがはんだ2
4により接合され、実装基板30の表面に形成された各
々の電極32と基板10の他方の面に形成したパッド1
2bとがはんだ34により接合されている。
As described above, the parts for electrically connecting electronic parts such as semiconductor elements and the mounting substrate and the substrate 10 supporting them are configured to effectively reduce the thermal stress, so that the semiconductor element It is possible to effectively reduce the thermal stress when electronic components such as are mounted. FIG. 2 shows a state in which the semiconductor element 20 is mounted on a mounting substrate 30 using the circuit board for mounting electronic components of the above embodiment. The connection terminal 22 formed on the connection terminal formation surface of the semiconductor element 20 and the pad 12a formed on one surface of the substrate 10 are solder 2
4, each electrode 32 formed on the surface of the mounting substrate 30 and the pad 1 formed on the other surface of the substrate 10.
2b are joined by solder 34.

【0016】電子部品実装用回路基板は半導体素子20
と実装基板30との中間に介在して半導体素子20の接
続端子22と実装基板30の電極32とを電気的に接続
している。電子部品実装用回路基板は基板10および接
続ワイヤ16、緩衝材18の作用により十分な緩衝性を
有するから、実装基板30と半導体素子20の熱膨張係
数が相違してこれらの間に熱応力が生じる場合であって
も、電子部品実装用回路基板の緩衝作用によって熱応力
が半導体素子20に作用したり、実装基板と半導体素子
20の接合部に作用したりすることを効果的に防止する
ことが可能になる。これによって、きわめて信頼性の高
い実装構造として提供することが可能になる。
The circuit board for mounting electronic parts is a semiconductor element 20.
The connection terminal 22 of the semiconductor element 20 and the electrode 32 of the mounting substrate 30 are electrically connected to each other between the semiconductor device 20 and the mounting substrate 30. Since the circuit board for mounting electronic components has a sufficient buffering property due to the action of the board 10, the connecting wires 16, and the buffer material 18, the thermal expansion coefficients of the mounting board 30 and the semiconductor element 20 are different, and thermal stress is generated between them. Even if it occurs, it is possible to effectively prevent thermal stress from acting on the semiconductor element 20 or acting on a joint between the mounting board and the semiconductor element 20 due to the buffering action of the electronic component mounting circuit board. Becomes possible. This makes it possible to provide a highly reliable mounting structure.

【0017】図3は上述した実施形態の電子部品実装用
回路基板の製造方法を示す。図3(a) はシリコーン樹脂
等の弾性材料をシート状に形成した基材40に銅箔42
を被着した材料である。基材40は電子部品実装用回路
基板の基板10となるものであり、所定の弾性を有する
材料によって形成したものを使用する。銅箔42は電気
的接続用のパッドとなるものである。
FIG. 3 shows a method of manufacturing the circuit board for mounting electronic components according to the above-described embodiment. FIG. 3A shows a copper foil 42 on a substrate 40 formed of an elastic material such as silicone resin in a sheet shape.
Is a material to which is adhered. The substrate 40 is to be the substrate 10 of the electronic component mounting circuit board, and is formed of a material having a predetermined elasticity. The copper foil 42 serves as a pad for electrical connection.

【0018】図3(b) は基材40にレーザ光を照射して
貫通孔14を形成した状態である。貫通孔14は半導体
素子等の実装基板に搭載する電子部品の接続端子の平面
配置に一致させて形成する。上述したように、貫通孔1
4は基板10の両面に設けるパッド12a、12bを接
続ワイヤ16によって接続するために設けるもので、接
続ワイヤ16を形成できる径寸法に形成する。レーザ光
照射によって貫通孔14を設ける場合は銅箔42でレー
ザ光が遮断され、銅箔42を露出させた貫通孔14を容
易に形成することができる。
FIG. 3B shows a state in which the substrate 40 is irradiated with laser light to form the through-holes 14. The through-holes 14 are formed in accordance with the planar arrangement of connection terminals of electronic components mounted on a mounting substrate such as a semiconductor element. As described above, the through hole 1
Numeral 4 is provided to connect the pads 12a and 12b provided on both surfaces of the substrate 10 by the connection wires 16, and is formed to have a diameter dimension that allows the connection wires 16 to be formed. When the through hole 14 is provided by laser light irradiation, the laser light is blocked by the copper foil 42, and the through hole 14 exposing the copper foil 42 can be easily formed.

【0019】図3(c) は各々の貫通孔14内で銅箔42
の内面に接続ワイヤ16の基端をボンディングし、S字
形に湾曲させるようにして引き出し、先端が貫通孔14
の開口面よりも外側に突出した位置で切断した状態であ
る。次に、図3(d) に示すように、貫通孔14に緩衝材
18を充填する。緩衝材18を充填する場合は、基材4
0の表面と緩衝材18の表面が同一平面になるように貫
通孔14の上端面まで充填する。
FIG. 3C shows a copper foil 42 in each through hole 14.
The base end of the connecting wire 16 is bonded to the inner surface of the connecting wire 16 and pulled out so as to be curved in an S-shape.
Is a state where it is cut at a position protruding outward from the opening surface of. Next, as shown in FIG. 3D, the buffer material 18 is filled in the through hole 14. When filling the cushioning material 18, the base material 4
The filling is performed up to the upper end surface of the through-hole 14 so that the surface of the through hole 14 is flush with the surface of the cushioning material 18.

【0020】次に、基材40の上面に無電解銅めっきお
よび電解銅めっきを施し、基材40の表面を銅層44に
よって被覆する。図3(e) が基材40の露出面と緩衝材
18の露出面が銅層44によって被覆された状態を示
す。貫通孔14の開口面よりも接続ワイヤ16の先端が
突出していることにより、接続ワイヤ16と銅層44と
が電気的に接続される。
Next, the upper surface of the substrate 40 is subjected to electroless copper plating and electrolytic copper plating, and the surface of the substrate 40 is covered with a copper layer 44. FIG. 3E shows a state in which the exposed surface of the base material 40 and the exposed surface of the cushioning material 18 are covered with the copper layer 44. Since the tip of the connection wire 16 protrudes from the opening surface of the through hole 14, the connection wire 16 and the copper layer 44 are electrically connected.

【0021】図3(f) は、最後に基材40の下面の銅箔
42と基材40の上面の銅層44をエッチングしてパッ
ド12a、12bを形成した状態である。パッド12
a、12bは実装する電子部品の接続端子の寸法及び実
装基板の電極の寸法に合わせて所定形状に形成すればよ
い。こうして、図1に示した電子部品実装用回路基板が
得られる。この電子部品実装用回路基板のパッド12
a、12bの平面配列は、電子部品の接続端子及び実装
基板の電極の平面配列に合わせてエリアアレイ状にパッ
ド12a、12bが配列されたものである。
FIG. 3F shows a state in which the copper foil 42 on the lower surface of the substrate 40 and the copper layer 44 on the upper surface of the substrate 40 are finally etched to form the pads 12a and 12b. Pad 12
A and 12b may be formed in a predetermined shape according to the dimensions of the connection terminals of the electronic component to be mounted and the dimensions of the electrodes of the mounting board. Thus, the electronic component mounting circuit board shown in FIG. 1 is obtained. Pad 12 of this electronic component mounting circuit board
The plane arrangement of a and 12b is such that pads 12a and 12b are arranged in an area array in accordance with the plane arrangement of the connection terminals of the electronic component and the electrodes of the mounting board.

【0022】図4は電子部品実装用回路基板の他の実施
形態を示す。本実施形態の電子部品実装用回路基板は、
貫通孔14内に導電体50を充填して基板10の両面に
設けたパッド12a、12bを電気的に接続するように
構成したものである。導電体50としては導電性樹脂、
銀ペースト等のペースト体等が使用できる。上記実施形
態と同様に導電体50も緩衝性を有する材料であること
が熱応力を緩和する目的に有効である。なお、基板10
およびパッド12a、12bの構成は上記実施形態と同
様である。本実施形態の電子部品実装用回路基板を製造
する場合は、上記実施形態の製造方法で、貫通孔14を
形成した後、導電体50を充填することによればよい。
他の製造工程は上記実施形態と同様である。
FIG. 4 shows another embodiment of a circuit board for mounting electronic components. The electronic component mounting circuit board of the present embodiment includes:
The conductors 50 are filled in the through holes 14 to electrically connect the pads 12a and 12b provided on both surfaces of the substrate 10. Conductive resin as the conductor 50,
A paste body such as a silver paste can be used. As in the above-described embodiment, it is effective that the conductor 50 is also a material having a buffering property for the purpose of relieving thermal stress. The substrate 10
The configuration of the pads 12a and 12b is the same as in the above embodiment. In the case of manufacturing the electronic component mounting circuit board of the present embodiment, the conductor 50 may be filled after forming the through hole 14 by the manufacturing method of the above embodiment.
Other manufacturing steps are the same as in the above embodiment.

【0023】図5は電子部品実装用回路基板のさらに他
の実施形態を示す。本実施形態の電子部品実装用回路基
板は、基板10の両面のパッド12a、12bを貫通孔
内に導電体として金属柱52を設けて電気的に接続した
ものである。金属柱52を有する電子部品実装用回路基
板を製造する場合は、たとえば、前述した電子部品実装
用回路基板の製造方法で、基材40に貫通孔14を形成
した後、銅箔42をめっき給電層とする電解銅めっきに
より、貫通孔14内に銅を盛り上げて金属柱52を形成
することによる。パッド12a、12bを形成する方法
は上記実施形態と同様である。
FIG. 5 shows still another embodiment of the circuit board for mounting electronic components. In the electronic component mounting circuit board of the present embodiment, the pads 12a and 12b on both surfaces of the board 10 are electrically connected by providing metal pillars 52 as conductors in the through holes. In the case of manufacturing an electronic component mounting circuit board having the metal columns 52, for example, the through-holes 14 are formed in the base material 40 and then the copper foil 42 is plated and supplied by the above-described method for manufacturing an electronic component mounting circuit board. The metal pillar 52 is formed by raising copper in the through hole 14 by electrolytic copper plating as a layer. The method of forming the pads 12a and 12b is the same as in the above embodiment.

【0024】図6は電子部品実装用回路基板を多層に形
成する製造方法の例を示す。図6(a) は前述した製造方
法と同じ方法によって基材40の両面にパッド12a、
12bを設けた第1層目の回路基板を形成した状態であ
る。電子部品実装用回路基板を多層に形成する場合は第
1層目の基材40の表面に基材40と同様な電気的絶縁
性を有する弾性材料からなる基材40aを積層し、前述
した実施形態と同様に基材40aにレーザ光を照射し、
第1層目の回路基板に設けたパッド12aとの接続位置
に合わせて貫通孔14を形成する(図6(b))。基材40
aはシート状のものを接着する方法あるいは均等な厚さ
に弾性材料を塗布する方法等によって形成することがで
きる。
FIG. 6 shows an example of a manufacturing method for forming a circuit board for mounting electronic components in multiple layers. FIG. 6 (a) shows pads 12a on both surfaces of a base material 40 by the same method as the manufacturing method described above.
This is a state in which a first-layer circuit board provided with 12b is formed. When the circuit board for mounting electronic components is formed in multiple layers, a substrate 40a made of an elastic material having the same electrical insulation property as the substrate 40 is laminated on the surface of the substrate 40 of the first layer, and The base material 40a is irradiated with laser light in the same manner as the form,
A through-hole 14 is formed in accordance with the connection position with the pad 12a provided on the first-layer circuit board (FIG. 6B). Substrate 40
a can be formed by a method of bonding a sheet-like material or a method of applying an elastic material to a uniform thickness.

【0025】次に、各々の貫通孔14に接続ワイヤ16
をボンディングし、前述した実施形態と同様にS字形に
湾曲させて接続ワイヤ16を引き出し、先端が貫通孔1
4の開口面よりも外側に突出した位置で切断する(図6
(c))。次に、貫通孔14に緩衝材18を充填し、基材4
0の表面に無電解銅めっき及び電解銅めっきを施して銅
層44を形成する(図6(d))。最後に、銅層44をエッ
チングすることによって、第2層目の基材40aの表面
にパッド12cを形成する(図6(e))。
Next, a connection wire 16 is inserted into each through hole 14.
And connecting wire 16 is drawn out in the same manner as in the above-described embodiment by bending into an S-shape,
6 at a position protruding outside the opening surface of FIG.
(c)). Next, the buffer material 18 is filled in the through holes 14 and the base material 4
The copper layer 44 is formed by performing electroless copper plating and electrolytic copper plating on the surface of No. 0 (FIG. 6D). Finally, the pad 12c is formed on the surface of the second-layer base material 40a by etching the copper layer 44 (FIG. 6E).

【0026】こうして、接続ワイヤ16を介して第1層
目のパッド12a、12bと第2層目のパッド12cと
が電気的に接続された多層構成の電子部品実装用回路基
板が得られる。多層の電子部品実装用回路基板の場合に
は基材40および基材40aを合わせて基板10を構成
すると考えることにより、基板10の両面に半導体素子
等の電子部品の接続端子と実装基板の電極の配置に合わ
せてパッド12c、12bが設けられた電子部品実装用
回路基板として提供される。
In this way, a multilayer circuit board for mounting electronic components, in which the first-layer pads 12a and 12b and the second-layer pads 12c are electrically connected via the connection wires 16, is obtained. In the case of a multilayer electronic component mounting circuit board, it is considered that the substrate 10 is configured by combining the base material 40 and the base material 40a, and thus connection terminals of electronic components such as semiconductor elements and electrodes of the mounting substrate are provided on both surfaces of the substrate 10. Is provided as a circuit board for mounting electronic components provided with pads 12c and 12b in accordance with the arrangement.

【0027】この多層に形成された電子部品実装用回路
基板も前述した電子部品実装用回路基板と同様に、基板
および接続ワイヤ16等のパッド間を電気的に接続する
部位が十分な緩衝性を備えているから、半導体素子と実
装基板との中間に介在して、半導体素子の接続端子と実
装基板の電極とを電気的に接続する回路基板として用い
ることにより、半導体素子と実装基板との熱膨張係数が
相違することによって生じる熱応力を効果的に緩和する
ことができ、信頼性の高い実装構造を提供することが可
能になる。
In the electronic component mounting circuit board formed in multiple layers, similarly to the above-described electronic component mounting circuit board, the portion for electrically connecting the substrate and the pad such as the connection wire 16 has a sufficient buffering property. Since the semiconductor device and the mounting substrate are interposed between the semiconductor device and the mounting substrate and used as a circuit board for electrically connecting the connection terminals of the semiconductor device and the electrodes of the mounting substrate, the heat of the semiconductor device and the mounting substrate can be reduced. The thermal stress generated due to the difference in the expansion coefficient can be effectively reduced, and a highly reliable mounting structure can be provided.

【0028】なお、本実施形態のように電子部品実装用
回路基板を多層に形成する場合は、層間に設けるパッド
12aは電気的接続のための配線パターンとして使用す
ることができる。すなわち、パッド12aは銅層等の導
体層をエッチングして形成するから、導体層をエッチン
グして任意のパターンで配線パターンを形成することが
でき、所要の配線パターンを形成して層間で電気的に接
続させることができる。半導体素子の接続端子がきわめ
て高密度に配置されていて実装基板の電極が半導体素子
の接続端子と同一の平面配置で配列できないような場合
に、電子部品実装用回路基板を多層に形成することによ
って電極の配置間隔を広げるといったことが可能にな
る。このような場合に電子部品実装用回路基板を多層に
形成することが有効である。
When the circuit board for mounting electronic components is formed in multiple layers as in this embodiment, the pads 12a provided between the layers can be used as wiring patterns for electrical connection. That is, since the pad 12a is formed by etching a conductor layer such as a copper layer, the conductor layer can be etched to form a wiring pattern in an arbitrary pattern. Can be connected. In the case where the connection terminals of the semiconductor element are arranged at a very high density and the electrodes of the mounting board cannot be arranged in the same plane arrangement as the connection terminals of the semiconductor element, the circuit board for mounting electronic components is formed in multiple layers. It is possible to widen the arrangement interval of the electrodes. In such a case, it is effective to form the electronic component mounting circuit board in multiple layers.

【0029】[0029]

【発明の効果】本発明に係る電子部品実装用回路基板に
よれば、上述したように、半導体素子等の電子部品を実
装基板に実装した際の熱応力を有効に緩和することがで
き、実装時の熱応力が電子部品に及ぼす悪影響や電子部
品と実装基板との接合部に及ぼす悪影響を解消すること
ができて、信頼性の高い電子部品の実装を可能にする。
また、本発明に係る電子部品実装用回路基板を用いれば
フリップチップタイプの半導体素子についても熱応力を
好適に緩和して実装することが可能になる。また、本発
明に係る半導体装置によれば、被実装品である電子部品
および実装基板との接合部に作用する実装時での熱応力
が電子部品実装用回路基板によって効果的に緩和され、
信頼性の高い半導体装置として提供することができる。
According to the circuit board for mounting electronic components according to the present invention, as described above, the thermal stress when electronic components such as semiconductor elements are mounted on the mounting board can be effectively alleviated. The adverse effect of thermal stress on the electronic component and the adverse effect on the joint between the electronic component and the mounting board can be eliminated, thereby enabling highly reliable mounting of the electronic component.
Further, the use of the circuit board for mounting electronic components according to the present invention makes it possible to mount flip-chip type semiconductor elements by suitably reducing thermal stress. Further, according to the semiconductor device of the present invention, the thermal stress at the time of mounting, which acts on the junction between the electronic component to be mounted and the mounting board, is effectively reduced by the electronic component mounting circuit board,
The semiconductor device can be provided as a highly reliable semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】電子部品実装用回路基板の実施形態を示す断面
図である。
FIG. 1 is a cross-sectional view illustrating an embodiment of a circuit board for mounting electronic components.

【図2】電子部品実装用回路基板を用いて実装基板に半
導体素子を搭載した状態を示す断面図である。
FIG. 2 is a cross-sectional view showing a state where a semiconductor element is mounted on a mounting board using an electronic component mounting circuit board.

【図3】電子部品実装用回路基板の製造方法を示す説明
図である。
FIG. 3 is an explanatory view illustrating a method of manufacturing a circuit board for mounting electronic components.

【図4】電子部品実装用回路基板の他の実施形態を示す
断面図である。
FIG. 4 is a sectional view showing another embodiment of a circuit board for mounting electronic components.

【図5】電子部品実装用回路基板のさらに他の実施形態
を示す断面図である。
FIG. 5 is a sectional view showing still another embodiment of the circuit board for mounting electronic components.

【図6】多層に形成した電子部品実装用回路基板の製造
方法を示す断面図である。
FIG. 6 is a cross-sectional view showing a method of manufacturing a multilayer circuit board for mounting electronic components.

【符号の説明】[Explanation of symbols]

10 基板 12a、12b、12c パッド 14 貫通孔 16 接続ワイヤ 18 緩衝材 20 半導体素子 22 接続端子 24 はんだ 30 実装基板 32 電極 34 はんだ 40、40a 基材 42 銅箔 50 導電体 52 金属柱 DESCRIPTION OF SYMBOLS 10 Substrate 12a, 12b, 12c Pad 14 Through hole 16 Connection wire 18 Buffer material 20 Semiconductor element 22 Connection terminal 24 Solder 30 Mounting substrate 32 Electrode 34 Solder 40, 40a Base material 42 Copper foil 50 Conductor 52 Metal column

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 面実装型の電子部品の接続端子が形成さ
れた面と実装基板の接続用の電極が形成された面との間
に介在して、電子部品の接続端子と実装基板の電極とを
電気的に接続する電子部品実装用回路基板において、 電気的絶縁性を有する基板の一方の面に前記接続端子の
平面配列に対応して接続端子が接合されるパッドが設け
られると共に、基板の他方の面に前記電極の平面配列に
対応して電極が接合されるパッドが設けられ、 前記一方の面に設けられた各パッドと他方の面に設けら
れた各パッドとの間に、基板の両面間を貫通する貫通孔
が形成され、 該貫通孔内で基板の一方の面に設けられたパッドと他方
の面に設けられたパッドとの間に接続ワイヤが接続され
て基板の両面に設けられたパッドが電気的に接続されて
いることを特徴とする電子部品実装用回路基板。
1. A connection terminal of an electronic component and an electrode of a mounting substrate interposed between a surface of the surface mounting type electronic component on which a connection terminal is formed and a surface of the mounting substrate on which a connection electrode is formed. An electronic component mounting circuit board for electrically connecting the connection terminals to one another on a surface of the substrate having electrical insulation, the pads being provided with connection terminals corresponding to the planar arrangement of the connection terminals. A pad to which an electrode is joined corresponding to the planar arrangement of the electrodes is provided on the other surface of the substrate, and a substrate is provided between each pad provided on the one surface and each pad provided on the other surface. A connection wire is connected between a pad provided on one surface of the substrate and a pad provided on the other surface in the through hole, and a connection wire is formed on both surfaces of the substrate. The provided pads are electrically connected Electronic component mounting circuit board.
【請求項2】 接続ワイヤが、S字形等の変形可能な形
状に形成されていることを特徴とする請求項1記載の電
子部品実装用回路基板。
2. The electronic component mounting circuit board according to claim 1, wherein the connection wire is formed in a deformable shape such as an S-shape.
【請求項3】 前記貫通孔内に絶縁材料あるいは導電材
料からなる緩衝材が充填されていることを特徴とする請
求項1または2記載の電子部品実装用回路基板。
3. The circuit board for mounting electronic components according to claim 1, wherein the through hole is filled with a buffer material made of an insulating material or a conductive material.
【請求項4】 前記緩衝材が、ヤング率10MPa〜1
0GPa、好ましくは10MPa〜1GPaの低弾性材
料からなることを特徴とする請求項3記載の電子部品実
装用回路基板。
4. The cushioning material has a Young's modulus of 10 MPa to 1
The electronic component mounting circuit board according to claim 3, wherein the circuit board is made of a low elastic material of 0 GPa, preferably 10 MPa to 1 GPa.
【請求項5】 面実装型の電子部品の接続端子が形成さ
れた面と実装基板の接続用の電極が形成された面との間
に介在して、電子部品の接続端子と実装基板の電極とを
電気的に接続する電子部品実装用回路基板において、 電気的絶縁性を有する基板の一方の面に前記接続端子の
平面配列に対応して接続端子が接合されるパッドが設け
られると共に、基板の他方の面に前記電極の平面配列に
対応して電極が接合されるパッドが設けられ、 前記一方の面に設けられた各パッドと他方の面に設けら
れた各パッドとの間に、基板の両面間を貫通する貫通孔
が形成され、 該貫通孔内に導電体が充填されて基板の両面に設けられ
たパッドが電気的に接続されていることを特徴とする電
子部品実装用回路基板。
5. A connection terminal of an electronic component and an electrode of a mounting substrate interposed between a surface of the surface mounting type electronic component on which a connection terminal is formed and a surface of the mounting substrate on which a connection electrode is formed. An electronic component mounting circuit board for electrically connecting the connection terminals to one another on a surface of the substrate having electrical insulation, the pads being provided with connection terminals corresponding to the planar arrangement of the connection terminals. A pad to which an electrode is joined corresponding to the planar arrangement of the electrodes is provided on the other surface of the substrate, and a substrate is provided between each pad provided on the one surface and each pad provided on the other surface. A through-hole penetrating between both surfaces of the substrate is formed, and a conductor is filled in the through-hole and pads provided on both surfaces of the substrate are electrically connected to each other. .
【請求項6】 前記導電体が、緩衝性を有する導電材料
からなることを特徴とする請求項5記載の電子部品実装
用回路基板。
6. The electronic component mounting circuit board according to claim 5, wherein the conductor is made of a conductive material having a buffering property.
【請求項7】 前記基板が、ヤング率10MPa〜10
GPa、好ましくは10MPa〜1GPaの低弾性材料
からなることを特徴とする請求項1、2、3、4、5ま
たは6記載の電子部品実装用回路基板。
7. The method according to claim 1, wherein the substrate has a Young's modulus of 10 MPa to 10 MPa.
7. The electronic component mounting circuit board according to claim 1, wherein the circuit board is made of a low elastic material of GPa, preferably 10 MPa to 1 GPa.
【請求項8】 請求項1、2、3、4、5、6または7
記載の電子部品実装用回路基板が、被実装品である電子
部品の接続端子が形成された面と実装基板の電極が形成
された面との間に介在し、 前記接続端子が基板の一方の面に設けられたパッドと接
合され、前記電極が基板の他方の面に設けられたパッド
と接合されていることを特徴とする半導体装置。
8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
The electronic component mounting circuit board described above is interposed between the surface on which the connection terminal of the electronic component to be mounted is formed and the surface of the mounting substrate on which the electrode is formed, and the connection terminal is provided on one side of the substrate. A semiconductor device, wherein the electrode is bonded to a pad provided on a surface of the substrate, and the electrode is bonded to a pad provided on the other surface of the substrate.
JP11000773A 1999-01-06 1999-01-06 Electronic component mounting circuit board and semiconductor device Pending JP2000200848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11000773A JP2000200848A (en) 1999-01-06 1999-01-06 Electronic component mounting circuit board and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11000773A JP2000200848A (en) 1999-01-06 1999-01-06 Electronic component mounting circuit board and semiconductor device

Publications (1)

Publication Number Publication Date
JP2000200848A true JP2000200848A (en) 2000-07-18

Family

ID=11483029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11000773A Pending JP2000200848A (en) 1999-01-06 1999-01-06 Electronic component mounting circuit board and semiconductor device

Country Status (1)

Country Link
JP (1) JP2000200848A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005223162A (en) * 2004-02-06 2005-08-18 Sony Corp Chip-shaped electronic component, its manufacturing method, and mounting structure thereof
JP2006080199A (en) * 2004-09-08 2006-03-23 Ibiden Co Ltd Electric relay plate
JP2016005892A (en) * 2014-05-30 2016-01-14 キヤノン株式会社 Liquid ejection cartridge and liquid ejection device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005223162A (en) * 2004-02-06 2005-08-18 Sony Corp Chip-shaped electronic component, its manufacturing method, and mounting structure thereof
JP2006080199A (en) * 2004-09-08 2006-03-23 Ibiden Co Ltd Electric relay plate
JP4599121B2 (en) * 2004-09-08 2010-12-15 イビデン株式会社 Electrical relay plate
JP2016005892A (en) * 2014-05-30 2016-01-14 キヤノン株式会社 Liquid ejection cartridge and liquid ejection device

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