JPH1187402A - Mounting structure and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To disperse the stress developed by the difference in thermal expansion coefficients between sealing resin, wirings and a circuit substrate by a method wherein a substrate terminal is formed on the mounting surface of the region located directly under a semiconductor device, a backside wiring is formed on the backside of the mounting surface and a conductive hole is formed on the circuit substrate located in the region directly under the semiconductor device. SOLUTION: The electrode pad 3 of an IC substrate chip 1 is electronically connected to the input/output terminal electrode 7 to be used as the substrate terminal formed on a two wiring layer substrates 11. A backside wiring layer 9 is formed on the backside of the mounting surface of the wiring layer substrates 11 where an input/output terminal electrode 7 and a surface wiring layer 8 are formed, and the input/output terminal electrode 7 and the surface wiring layer 8 are electrically connected to the backside wiring layer 9 through a conductive via hole 4 as a conductive hole. Accordingly, the malfunction such as breaking of wire, caused by the stress generated by the difference in thermal expansion coefficient of a circuit substrate, sealing resin and wirings, can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a mounting structure in which a semiconductor device such as an integrated circuit chip is mounted on a circuit board by a flip chip method, and a method of manufacturing the same.

[0002]

2. Description of the Related Art At present, mounting structures are used in various electronic devices. Therefore, the improvement of the reliability of the mounting structure
Contributes to improving the reliability of electronic devices.

As a method of mounting a semiconductor device on a circuit board and electrically connecting the same, a wire bonding method has been conventionally used. The wire bonding method means that an electrode formed on a semiconductor device and an input / output terminal electrode formed on a circuit board corresponding to the electrode are soldered through a thin wire made of Au, Al, or the like. It is a thing to connect.

However, in recent years, the pitch of the connection terminals has been narrowed along with the miniaturization of the package of the semiconductor device and the increase in the number of connection terminals. Therefore, a conventional semiconductor device mounting method which requires soldering is used. Things are becoming increasingly difficult.

To address this problem, wireless bonding has been proposed in which a semiconductor device is directly mounted on input / output terminal electrodes formed on a circuit board without using wires.

In a flip chip method, which is one type of wireless bonding, a semiconductor device is mounted on a circuit board in a face-down state in which an electrode of the semiconductor device and an input / output terminal electrode of a circuit board are in contact via bumps. .
The flip-chip method has attracted particular attention because the electrical connection between the semiconductor device and the circuit board can be performed collectively and the connection via the bumps is mechanically strong.

[0007] "IC" edited by Japan Microelectronics, published by the Industrial Research Council on January 15, 1980.
"Mounting technology" discloses a flip-chip mounting method using a solder plating method. The mounting method disclosed in the above document will be described below as a first conventional example with reference to FIG.

FIG. 7A is a schematic cross-sectional view of the IC substrate chip 1 on which the solder bumps 20 are formed, and FIG. 7B is an IC of a mounting structure according to a first conventional example. FIG. 2 is a schematic cross-sectional view of a connection portion between a substrate chip 1 and a circuit board 21.

A method for connecting the IC substrate chip 1 and the circuit board 21 will be described below. First, a diffusion preventing metal film 18 and an adhesion metal film 19 are formed on the electrode pads 3 of the IC substrate chip 1 by a vapor deposition method. Subsequently, solder bumps 20 as electrical connection points made of solder are formed on the two metal films by a plating method. After forming the solder bumps 20,
The IC chip 1 is placed on the circuit board 21 in a face-down state where the electrode pads 3 are in contact with the input / output terminal electrodes 7 formed on the circuit board 21 corresponding to the electrode pads 3 via the solder bumps 20. Subsequently, the circuit board 21 on which the IC chip 1 is mounted is heated at a high temperature to fuse the solder bumps 20. Thus, the electrical connection between the electrode pads 3 of the IC substrate chip 1 and the corresponding input / output terminal electrodes 7 is completed. At the same time, each other electrode pad (not shown) of the IC substrate chip 1 is electrically connected to the corresponding input / output terminal electrode (not shown) of the circuit board 2, so that the flip-chip IC Circuit board 2 of board chip 1
1 is completed, and the mounting structure is completed.

Further, a method has been proposed in which the sealing resin 5 is injected between the IC substrate chip 1 and the circuit board 21 and hardened to strengthen the fixation of the IC substrate chip 1.

Next, a mounting structure according to a second conventional example will be described. FIG. 8 is a schematic cross-sectional view of a mounting structure according to a second conventional example. In the mounting structure according to the second conventional example, the electrode pads 3 of the IC board chip 1 and the corresponding input / output terminal electrodes 7 of the circuit board 21 are formed of Au bumps 22.
And electrically connected via a conductive adhesive 6.

The Au bumps 22 are formed on the electrode pads 3 by a wire bonding method or a plating method. The mounting of the IC board chip 1 on the circuit board 21 is performed after the conductive adhesive 6 is transferred to the Au bump 22.
The IC board chip 1 is opposed to the circuit board 21 so that the Au bumps 22 are in contact with the corresponding input / output terminal electrodes 7. The conductive adhesive 6 is cured so that the IC board chip 1 and the circuit board 21 are hardened. The electrical connection with is completed.

Further, as in the first conventional example, a method is proposed in which the sealing resin 5 is injected between the IC board chip 1 and the circuit board 21 and cured to strengthen the fixation of the IC board chip 1. Have been.

Next, a third conventional example will be described with reference to FIG. FIG. 9 is a schematic cross-sectional view of a mounting structure according to a third conventional example. In the mounting structure according to the third conventional example, the electrode pads 3 of the IC board chip 1
The IC board chip 1 is mounted on a circuit board 21 by a flip chip method in which the input / output terminal electrode 7 and the surface wiring 8 formed on the IC chip 1 are electrically connected via the bumps 2 and the conductive adhesive 6. . Further, a sealing resin 5 is injected between the IC board chip 1 and the circuit board 21 to reinforce the mounting and is cured.

[0015]

However, the above-described mounting structure having a sealing resin between the semiconductor device and the circuit board has the following problems. This problem will be described with reference to FIG.

In the mounting structure shown in FIG.
Covers the surface wiring layer 8 around the IC chip 1.
Since the sealing resin, the wiring, and the circuit board have different coefficients of thermal expansion, stress generated by the difference in coefficient of thermal expansion between the members may cause disconnection of the surface wiring layer 8.
Specifically, the generated stress concentrates on the portion of the surface wiring layer 8 where the wiring width is changed. This adversely affects the reliability of the mounting structure.

As a method for addressing the above-mentioned problem, the filler resin 12, which is an inorganic substance, is contained in the sealing resin to lower the coefficient of thermal expansion of the sealing resin and reduce the difference in the coefficient of thermal expansion between the wiring and the sealing resin. A method of suppressing the stress generated by reducing the size has been put to practical use. In order to further improve the reliability of the mounting structure, a method of dispersing the stress generated in the wiring or a method of arranging the wiring in a region where the stress does not reach can be considered.

An object of the present invention is to provide a highly reliable mounting structure and a method of manufacturing the same.

[0019]

A mounting structure according to the present invention is a mounting structure in which a semiconductor device is flip-chip mounted on a mounting surface of a circuit board, and the mounting surface is located in a region directly below the semiconductor device. And a substrate terminal electrically connected to an electrode of the semiconductor device, a back wiring formed on a back surface of the mounting surface, and the substrate terminal and the back surface formed on the circuit board in the region immediately below the substrate terminal. It is characterized by including a conductive hole for electrically connecting to a wiring.

The mounting structure according to the present invention includes a sealing resin for fixing the semiconductor device on the mounting surface for flip-chip mounting, and a sealing resin on the mounting surface other than a region where the sealing resin is in contact with the mounting surface. It is preferable to include a formed surface wiring and a second conductive hole formed on the circuit board and electrically connecting the surface wiring and the back wiring.

The mounting structure according to the present invention comprises a first surface layer,
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a second surface layer and a bonding layer for bonding the first surface layer and the second surface layer, wherein the semiconductor device is mounted. A substrate terminal formed in a region directly below the semiconductor device on the surface layer and electrically connected to an electrode of the semiconductor device; a first bonding surface which is a surface where the first surface layer and the bonding layer are in contact with each other; And an internal wiring formed on at least one of a second bonding surface that is a surface where the second surface layer and the bonding layer are in contact with each other; and the substrate for electrically connecting the substrate terminal and the internal wiring. The semiconductor device includes a first conductive hole formed in a region directly below the semiconductor device corresponding to the terminal.

A mounting structure according to the present invention is a mounting structure in which a semiconductor device is flip-chip mounted on a mounting surface of a circuit board, includes a region immediately below the semiconductor device, and is formed on a back surface of the mounting surface. It is characterized by including a metal foil.

The mounting structure according to the present invention comprises a first surface layer,
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a second surface layer and a bonding layer for bonding the first surface layer and the second surface layer,
A first semiconductor device flip-chip mounted on a surface layer, a substrate terminal formed on the first surface layer in a region immediately below the first semiconductor device and electrically connected to an electrode of the semiconductor device; An internal wiring formed on a first bonding surface where the first surface layer and the bonding layer are in contact with each other; a first wiring formed in the region directly below and electrically connecting the substrate terminal and the internal wiring; The semiconductor device is characterized by including a conductive hole and a metal foil formed on a second bonding surface where the second surface layer and the bonding layer are in contact with each other and including a region directly below the semiconductor device.

The mounting structure according to the present invention includes a sealing resin for fixing the semiconductor device to a corresponding surface layer for flip-chip mounting, and a region other than a region where the sealing resin is in contact with the corresponding surface layer. Surface wiring formed on the surface layer,
And a second conductive hole formed in the surface layer and electrically connecting the surface wiring and the internal wiring.

In the mounting structure according to the present invention, the first conductive hole is preferably an inner via hole.

In the mounting structure according to the present invention, it is more preferable that the second conductive hole is an inner via hole.

In the mounting structure according to the present invention, the metal foil is preferably made of copper.

The mounting structure according to the present invention comprises a first surface layer,
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a second surface layer and a bonding layer for bonding the first surface layer and the second surface layer,
A first semiconductor device flip-chip mounted on the surface layer,
A second semiconductor device flip-chip mounted at a position of a second surface layer which is plane-symmetric with respect to a position at which the first semiconductor device is mounted, with the bonding layer being a plane of symmetry. And

In the mounting structure according to the present invention, the first bonding surface that is the surface where the first surface layer and the bonding layer are in contact, and the second bonding surface that is the surface where the second surface layer and the bonding layer are in contact with each other. Preferably, an internal wiring is formed on at least one of the joining surfaces.

Further, in the mounting structure according to the present invention, the first semiconductor device and the second semiconductor device are electrically connected via an inner via hole formed in the multilayer circuit board. Is preferred.

The mounting structure according to the present invention comprises a first surface layer,
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a second surface layer and a bonding layer for bonding the first surface layer and the second surface layer,
A first semiconductor device flip-chip mounted on the surface layer,
A first substrate terminal formed on the first surface layer in a first region directly below the first semiconductor device and electrically connected to an electrode of the first semiconductor device; A first internal wiring formed on a first bonding surface where the layer and the bonding layer are bonded, formed in the first immediately lower region, and electrically connecting the first substrate terminal and the first internal wiring; A second semiconductor flip-chip mounted at a position of a second surface layer that is plane-symmetric with respect to a position at which the first semiconductor device is mounted, with the first conductive hole to be formed and the bonding layer being a plane of symmetry. apparatus,
Formed in a second region directly below the second semiconductor device;
The second electrically connected electrode of the second semiconductor device
Substrate terminal, a second internal wiring formed on a second bonding surface where the second surface layer and the bonding layer are bonded, and a second substrate terminal formed in the second immediately lower region and the second substrate terminal and the second And a third conductive hole for electrically connecting the internal wiring to the internal wiring.

The mounting structure according to the present invention includes a sealing resin for fixing at least one of the first semiconductor device and the second semiconductor device to a corresponding surface layer for flip-chip mounting, and the sealing resin. Surface wiring formed on the surface layer other than the region in contact with the corresponding surface layer,
And a second conductive hole formed in the surface layer and electrically connecting the surface wiring and the internal wiring.

Further, in the mounting structure according to the present invention, the first conductive hole is an inner via hole formed in the first surface layer, and the third conductive hole is formed in the inner via hole formed in the second surface layer. It is preferably a via hole.

[0034] A mounting structure according to the present invention is a mounting structure comprising a wiring connected on a circuit board and having different widths, and a semiconductor device mounted on the circuit board. It is characterized by being connected by arc-shaped wiring.

The method for manufacturing a mounting structure according to the present invention is characterized in that the position of the first semiconductor device flip-chip mounted on the first surface layer and the second semiconductor device flip-chip mounted on the second surface layer Wherein the position of the mounting structure is plane-symmetric with respect to a bonding layer that bonds the first surface layer and the second surface layer, wherein the first semiconductor device and the second At least one of the two semiconductor devices is flip-chip mounted on the corresponding surface layer using an anisotropic conductive film, the anisotropic conductive film is cured, and the semiconductor device is fixed to the corresponding surface layer. It is characterized by doing.

The method of manufacturing a mounting structure according to the present invention is characterized in that the position of the first semiconductor device flip-chip mounted on the first surface layer and the second semiconductor device flip-chip mounted on the second surface layer Wherein the position of the mounting structure is plane-symmetric with respect to the joining layer that joins the first surface layer and the second surface layer, wherein the first surface layer and the second surface layer Injecting a sealing resin into at least one predetermined position of the surface layer of No. 2, flip-chip mounting the semiconductor device corresponding to the predetermined position, and curing the sealing resin,
The semiconductor device is fixed to the surface layer.

According to the method of manufacturing a mounting structure according to the present invention, the position of the first semiconductor device flip-chip mounted on the first surface layer and the second semiconductor device flip-chip mounted on the second surface layer Wherein the position of the mounting structure is plane-symmetric with respect to the joining layer that joins the first surface layer and the second surface layer, wherein the first surface layer and the second surface layer A sealing resin is formed in a sheet shape at a predetermined position of at least one of the surface layers of the second surface layer, a semiconductor device corresponding to the predetermined position is flip-chip mounted, and the sealing resin is cured; Is fixed to the surface layer.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A mounting structure according to the present invention will be described below with reference to the drawings.

Embodiment 1 First, a mounting structure according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a two-wiring-layer substrate 1
1 is a schematic cross-sectional view of a mounting structure in which an IC substrate chip 1 is mounted by a flip chip method.

The two-wiring-layer substrate 11 includes the input / output terminal electrodes 7,
It includes a surface wiring layer 8 for electrically connecting chip components on the two wiring layer substrate 11, a back wiring layer 9 formed on the back surface 11b of the chip mounting surface 11a, and a via hole 4.

Next, the via hole 4 will be described. In this embodiment, an inner via hole is used as the via hole 4.
The formation of the via hole 4 employs a method of using a laser to penetrate a predetermined position in the chip mounting area 13b of the two-wiring layer substrate 11 and filling the through hole with a conductive paste. Note that a predetermined position of the two-wiring-layer substrate 11 may be penetrated by a drill, and the through-hole may be plated with a conductive material to form a via hole.

The electrode pads 3 of the IC substrate chip 1 are electrically connected to the input / output terminal electrodes 7 formed on the two-wiring-layer substrate 11 via the bump electrodes 2 and the conductive adhesive 6. The bump electrode 2 is formed on the electrode pad 3 by a known method. The back wiring layer 9 is electrically connected to the input / output terminal electrode 7 and the front wiring layer 8 via the via hole 4. The surface wiring layer 8 is not formed in the sealing resin region 13a where the sealing resin 5 is in contact with the mounting surface 11a. The back wiring layer 9 and the input / output terminal electrodes 7 are electrically connected via the via holes 4 in a region directly below the chip mounting region 13 b on the two-wiring-layer substrate 11.

When mounting the IC substrate chip 1 on the mounting surface 11a, the sealing resin 5 containing the silica filler 12 is injected between the IC substrate chip 1 and the mounting surface 11a, and then the sealing resin 5 is cured. By doing so, the fixation of the IC substrate chip 1 to the mounting surface 11a is strengthened. The silica filler 12 reduces the coefficient of thermal expansion of the sealing resin 5 and reduces the difference in coefficient of thermal expansion between the sealing resin and the wiring material. To this end, a material having at least one of high thermal conductivity and low thermal expansion coefficient may be used for the filler 12 instead of silica. Further, in this embodiment, solder or the like may be used as a substitute for the conductive adhesive 6 used for electrical connection between the IC substrate chip 1 and the two-wiring-layer substrate 11.

By forming the surface wiring layer 8 in a region other than the sealing resin region 13a, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, and to mount the wiring. The reliability of the structure can be improved.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a schematic sectional view of a mounting structure in which the IC substrate chip 1 is mounted on the four-wiring-layer substrate 16 by a flip-chip method. In addition, four wiring layer substrates 16
Are a surface layer 10 on which chip components are mounted, a bonding layer 14 for bonding the surface layer 10, an input / output terminal electrode 7, an internal wiring layer 15 formed between the surface layer 10 and the bonding layer 14, and a surface layer 10. It includes a surface wiring layer 8 for electrically connecting the upper chip components, and a via hole 4.

Next, the via hole 4 will be described. In this embodiment, an inner via hole is used as the via hole 4.
The formation of the via hole 4 is performed by using a surface layer 10 using a laser.
Of the chip mounting area 13b, and then filling the through-hole with a conductive paste. Note that a via hole may be formed by penetrating a predetermined position of the surface layer 10 with a drill and plating the through hole with a conductive material.

Through the pump electrode 2 and the conductive adhesive 6,
The electrode pads 3 are electrically connected to input / output terminal electrodes 7 formed on the surface layer 10. The bump electrode 2 is formed on the electrode pad 3 by a known method. The inner wiring layer 15 is electrically connected to the input / output terminal electrode 7 and the surface wiring layer 8 via the via hole 4. In this embodiment, the IC
As an alternative to the conductive adhesive 6 used for electrical connection between the substrate chip 1 and the surface layer 10, solder or the like may be used.

When mounting the IC substrate chip 1 on the surface layer 10, the sealing resin 5 containing the silica filler 12 is injected between the IC substrate chip 1 and the surface layer 10, and then the sealing resin 5 is cured. The surface layer 1 of the IC substrate chip 1
Fixation to zero is strengthened. The silica filler 12 reduces the coefficient of thermal expansion of the sealing resin 5 and reduces the difference in coefficient of thermal expansion between the sealing resin and the wiring material. To this end, a material having at least one of high thermal conductivity and low thermal expansion coefficient may be used for the filler 12 instead of silica.

In the sealing resin region 13a where the sealing resin 5 is in contact with the surface layer 10, the surface wiring layer 8 is not formed. Further, a chip mounting area 13b on the two wiring layer substrate 11
Of the internal wiring layer 15 via the via hole 4
And the input / output terminal electrode 7 are electrically connected.

By forming the surface wiring layer 8 in a region other than the sealing resin region 13a, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, and to mount the wiring. The reliability of the structure can be improved. Further, by using the inner via hole, the inner via hole for the semiconductor device can be easily designed.

Embodiment 3 Next, a third embodiment according to the present invention will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view of a mounting structure in which the IC substrate chip 1 is mounted on the chip mounting surface 11a of the two-layer wiring board 11 by a flip-chip method. 2
The wiring layer substrate 11 includes a surface wiring layer 8 for electrically connecting chip components on the two wiring layer substrate 11, and a chip mounting surface 11.
a includes a metal foil 23 formed on the back surface 11b.
The metal foil 23 includes a region immediately below the chip mounting region 13b. The IC substrate chip 1 is fixed to the two-wiring-layer substrate 11 with a sealing resin 5.

Through the pump electrode 2 and the conductive adhesive 6,
The electrode pads 3 of the IC substrate chip 1 are electrically connected to a surface wiring layer 8 formed on the surface layer 10. The bump electrode 2 is formed on the electrode pad 3 by a known method. In this embodiment, the IC substrate chip 1 and the surface layer 10
Solder or the like may be used as a substitute for the conductive adhesive 6 used for electrical connection with the semiconductor device.

Next, the metal foil 23 will be described. The metal foil 23 is twice as large as the chip mounting area 13b and is 18 μm
Of copper foil. In the present embodiment, the area of the metal foil 23 is twice as large as the chip mounting area 13b. However, it is effective if the area immediately below the corresponding chip mounting area 13b is included, and the area of the metal foil 23 is twice as large. However, the present invention is not limited to this. Further, a copper film formed by a plating method or the like may be used in place of the copper foil, and may be formed of a material having a thermal conductivity higher than copper or a Young's modulus higher than copper.

When mounting the IC substrate chip 1 on the mounting surface 11a, the sealing resin 5 containing the silica filler 12 is injected between the IC substrate chip 1 and the mounting surface 11a, and then the sealing resin 5 is cured. Thereby, the fixation of the IC substrate chip 1 to the mounting surface 11a is strengthened. The silica filler 12 reduces the coefficient of thermal expansion of the sealing resin 5 and reduces the difference in coefficient of thermal expansion between the sealing resin and the wiring material. According to this purpose,
A material having at least one of high thermal conductivity and low coefficient of thermal expansion may be used for the filler 12 instead of silica.

By forming the metal foil 23, the mounting surface 11
The stress generated at a is suppressed, and the influence on the surface wiring 8 is reduced. Further, by using copper of the same material as the wiring layer 8 as the material of the metal foil 23, it is possible to manufacture a circuit board without specially providing a metal foil forming step.

Embodiment 4 Next, a mounting structure according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 4 is a schematic sectional view of a mounting structure in which the IC substrate chip 1 is mounted on the four-wiring-layer substrate 16 by a flip-chip method. 4 wiring layer substrate 16
Are a surface layer 10 on which chip components are mounted, a bonding layer 14 for connecting the surface layer 10, an input / output terminal electrode 7, an internal wiring layer 15 formed between the surface layer 10 and the bonding layer 14, and a metal foil 23. , A surface wiring layer 8 for electrically connecting chip components on the surface layer 10, and via holes 4. In this embodiment, an inner via hole is used as the via hole 4.

The surface wiring layer 8 is not formed in the sealing resin region 13a where the sealing resin 5 is in contact with the surface layer 10. The input / output terminal electrode 7 is electrically connected to the internal wiring layer 15 and the surface wiring layer 8 via the via hole 4 in a region directly below the chip mounting region 13 b of the surface layer 10. The metal foil 23 includes a region immediately below the chip mounting region 13b. The method of forming the via hole 4, the method of mounting the IC substrate chip 1, and the materials of the filler 12 and the metal foil 23 included in the sealing resin 5 are the same as those in the second embodiment.

By forming the surface wiring layer 8 in a region other than the sealing resin region 13a, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, and to mount the wiring. The reliability of the structure can be improved. Further, by forming the metal foil 23, the surface layer 1
The stress generated at 0 can be suppressed.

Fifth Embodiment Next, a fifth embodiment according to the present invention will be described with reference to FIG. FIG. 5 is a schematic diagram of a mounting structure in which a first IC substrate chip 1a and a second IC substrate chip 1b are mounted on the first surface layer 10a and the second surface layer 10b of the four wiring layer substrate 16, respectively. FIG. The first IC substrate chip 1a and the second IC substrate chip 1b
It is mounted at a position symmetrical with respect to the bonding layer 14.

The flip-chip system in which the electrode pads 3 of the first IC substrate chip 1 a are electrically connected to the input / output terminal electrodes 7 and the surface wiring layer 8 via the bump electrodes 2 and the conductive adhesive 6. The first IC substrate chip 1a is mounted on the first surface layer 10a. The bump electrode 2 is formed by a known method.

When mounting the first IC substrate chip 1a on the first surface layer 10a, the first IC substrate chip 1a and the first
Of the first IC substrate chip 1a to the first surface layer 10a by injecting the sealing resin 5 containing the silica filler 12 between the first IC chip 1a and the first surface layer 10a. Is strengthened. Silica filler 12 is sealing resin 5
Is reduced, and the difference in the coefficient of thermal expansion between the sealing resin and the wiring material is reduced. To this end, a material having at least one of high thermal conductivity and low thermal expansion coefficient may be used for the filler 12 instead of silica.

Similarly, the electrode pads 3 of the second IC substrate chip 1 b are interposed via the bump electrodes 2 and the conductive adhesive 7.
Is a flip-chip type electrically connected to the input / output terminal electrode 6 and the surface wiring layer 8, and the second IC substrate chip 1
b is mounted on the second surface layer 10b. Bump electrode 2
Is formed by a known method.

Second surface layer 1 of second IC substrate chip 1b
For mounting on Ob, an anisotropic conductive film 17 is used.
The first IC substrate chip 1a and the second IC substrate chip 1b are electrically connected via the internal wiring layer 15 and the via hole 4. In this embodiment, an inner via hole is used as the via hole.

In this embodiment, the first IC substrate chip 1a
The conductive adhesive 6 is used to mount the second IC board chip 1b, and the anisotropic conductive film 17 is used to mount the second IC board chip 1b. However, the present invention is not limited thereto, and both of the two IC substrate chips may be mounted using a conductive adhesive or an anisotropic conductive film. In addition, solder or the like may be used as a substitute for the conductive adhesive 9 used for the electrical connection between the first IC substrate chip 1a and the first surface layer 10a in this embodiment.

When both IC substrate chips are mounted using a conductive adhesive, the sealing resin is suctioned to a predetermined position on the surface layer in order to inject the sealing resin between the semiconductor device and the surface layer. After the injection or after the sealing resin is formed in a sheet shape at a predetermined position on the surface layer, the semiconductor device needs to be mounted with a conductive adhesive.

By forming the two semiconductor devices at symmetrical positions, it is possible to suppress the stress and deformation generated in the wiring of each surface layer. Further, by using the inner via holes, the two semiconductor devices can be easily manufactured. Can be electrically connected to

Embodiment 6 Next, with reference to FIG. 6, a sixth embodiment according to the present invention will be described. FIG. 6 is a schematic cross section of a mounting structure in which a first IC substrate chip 1a and a second IC substrate chip 1b are mounted on a first surface layer 10a and a second surface layer 10b of a four-wiring layer substrate 16, respectively. FIG. First IC
The substrate chip 1a and the second IC substrate chip 1b are mounted at positions symmetrical with respect to the bonding layer 14.

As in the fifth embodiment, the first IC substrate chip 1a and the second IC substrate chip 1b are mounted on the first surface layer 10a and the second surface layer 10b by a flip chip method, respectively. ing. The fixing of the two IC board chips to the surface layer is enhanced by the sealing resin 5.

The surface wiring layer 8 is not formed in the sealing resin region 13a where the sealing resin 5 contacts the first surface layer 10a and the second surface layer 10b. Further, both chip mounting areas 13
The input / output terminal electrode 7 and the internal wiring layer 15 are electrically connected to each other via the via hole 4 in a region immediately below the area b. Material of filler 12 and via hole 4 included in sealing resin 5
Is the same as that described in Examples 1 to 6 described above.

Embodiment 7 Next, a seventh embodiment according to the present invention will be described. Seventh
The mounting structure according to the embodiment has a semiconductor device mounted on a mounting surface of a circuit board. As in the previous embodiment,
In the flip chip method, the electrode pads of the semiconductor device and the input / output terminal electrodes or surface wiring layers corresponding to the respective electrode pads formed on the mounting surface are electrically connected via bump electrodes and a conductive adhesive. A semiconductor device is mounted on a circuit board. Further, the surface wirings do not have a uniform width, but have different widths, and the wirings having different widths are connected by wirings formed in an arc shape. The bump electrodes are formed on the electrode pads of the semiconductor device by a known method.

The semiconductor device contains silica filler and is fixed to the surface layer with a thermosetting sealing resin. The material of the filler contained in the sealing resin is of the same type as in Examples 1 to 6 described above. As an alternative to the conductive adhesive used for the electrical connection between the semiconductor device and the mounting surface in this embodiment, solder or the like can be mentioned.

By connecting the wirings having different widths of the surface wiring layer by arc-shaped wirings, the stress generated due to the difference in thermal expansion coefficient between the sealing resin, the wirings and the circuit board is dispersed, and the disconnection of the wirings is suppressed. can do.

[0073]

According to the mounting structure of the present invention, the surface wiring in the sealing resin region of the semiconductor device is eliminated, and the wiring is formed as the rear wiring on the rear surface of the mounting surface. Accordingly, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, thereby improving the reliability of the mounting structure.

The mounting structure according to the present invention is one in which a surface wiring is formed on the surface layer other than the sealing resin region. Accordingly, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, thereby improving the reliability of the mounting structure.

The mounting structure according to the present invention excludes surface wiring in the mounting region of the semiconductor device, and forms such wiring as an internal wiring between the surface layer and the bonding layer. By doing so, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, thereby improving the reliability of the mounting structure.

In the mounting structure according to the present invention, a metal foil including a region directly below the semiconductor device is formed on the back surface of the mounting surface. This increases the coefficient of thermal expansion of the circuit board and reduces the difference in coefficient of thermal expansion between the circuit board and the sealing resin, thereby reducing the stress generated in the wiring on the surface layer. Further, the stress generated by giving the circuit board rigidity can be suppressed.

The mounting structure according to the present invention includes a region immediately below the semiconductor device between the surface layer and the bonding layer with a metal foil, and eliminates surface wiring in the semiconductor mounting region.
Such a wiring is formed as an internal wiring layer between the surface layer and the bonding layer. Thus, the stress generated in the sealing resin region does not affect the surface wiring, and the generated stress can be suppressed.

The mounting structure according to the present invention has a surface wiring layer electrically connected to a semiconductor device other than the sealing resin region of the surface layer. Accordingly, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, thereby improving the reliability of the mounting structure.

A mounting structure according to the present invention uses an inner via hole for electrical connection between an internal wiring and an electrode of a semiconductor device. By doing so, it is possible to easily design the formation position of the mounting via hole of the semiconductor device, and the electrical connection between the electrode of the semiconductor device and the internal wiring can be performed in a region directly below the semiconductor device.

The mounting structure according to the present invention uses an inner via hole for electrical connection between the internal wiring and the surface wiring. This makes it possible to easily design the formation position of the mounting via hole of the semiconductor device.

In the mounting structure according to the present invention, the metal foil is preferably made of copper. Since copper is also used as the wiring of the circuit board, the circuit board can be manufactured without specially providing a metal foil forming step.

The mounting structure according to the present invention is one in which two semiconductor devices are mounted at symmetrical positions on two opposing surface layers. Thereby, stress and deformation generated in the wiring of each surface layer can be suppressed.

The mounting structure according to the present invention has two semiconductor devices mounted at symmetrical positions on two opposing surface layers, and further has at least one internal wiring layer. Thus, it is possible to suppress the stress and deformation generated in the wiring of each surface layer of the mounting structure having the internal wiring.

The mounting structure according to the present invention is one in which the above two semiconductor devices are electrically connected via an inner via hole. This makes it possible to easily electrically connect the two semiconductor devices.

The mounting structure according to the present invention is obtained by mounting two semiconductor devices at symmetrical positions on two opposing surface layers. Further, the surface wiring layer in the mounting regions of the two semiconductor devices is eliminated, and the wiring is formed as an internal wiring between the surface layer and the bonding layer. This alleviates the stress and deformation generated on the surface layer, and further improves the reliability of the mounting structure.

The mounting structure according to the present invention has a surface wiring layer electrically connected to the semiconductor device other than the sealing resin region of the surface layer. Accordingly, it is possible to prevent a problem that a stress generated due to a difference in thermal expansion coefficient between the circuit board, the sealing resin, and the wiring breaks the wiring, thereby improving the reliability of the mounting structure.

A mounting structure according to the present invention uses an inner via hole for electrical connection between an internal wiring and an electrode of a semiconductor device. By doing so, it is possible to easily design the formation position of the mounting via hole of the semiconductor device, and the electrical connection between the electrode of the semiconductor device and the internal wiring can be performed in a region directly below the semiconductor device.

The mounting structure according to the present invention is obtained by connecting wirings having different widths on the mounting surface on which the semiconductor device is mounted by arc-shaped wirings. Thereby, the stress applied to the wiring can be dispersed.

In the method for manufacturing a mounting structure according to the present invention, at least one of two semiconductor devices mounted on a circuit board is mounted using an anisotropic conductive film. This facilitates mounting of the semiconductor device on a circuit board.

In the method for manufacturing a mounting structure according to the present invention, after injecting a sealing resin into a predetermined position of at least one of the first surface layer and the second surface layer, the corresponding semiconductor device is mounted. Then, the semiconductor device is fixed by curing the sealing resin. As a result, a highly reliable mounting structure can be manufactured.

In the method for manufacturing a mounting structure according to the present invention, a resin material is formed in a sheet shape at a predetermined position on at least one of the first surface layer and the second surface layer, and then the corresponding semiconductor device is formed. Is to implement. As a result, a highly reliable mounting structure can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a mounting structure according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view of a mounting structure according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view of a mounting structure according to a third embodiment of the present invention.

FIG. 4 is a schematic sectional view of a mounting structure according to a fourth embodiment of the present invention.

FIG. 5 is a schematic sectional view of a mounting structure according to a fifth embodiment of the present invention.

FIG. 6 is a schematic sectional view of a mounting structure according to a sixth embodiment of the present invention.

FIGS. 7A and 7B show a mounting structure according to a first conventional example.

FIG. 8 is a schematic cross-sectional view of a mounting structure according to a second conventional example.

FIG. 9 is a schematic cross-sectional view of a mounting structure according to a third conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... IC board chip 2 ... Bump electrode 3 ... Electrode pad 4 ... Via hole 5 ... Seal resin 6 ... Conductive adhesive 7 ... Input / output terminal electrode 8 ... Surface wiring layer 9 ... Back wiring layer 10 ... Surface layer 11 ... 2 Wiring layer substrate 12 Filler 13a Sealing resin region 13b Semiconductor device mounting region 14 Bonding layer 15 Internal wiring layer 16 Four wiring layer substrate 17 Anisotropic conductive film 18 Diffusion preventing metal film 19 Adhesive metal film Reference Signs List 20 solder bump 21 circuit board 22 Au bump 23 metal foil

Continued on the front page (72) Inventor Kazuo Eda 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (19)

[Claims] 1. A mounting structure in which a semiconductor device is flip-chip mounted on a mounting surface of a circuit board, wherein the semiconductor device is formed on the mounting surface in a region directly below the semiconductor device,
A substrate terminal electrically connected to the electrode of the semiconductor device, a back wiring formed on the back surface of the mounting surface, and an electrical connection between the substrate terminal and the back wiring formed on the circuit board in the region immediately below A mounting structure, comprising: a first conductive hole that is electrically connected. 2. A sealing resin for fixing the semiconductor device to the mounting surface for flip-chip mounting, a surface wiring formed on the mounting surface other than a region where the sealing resin is in contact with the mounting surface, and The mounting structure according to claim 1, further comprising a second conductive hole formed on the circuit board and electrically connecting the front surface wiring and the rear surface wiring. 3. The first surface layer, the second surface layer, and the first surface layer.
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a bonding layer for bonding a surface layer and the second surface layer, wherein the semiconductor device is mounted on the surface layer on which the semiconductor device is mounted. A substrate terminal formed in a region directly below and electrically connected to an electrode of the semiconductor device; a first bonding surface which is a surface where the first surface layer and the bonding layer are in contact; and a bonding between the second surface layer and the second surface layer An internal wiring formed on at least one of the second bonding surfaces that is in contact with the layer, and a region directly below the semiconductor device corresponding to the substrate terminal, for electrically connecting the substrate terminal and the internal wiring. A first conductive hole formed in the mounting structure. 4. A mounting structure in which a semiconductor device is flip-chip mounted on a mounting surface of a circuit board, including a region immediately below the semiconductor device and including a metal foil formed on a back surface of the mounting surface. Mounting structure characterized by the following. 5. A first surface layer, a second surface layer, and the first surface layer.
A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a bonding layer for bonding a surface layer and the second surface layer, wherein the first semiconductor flip-chip mounted on the first surface layer A device, a substrate terminal formed on the first surface layer in a region directly below the first semiconductor device, and electrically connected to an electrode of the semiconductor device, wherein the first surface layer and the bonding layer are An internal wiring formed on a first bonding surface that is in contact with the first conductive hole formed in the region directly below and electrically connecting the substrate terminal and the internal wiring; and a bonding between the second conductive layer and a second surface layer. A mounting structure comprising a metal foil formed on a second bonding surface in contact with a layer and including a region immediately below the semiconductor device. 6. A sealing resin for fixing the semiconductor device to a corresponding surface layer for flip-chip mounting, wherein the sealing resin is formed on the surface layer other than a region in contact with the corresponding surface layer. The mounting structure according to claim 3, further comprising: a surface wiring; and a second conductive hole formed in the surface layer and electrically connecting the surface wiring and the internal wiring. 7. The mounting structure according to claim 3, wherein the first conductive hole is an inner via hole. 8. The mounting structure according to claim 6, wherein the second conductive hole is an inner via hole. 9. The mounting structure according to claim 4, wherein the metal foil is copper. 10. A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a first surface layer, a second surface layer, and a bonding layer for bonding the first surface layer and the second surface layer. A first semiconductor device flip-chip mounted on the first surface layer, and a second surface which is plane-symmetric with respect to a position where the first semiconductor device is mounted, with the bonding layer being a plane of symmetry. A second semiconductor device which is flip-chip mounted at the position of the surface layer. 11. A bonding surface between the first surface layer and the bonding layer, and a second bonding surface between the second surface layer and the bonding layer. The mounting structure according to claim 10, wherein an internal wiring is formed in the mounting structure. 12. The semiconductor device according to claim 10, wherein the first semiconductor device and the second semiconductor device are electrically connected via an inner via hole formed in the multilayer circuit board.
Or the mounting structure according to 11. 13. A mounting structure in which a semiconductor device is flip-chip mounted on a multilayer circuit board having a first surface layer, a second surface layer, and a bonding layer for bonding the first surface layer and the second surface layer. A first semiconductor device flip-chip mounted on the first surface layer; a first semiconductor device formed on the first surface layer in a first region directly below the first semiconductor device; A first substrate terminal electrically connected to an electrode of the semiconductor device; a first internal wiring formed on a first bonding surface where the first surface layer and the bonding layer are bonded; A first conductive hole formed to electrically connect the first substrate terminal and the first internal wiring; and a position where the first semiconductor device is mounted, with the bonding layer being a plane of symmetry. A second flip-chip mounted flip-chip mounted at the position of the second surface layer that is plane-symmetric Semiconductor device, is formed in the second immediately below the region of the second semiconductor device,
The second electrically connected electrode of the second semiconductor device
A second internal wiring formed on a second bonding surface where the second surface layer and the bonding layer are bonded to each other; a second internal terminal formed in the second immediately lower region; A third conductive hole for electrically connecting the internal wiring to the internal wiring. 14. A sealing resin for fixing at least one of the first semiconductor device and the second semiconductor device to a corresponding surface layer for flip-chip mounting, wherein the sealing resin corresponds to the corresponding surface layer. 14. A surface wiring formed on the surface layer other than the contacting region, and a second conductive hole formed on the surface layer and electrically connecting the surface wiring and the internal wiring. The described mounting structure. 15. The semiconductor device according to claim 13, wherein the first conductive hole is an inner via hole formed in the first surface layer, and the third conductive hole is an inner via hole formed in the second surface layer. Mounting structure. 16. A mounting structure comprising a wiring having different widths connected on a circuit board and a semiconductor device mounted on the circuit board, wherein the wirings having different widths are connected by arc-shaped wiring. A mounting structure, characterized in that: 17. The position of the first semiconductor device flip-chip mounted on the first surface layer and the position of the second semiconductor device flip-chip mounted on the second surface layer correspond to the first surface. A method of manufacturing a mounting structure which is plane-symmetric with respect to a bonding layer for bonding a layer and the second surface layer, wherein at least one of the first semiconductor device and the second semiconductor device is formed. A flip-chip mounting using an anisotropic conductive film on a corresponding surface layer, curing the anisotropic conductive film, and fixing the semiconductor device to the corresponding surface layer. Production method. 18. The position of the first semiconductor device flip-chip mounted on the first surface layer and the position of the second semiconductor device flip-chip mounted on the second surface layer correspond to the first surface. A method of manufacturing a mounting structure which is plane-symmetric with respect to a bonding layer for bonding a layer and the second surface layer, wherein at least one of the first surface layer and the second surface layer is provided. Injecting a sealing resin into a predetermined position, flip-chip mounting a semiconductor device corresponding to the predetermined position, curing the sealing resin, and fixing the semiconductor device to the surface layer. The method of manufacturing the structure. 19. The position of the first semiconductor device flip-chip mounted on the first surface layer and the position of the second semiconductor device flip-chip mounted on the second surface layer are the first surface. A method of manufacturing a mounting structure which is plane-symmetric with respect to a bonding layer for bonding a layer and the second surface layer, wherein at least one of the first surface layer and the second surface layer is provided. Forming a sealing resin at a predetermined position in a sheet shape, flip-chip mounting a semiconductor device corresponding to the predetermined position, curing the sealing resin, and fixing the semiconductor device to the surface layer. Manufacturing method of the mounting structure.