JPH05121590A - Surface mounting type semiconductor device - Google Patents
Surface mounting type semiconductor deviceInfo
- Publication number
- JPH05121590A JPH05121590A JP3278089A JP27808991A JPH05121590A JP H05121590 A JPH05121590 A JP H05121590A JP 3278089 A JP3278089 A JP 3278089A JP 27808991 A JP27808991 A JP 27808991A JP H05121590 A JPH05121590 A JP H05121590A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- solder
- semiconductor device
- outer lead
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、表面実装型半導体装
置に関するものである。さらに詳しくは、この発明は、
実装信頼性に優れた表面実装型半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount semiconductor device. More specifically, the present invention is
The present invention relates to a surface mount semiconductor device having excellent mounting reliability.
【０００２】[0002]
【従来の技術】従来より、電気・電子機器、通信機器、
計算機等の各種のエレクトロニクスの分野においては、
表面実装型の各種の半導体装置が使用されてきている。
この従来の表面実装型半導体装置は、たとえば図１０に
示したように、セラミック製もしくはプラスチック製の
回路基板（ア）のキャビティに半導体チップ（イ）を搭
載し、導体回路とこの半導体チップ（イ）とを金属ワイ
ヤ（ウ）により接続するとともに、0.2 〜0.3mm 径程度
の小径で、かつ、１〜２mmの長さのピン、すなわちアウ
ターリード（エ）を電気的に接続した構造を有してい
る。そして、このような構造の表面実装型半導体装置
は、図１１に部分拡大して示したように、前記のアウタ
ーリード（エ）を、大型プリント配線板、すなわちマザ
ーボード（オ）のランド部（カ）に半田フィレット
（キ）を用いて接続するようにしている。2. Description of the Related Art Conventionally, electrical and electronic equipment, communication equipment,
In the field of various electronics such as computers,
Various surface mount semiconductor devices have been used.
In this conventional surface mount semiconductor device, for example, as shown in FIG. 10, a semiconductor chip (a) is mounted in a cavity of a ceramic or plastic circuit board (a), and a conductor circuit and this semiconductor chip (a) are mounted. ) Is connected by a metal wire (c) and a pin having a small diameter of about 0.2 to 0.3 mm and a length of 1 to 2 mm, that is, an outer lead (d) is electrically connected. ing. In the surface-mounted semiconductor device having such a structure, as shown in a partially enlarged view of FIG. 11, the outer lead (d) is connected to the land portion (cover) of the large printed wiring board, that is, the mother board (e). ) Is connected by using a solder fillet.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この従
来の表面実装型半導体装置は、アウターリード（エ）の
ピン径が細いために、その強度が弱く、実装時の扱い等
においてピンが非常に曲がりやすく、実装信頼性を低下
させていた。そこで、この発明は、以上の通りの従来の
装置の欠点を解消し、機械的強度の大きなアウターリー
ドを有し、高い実装信頼性を発揮することのできる改良
された表面実装型半導体装置を提供することを目的とし
ている。However, in this conventional surface mount type semiconductor device, since the pin diameter of the outer lead (d) is small, the strength thereof is weak, and the pin is very bent when mounted. It was easy and reduced the mounting reliability. Therefore, the present invention provides an improved surface mount type semiconductor device which solves the above-mentioned drawbacks of the conventional device, has an outer lead having a large mechanical strength, and can exhibit high mounting reliability. The purpose is to do.
【０００４】[0004]
【課題を解決するための手段】この発明は、上記の課題
を解決するものとして、表面実装型半導体装置のアウタ
ーリード部にスルホールを設け、このスルホールの開口
端周辺に、スルホールに接続する厚みのある金属製バン
プを配設してなることを特徴とする表面実装型半導体装
置を提供する。In order to solve the above problems, the present invention provides a through hole in an outer lead portion of a surface mount type semiconductor device, and has a thickness around the opening end of the through hole which is connected to the through hole. Provided is a surface-mounted semiconductor device having certain metal bumps.
【０００５】また、この発明は前記半導体装置におい
て、バンプ表面に半田層を設けることや、スルホール内
にも半田が充填されている表面実装型半導体装置をその
一つの態様としてもいる。このような構造からなるこの
発明の表面実装型半導体装置においては、たとえば図１
および図２に例示したように、半導体チップ（１）を搭
載した従来と同様のセラミック製もしくはプラスチック
製の適宜な回路基板（２）にスルホール（３）を形成
し、このスルホール（３）の回路と電気的に接続した金
属製バンプ（４）をスルホール開口端に配設している。
そして、この場合の金属製バンプ（４）は、半田（５）
に濡れやすい金属によって構成するか、または、半田
（５）に濡れやすい金属層をその表面に持つようにす
る。Further, the present invention has, as one aspect thereof, a surface mount type semiconductor device in which a solder layer is provided on the surface of the bump in the semiconductor device and solder is filled in the through holes. In the surface mount type semiconductor device of the present invention having such a structure, for example, as shown in FIG.
As illustrated in FIG. 2 and FIG. 2, a through hole (3) is formed in an appropriate circuit board (2) made of ceramic or plastic similar to the conventional one, on which the semiconductor chip (1) is mounted. A metal bump (4) electrically connected to is disposed at the opening end of the through hole.
The metal bumps (4) in this case are solder (5).
It is made of a metal that easily wets the solder, or has a metal layer that easily wets the solder (5) on its surface.
【０００６】さらにまた、前記の通り、金属製バンプ
（４）の表面には、半田層を設けてもよい。なお、図２
のようにスルホール（３）内に半田（５）を充填するこ
とも有効である。このようなバンプとしては、長さが７
０μｍ以上あることが好ましい。また、バンプの形状は
適宜とすることができる。Furthermore, as described above, a solder layer may be provided on the surface of the metal bump (4). Note that FIG.
It is also effective to fill the through hole (3) with the solder (5) as described above. Such a bump has a length of 7
It is preferably 0 μm or more. Also, the shape of the bump can be set appropriately.
【０００７】[0007]
【作用】この本発明の表面実装型半導体装置では、アウ
ターリードを従来のピン型から金属製バンプに変更する
ことにより、従来のように強度が弱いことによるリード
の曲がりが発生せず、高い実装信頼性が発揮される。ま
た、図３に示したように、金属製バンプ（４）の上に半
田（５）層を設けることにより、マザーボード（６）の
ランド部（７）への実装時に、半田濡れ性が優れたもの
となる。In this surface mounting type semiconductor device of the present invention, the outer lead is changed from the conventional pin type to the metal bump, so that bending of the lead due to weak strength unlike the conventional case does not occur and high mounting is achieved. Reliability is demonstrated. Further, as shown in FIG. 3, by providing the solder (5) layer on the metal bumps (4), the solder wettability was excellent at the time of mounting on the land portion (7) of the motherboard (6). Will be things.
【０００８】また、図４にも示したように、スルホール
内に半田（５）を充填する場合には、クリーム半田印刷
等にて半田の量がばらついても不足している分だけスル
ホール内の半田が流出し、半田不足を補い、高い実装信
頼性を実現する。半導体装置のバンプ（４）とマザーボ
ード（６）上のランド（７）の間隔が狭いことと半田
（５）の表面張力により、過剰に半田が供給されアウタ
ーリード間で短絡することもない。さらには、実装のた
めの半田をマザーボードへ供給しなくても、半導体装置
からだけでも十分な半田を供給でき、半導体装置やマザ
ーボードに反りがあっても半田が必要なだけ供給される
ことにより、半導体装置とマザーボード間の電気的接続
が容易に確保できる。Further, as shown in FIG. 4, when the solder (5) is filled in the through hole, even if the amount of the solder varies due to cream solder printing or the like, the amount of the solder in the through hole is insufficient. Solder leaks out to compensate for the lack of solder and achieve high mounting reliability. Due to the small distance between the bumps (4) of the semiconductor device and the lands (7) on the motherboard (6) and the surface tension of the solder (5), excessive solder is not supplied and a short circuit occurs between the outer leads. Furthermore, even if the solder for mounting is not supplied to the mother board, sufficient solder can be supplied only from the semiconductor device, and even if the semiconductor device or the mother board is warped, the necessary amount of solder can be supplied. The electrical connection between the semiconductor device and the motherboard can be easily secured.
【０００９】バンプ厚みを７０μｍ以上とすることによ
り、半導体装置とマザーボード間に溜まったフラック
ス、半田ボール等の洗浄性を上げることになる。By setting the bump thickness to 70 μm or more, the cleaning properties of the flux, solder balls and the like accumulated between the semiconductor device and the mother board can be improved.
【００１０】[0010]
【実施例】以下、添付した図面に沿って実施例を示し、
さらに詳しくこの発明の表面実装型半導体装置について
説明する。なお、以下の図は、アウターリード部を拡大
して例示している。図５（ａ）（ｂ）は、スルホール
（１０）の開口端周囲に設けられたランド部（１１）
に、電気メッキにより銅を厚く形成し、表面にニッケル
メッキ、次いで金メッキを施して銅メッキベースのバン
プ（１２）を設け、かつ、このバンプ（１２）表面に半
田（１３）層を設けた例を示している。この場合のバン
プ（１２）は、円環状の平面を有してもいる。EXAMPLES Examples will be shown below with reference to the accompanying drawings.
The surface mount semiconductor device of the present invention will be described in more detail. In addition, in the following figures, the outer lead portion is enlarged and illustrated. 5 (a) and 5 (b) are land portions (11) provided around the open end of the through hole (10).
An example in which copper is thickly formed by electroplating, nickel plating is performed on the surface, and then gold plating is performed to provide bumps (12) of a copper plating base, and solder (13) layers are provided on the surfaces of the bumps (12). Is shown. The bump (12) in this case also has an annular flat surface.
【００１１】図６（ａ）（ｂ）は、同様の形状におい
て、スルホール（１０）の周囲のランド部（１１）に、
電気メッキによりニッケルを厚く形成し、その上に金メ
ッキを施したニッケルメッキベースのバンプ（１４）を
設けた例を示し、かつ、このバンプは円環状の平面を有
してもいる。図７（ａ）（ｂ）は、ランド部（１１）
に、表面が金メッキされたニッケルスラグを半田または
銀ベーストにて接着したバンプ（１５）の例を示してい
る。この例の場合には、図７（ｂ）に示したように、ラ
ンド部（１１）に対して、微小角柱状に、この金メッキ
被覆ニッケルスラグベースバンプ（１５）を設けた構造
を有している。FIGS. 6 (a) and 6 (b) show the same shape in the land portion (11) around the through hole (10).
An example is shown in which nickel is thickly formed by electroplating and a nickel-plated bump (14) plated with gold is provided on the nickel, and the bump also has an annular flat surface. 7 (a) and 7 (b) show the land portion (11).
FIG. 3 shows an example of the bump (15) in which nickel slag whose surface is plated with gold is bonded with solder or silver base. In the case of this example, as shown in FIG. 7B, the land portion (11) has a structure in which the gold-plated nickel slag base bump (15) is provided in a minute prismatic shape. There is.
【００１２】図８（ａ）（ｂ）は、スルホール（１０）
周辺のランド部（１１）に、電気メッキにより銅を厚く
形成してバンプ（１６）とした後に、このバンプ（１
６）の表面に半田（１３）層を設けた構造としている。
図９（ａ）（ｂ）は、スルホール（１０）周辺のランド
部に、電気メッキにより銅を厚く形成してバンプ（１
７）とし、その表面に半田（１３）層を設けるととも
に、スルホール（１０）内に半田（１３）を充填した構
造を示している。8 (a) and 8 (b) show a through hole (10).
After copper is thickly formed on the peripheral land portion (11) by electroplating to form bumps (16), the bumps (1
It has a structure in which a solder (13) layer is provided on the surface of 6).
9 (a) and 9 (b) show that bumps (1) are formed by thickly forming copper on lands around the through holes (10) by electroplating.
7), a solder (13) layer is provided on the surface, and the through hole (10) is filled with the solder (13).
【００１３】たとえば以上のように、金属製バンプの形
成方法、その形状には各種のものが可能であり、半田層
の配設、さらにはスルホール内への半田の充填も任意に
可能である。このようなアウターリード構造を持つこの
発明の表面実装型半導体装置によって、従来のものより
はるかに実装時の接続信頼性に優れた半導体装置が実現
される。For example, as described above, various methods can be used for forming the metal bumps and their shapes, and a solder layer can be arranged and solder can be filled in the through holes. With the surface-mounted semiconductor device of the present invention having such an outer lead structure, a semiconductor device having much better connection reliability during mounting than the conventional one is realized.
【００１４】[0014]
【発明の効果】以上詳しく説明した通り、この発明によ
って、アウターリードの機械的強度に優れ、かつ実装時
の接続信頼性に優れた表面実装型半導体装置が得られ
る。さらには実装時に必要な半田を半導体装置から供給
することもでき、反り等があっても必要な半田が供給さ
れ、高い接続信頼性が得られる。実装時の洗浄性も確保
される。As described in detail above, according to the present invention, a surface mount type semiconductor device having excellent mechanical strength of the outer leads and excellent connection reliability during mounting can be obtained. Furthermore, the solder required during mounting can be supplied from the semiconductor device, and the required solder can be supplied even if there is warpage or the like, and high connection reliability can be obtained. The cleanability at the time of mounting is also secured.
【図１】この発明の半導体装置を例示した断面図であ
る。FIG. 1 is a sectional view illustrating a semiconductor device of the present invention.
【図２】スルホール内に半田が充填されたこの発明の半
導体装置例を示した断面図である。FIG. 2 is a sectional view showing an example of a semiconductor device of the present invention in which a through hole is filled with solder.
【図３】この発明の半導体装置のマザーボードへの実装
時の状態を示した断面図である。FIG. 3 is a cross-sectional view showing a state when the semiconductor device of the present invention is mounted on a motherboard.
【図４】図３と同様の実装時の状態を示した断面図であ
る。FIG. 4 is a cross-sectional view showing a state at the time of mounting similar to FIG.
【図５】銅メッキベースのバンプを例示した実施例の断
面図である。FIG. 5 is a cross-sectional view of an example illustrating a copper-plated base bump.
【図６】ニッケルメッキベースのバンプを例示した実施
例の断面図である。FIG. 6 is a cross-sectional view of an example illustrating a nickel-plated base bump.
【図７】金メッキ被覆ニッケルスラグバンプを例示した
実施例の断面図である。FIG. 7 is a cross-sectional view of an example illustrating a gold-plated nickel slag bump.
【図８】半田層を設けた実施例を示した断面図である。FIG. 8 is a cross-sectional view showing an example in which a solder layer is provided.
【図９】スルホールに半田を充填した実施例を示した断
面図である。FIG. 9 is a sectional view showing an embodiment in which a through hole is filled with solder.
【図１０】従来の表面実装型半導体装置を示した正面図
である。FIG. 10 is a front view showing a conventional surface mount semiconductor device.
【図１１】従来の装置におけるアウターリード部の実装
状態を示した断面図である。FIG. 11 is a cross-sectional view showing a mounted state of an outer lead portion in a conventional device.
１ 半導体チップ ２ 回路基板 ３ スルホール ４ 金属製バンプ ５ 半田 ６ マザーボード ７ ランド部 １０ スルホール １１ ランド部 １２ 銅メッキベースバンプ １３ 半田 １４ ニッケルメッキベースバンプ １５ 金メッキ被覆ニッケルスラグベースバンプ １６，１７ バンプ 1 Semiconductor Chip 2 Circuit Board 3 Through Hole 4 Metal Bump 5 Solder 6 Motherboard 7 Land Part 10 Through Hole 11 Land Part 12 Copper Plating Base Bump 13 Solder 14 Nickel Plating Base Bump 15 Gold Plating Nickel Slag Base Bump 16, 17 Bump
Claims (3)
部にスルホールを設け、このスルホールの開口端周辺
に、スルホールに接続する厚みのある金属製バンプを配
設してなることを特徴とする表面実装型半導体装置。1. A surface-mounting semiconductor device comprising: a through hole provided in an outer lead portion; and a thick metal bump connected to the through hole disposed around an opening end of the through hole. Type semiconductor device.
１の表面実装型半導体装置。2. The surface mount semiconductor device according to claim 1, wherein a solder layer is provided on the bump surface.
請求項２の表面実装型半導体装置。3. The surface mount semiconductor device according to claim 2, wherein the through holes are also filled with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3278089A JPH05121590A (en) | 1991-10-24 | 1991-10-24 | Surface mounting type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3278089A JPH05121590A (en) | 1991-10-24 | 1991-10-24 | Surface mounting type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05121590A true JPH05121590A (en) | 1993-05-18 |
Family
ID=17592487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3278089A Pending JPH05121590A (en) | 1991-10-24 | 1991-10-24 | Surface mounting type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05121590A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994025984A1 (en) * | 1993-04-23 | 1994-11-10 | Nihon Micron Kabushiki Kaisha | Ic package and method of its manufacture |
| KR100577015B1 (en) * | 2003-07-29 | 2006-05-10 | 매그나칩 반도체 유한회사 | Stacked chip package of the semiconductor device and method for manufacturing thereof |
-
1991
- 1991-10-24 JP JP3278089A patent/JPH05121590A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994025984A1 (en) * | 1993-04-23 | 1994-11-10 | Nihon Micron Kabushiki Kaisha | Ic package and method of its manufacture |
| KR100577015B1 (en) * | 2003-07-29 | 2006-05-10 | 매그나칩 반도체 유한회사 | Stacked chip package of the semiconductor device and method for manufacturing thereof |
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