JPH1050915A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH1050915A JPH1050915A JP8207027A JP20702796A JPH1050915A JP H1050915 A JPH1050915 A JP H1050915A JP 8207027 A JP8207027 A JP 8207027A JP 20702796 A JP20702796 A JP 20702796A JP H1050915 A JPH1050915 A JP H1050915A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- palladium layer
- layer
- soldering
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、端子が半田付けによって配線
基板に実装される半導体装置に適用して有効な技術に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a technique effective when applied to a semiconductor device in which terminals are mounted on a wiring board by soldering.
【０００２】[0002]
【従来の技術】半導体装置の代表として知られているＬ
ＳＩは、パーソナルコンピュータ（パソコン）、ワード
プロセッサ（ワープロ）などを初めとする各種電子機器
に広範囲に使用されている。このＬＳＩを各種電子機器
に組み込むにあたっては、ＬＳＩのパッケージから取り
出されているボール状の端子、あるいはピン状の端子を
半田付けによって配線基板に実装することが行われる。2. Description of the Related Art L which is known as a representative of a semiconductor device
SI is widely used in various electronic devices such as personal computers (personal computers) and word processors (word processors). When incorporating this LSI into various electronic devices, a ball-shaped terminal or a pin-shaped terminal taken out of a package of the LSI is mounted on a wiring board by soldering.
【０００３】ボール状の端子が取り出されているパッケ
ージはＢＧＡ（Ｂａｌｌ ＧｒｉｄＡｒｒａｙ）として
知られており、またピン状の端子が取り出されているパ
ッケージはＰＧＡ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）と
して知られ、両者は従来広く用いられているＱＦＰ（Ｑ
ｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）に比べて、配線基
板上に占める実装面積を小さくできることや、端子ピッ
チを拡大できるなどの利点を備えているので、軽量、小
型化を図る電子機器に好んで採用される傾向にある。A package from which a ball-shaped terminal is taken out is known as a BGA (Ball Grid Array), a package from which a pin-shaped terminal is taken out is known as a PGA (Pin Grid Array). QFP (Q
Compared with a flat board package, it has advantages such as a smaller mounting area on a wiring board and a larger terminal pitch. is there.
【０００４】ＢＧＡ構造を有するＬＳＩはボール状の端
子が配線基板上に半田付けされることにより実装され、
ＰＧＡ構造を有するＬＳＩはピン状の端子が配線基板内
に挿入されて半田付けされることにより実装される。An LSI having a BGA structure is mounted by soldering ball-shaped terminals on a wiring board.
An LSI having a PGA structure is mounted by inserting a pin-shaped terminal into a wiring board and soldering the terminal.
【０００５】ここで、ＢＧＡ構造を有するＬＳＩでは、
ボール状の端子としては半田（Ｐｂ−Ｓｎ）ボールが用
いられて、この半田ボールはパッケージから導電性パッ
ドを介して取り出されている。一方、ＰＧＡ構造を有す
るＬＳＩでは、ピン状の端子としては鉄−ニッケル（Ｆ
ｅ−Ｎｉ）系合金が用いられている。そして、各端子に
は実装時の半田濡れ性を向上するために、一般に金（Ａ
ｕ）めっきが施されている。すなわち、前者のＢＧＡ構
造では導電性パッドに対して金めっきが施されており、
後者のＰＧＡ構造ではピン状の端子に対して金めっきが
施されている。Here, in an LSI having a BGA structure,
A solder (Pb-Sn) ball is used as the ball-shaped terminal, and the solder ball is taken out of the package via a conductive pad. On the other hand, in an LSI having a PGA structure, iron-nickel (F
e-Ni) alloy is used. Generally, gold (A) is applied to each terminal in order to improve solder wettability during mounting.
u) Plating is applied. That is, in the former BGA structure, the conductive pad is plated with gold,
In the latter PGA structure, gold plating is applied to pin-shaped terminals.
【０００６】また、金めっきは半導体チップのパッド電
極とワイヤボンディングを行うリードのインナーリード
に対しても施されて、ボンディング性の向上や腐食防止
が図られている。Gold plating is also applied to inner leads of leads for performing wire bonding with pad electrodes of a semiconductor chip to improve bonding properties and prevent corrosion.
【０００７】[0007]
【発明が解決しようとする課題】前記のような従来の半
導体装置では、配線基板に実装後に端子の接続強度が劣
化するので、信頼性が低下するという問題がある。The conventional semiconductor device as described above has a problem that the connection strength of the terminals is deteriorated after mounting on the wiring board, so that the reliability is lowered.
【０００８】たとえば、ＢＧＡ構造では、導電性パッド
に半田ボールが溶融して実装後に半田ボールに金が拡散
するので、金と鉛または錫との合金ができてしまうた
め、接続強度が劣化するようになる。同様にして、ＰＧ
Ａ構造においても、実装時に用いる半田に金が拡散する
ので、同様な不都合が生ずる。For example, in the BGA structure, since the solder balls are melted on the conductive pads and gold is diffused into the solder balls after mounting, an alloy of gold and lead or tin is formed, so that the connection strength is deteriorated. become. Similarly, PG
In the case of the structure A, the same inconvenience occurs because gold diffuses into the solder used for mounting.
【０００９】また、従来の半導体装置では、パッケージ
の材料としてコスト的に優れている樹脂を用いた場合
は、この樹脂と金との接着力が弱いので、信頼性が低下
するという問題がある。Further, in the conventional semiconductor device, when a resin which is excellent in cost is used as a material of the package, there is a problem that the adhesive strength between the resin and gold is weak, so that the reliability is reduced.
【００１０】本発明の目的は、端子を半田付けによって
配線基板に実装する場合、半田濡れ性に優れた材料とし
て金を用いないことで、信頼性を向上することが可能な
技術を提供することにある。An object of the present invention is to provide a technique capable of improving reliability by not using gold as a material having excellent solder wettability when terminals are mounted on a wiring board by soldering. It is in.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１３】（１）本発明の半導体装置は、端子が半田
付けによって配線基板に実装される半導体装置であっ
て、前記端子にパラジュウム層が形成されている。(1) A semiconductor device according to the present invention is a semiconductor device in which terminals are mounted on a wiring board by soldering, and a palladium layer is formed on the terminals.
【００１４】（２）本発明の半導体装置は、パッケージ
から導電性パッドを介して取り出される端子が半田ボー
ルからなり半田付けによって配線基板に実装される半導
体装置であって、前記導電性パッドにパラジュウム層が
形成されている。(2) A semiconductor device according to the present invention is a semiconductor device in which terminals taken out of a package via conductive pads are formed of solder balls and mounted on a wiring board by soldering. A layer is formed.
【００１５】（３）本発明の半導体装置の製造方法は、
半導体チップのパッド電極とワイヤボンディングされる
べきインナーリードが露出され他の部分のリードが絶縁
被覆されたベース基板を用意する工程と、前記ベース基
板のインナーリードの周囲部にスルーホールを形成する
工程と、前記スルーホール内及びスルーホール表面に前
記インナーリードを含むリードと導通する配線層を形成
する工程と、前記スルーホール表面及びインナーリード
上の前記配線層に同時にパラジュウム層を形成する工程
とを含んでいる。(3) The method of manufacturing a semiconductor device according to the present invention
A step of preparing a base substrate in which inner leads to be wire-bonded to the pad electrodes of the semiconductor chip are exposed and other parts of the leads are insulated and covered; and a step of forming a through hole around the inner leads of the base substrate And forming a wiring layer in the through-hole and on the surface of the through-hole that is electrically connected to the lead including the inner lead, and forming a palladium layer on the surface of the through-hole and the wiring layer on the inner lead at the same time. Contains.
【００１６】上述した（１）の手段によれば、本発明の
半導体装置は、配線基板に半田付けされる端子にパラジ
ュウム層が形成されているので、パラジュウム層は半田
との合金が作りにくい。従って、端子を半田付けによっ
て配線基板に実装する場合、半田濡れ性に優れた材料と
して金を用いないことで、信頼性を向上することが可能
となる。According to the above-mentioned means (1), in the semiconductor device of the present invention, since the palladium layer is formed on the terminal to be soldered to the wiring board, it is difficult for the palladium layer to form an alloy with solder. Therefore, when terminals are mounted on a wiring board by soldering, reliability can be improved by not using gold as a material having excellent solder wettability.
【００１７】上述した（２）の手段によれば、本発明の
半導体装置は、パッケージから導電性パッドを介して取
り出される半田ボールからなる端子にパラジュウム層が
形成されており、パラジュウム層は半田との合金を作り
にくい。従って、端子を半田付けによって配線基板に実
装する場合、半田濡れ性に優れた材料として金を用いな
いことで、信頼性を向上することが可能となる。According to the above-mentioned means (2), in the semiconductor device of the present invention, a palladium layer is formed on a terminal made of a solder ball taken out from a package via a conductive pad, and the palladium layer is formed of a solder. Hard to make alloy. Therefore, when terminals are mounted on a wiring board by soldering, reliability can be improved by not using gold as a material having excellent solder wettability.
【００１８】上述した（３）の手段によれば、本発明の
半導体装置の製造方法は、まず、半導体チップのパッド
電極とワイヤボンディングされるべきインナーリードが
露出され他の部分のリードが絶縁被覆されたベース基板
を用意して、このベース基板のインナーリードの周囲部
にスルーホールを形成する。次に、スルーホール内及び
スルーホール表面にインナーリードを含むリードと導通
する配線層を形成する。続いて、スルーホール表面及び
インナーリード上の配線層に同時にパラジュウム層を形
成する。これによって、配線基板に半田付けされる端子
にパラジュウム層が形成されるので、端子を半田付けに
よって配線基板に実装する場合、半田濡れ性に優れた材
料として金を用いないことで、信頼性を向上することが
可能となる。According to the above-mentioned means (3), in the method of manufacturing a semiconductor device according to the present invention, first, the inner leads to be wire-bonded to the pad electrodes of the semiconductor chip are exposed, and the other leads are insulated. The prepared base substrate is prepared, and a through hole is formed around the inner lead of the base substrate. Next, a wiring layer is formed in the through-hole and on the surface of the through-hole to be electrically connected to the lead including the inner lead. Subsequently, a palladium layer is simultaneously formed on the surface of the through hole and the wiring layer on the inner lead. As a result, a palladium layer is formed on the terminals to be soldered to the wiring board, and when the terminals are mounted on the wiring board by soldering, the reliability is improved by not using gold as a material having excellent solder wettability. It is possible to improve.
【００１９】以下、本発明について、図面を参照して実
施形態とともに詳細に説明する。Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.
【００２０】なお、実施形態を説明するための全図にお
いて、同一機能を有するものは同一符号を付け、その繰
り返しの説明は省略する。In all the drawings for describing the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
【００２１】[0021]
（実施形態１）図１は本発明の実施形態１による半導体
装置を示す断面図である。本実施形態１の半導体装置１
は、例えばガラスエポキシ樹脂、セラミックスなどの絶
縁性材料からなるベース基板２にキャビティ３が形成さ
れて、このキャビティ３には例えば厚さ約２０μｍの銅
層からなるリード４のインナーリード４ａが露出されて
いる。ベース基板２の実装面（図１で上面）及びインナ
ーリード４ａには互いに導通する導電性パッド５が形成
されている。(Embodiment 1) FIG. 1 is a sectional view showing a semiconductor device according to Embodiment 1 of the present invention. Semiconductor device 1 of the first embodiment
In the first embodiment, a cavity 3 is formed in a base substrate 2 made of an insulating material such as a glass epoxy resin or a ceramic, and an inner lead 4a of a lead 4 made of a copper layer having a thickness of about 20 μm is exposed in the cavity 3. ing. Conductive pads 5 that are electrically connected to each other are formed on the mounting surface (the upper surface in FIG. 1) of the base substrate 2 and the inner leads 4a.
【００２２】図２は導電性パッド５の拡大構造を示すも
ので、この導電性パッド５は、例えばベース基板２にプ
リント基板製造技術によって形成された厚さ約２０μｍ
の銅（Ｃｕ）層６、厚さ約１〜５μｍのニッケル（Ｎ
ｉ）層７、厚さ約０．５〜１．５μｍのパラジュウム
（Ｐｄ）層８が順次に積層されている。図１に示した導
電性パッド５の各層の厚さは説明を理解し易くするため
に概略的に示している。FIG. 2 shows an enlarged structure of the conductive pad 5. The conductive pad 5 is formed on the base substrate 2 by a printed circuit board manufacturing technique and has a thickness of about 20 μm.
Copper (Cu) layer 6 and nickel (N
i) A layer 7 and a palladium (Pd) layer 8 having a thickness of about 0.5 to 1.5 μm are sequentially laminated. The thickness of each layer of the conductive pad 5 shown in FIG. 1 is schematically shown for easy understanding of the description.
【００２３】パラジュウム層８は従来の金層の代わり
に、半田濡れ性に優れた導電材料として用いられて、後
述するようにベース基板２の実装面及びインナーリード
４ａに同時にめっき法によって形成される。ニッケル層
７は銅層６にパラジュウム層８をめっきするための中間
材料として用いられている。The palladium layer 8 is used instead of a conventional gold layer as a conductive material having excellent solder wettability, and is simultaneously formed on the mounting surface of the base substrate 2 and the inner leads 4a by plating, as will be described later. . The nickel layer 7 is used as an intermediate material for plating the palladium layer 8 on the copper layer 6.
【００２４】ベース基板２の実装面には導電性パッド５
を介して半田（Ｐｂ−Ｓｎ合金）ボールからなる端子９
が取り出されている。この半田ボールは、目的に応じて
種々の成分比のものが使用可能である。一例として、Ｐ
ｂ９８％：Ｓｎ２％（融点約３２０〜３２６℃）のもの
が用いられる。A conductive pad 5 is provided on the mounting surface of the base substrate 2.
Via solder (Pb-Sn alloy) ball through terminal 9
Has been taken out. The solder balls having various component ratios can be used according to the purpose. As an example, P
b98%: Sn2% (melting point: about 320 to 326 ° C.) is used.
【００２５】ベース基板２のキャビティ３内には半導体
チップ１０が接着剤を介してボンディングされて、この
半導体チップ１０のパッド電極１１とインナーリード４
ａの導電性パッド５の最上層であるパラジュウム層８と
の間には、金線からなるワイヤ１２がボンディングされ
ている。そして、キャビティ３内には例えばエポキシ樹
脂からなる樹脂体１３が形成されて半導体チップ１３が
封止されている。ベース基板２、樹脂体１３はパッケー
ジ１４を構成している。A semiconductor chip 10 is bonded in the cavity 3 of the base substrate 2 via an adhesive, and the pad electrodes 11 of the semiconductor chip 10 and the inner leads 4 are bonded.
A wire 12 made of a gold wire is bonded between the conductive layer 5a and the palladium layer 8, which is the uppermost layer of the conductive pad 5a. A resin body 13 made of, for example, an epoxy resin is formed in the cavity 3 to seal the semiconductor chip 13. The base substrate 2 and the resin body 13 constitute a package 14.
【００２６】導電性パッド５の最上層を構成しているパ
ラジュウム層８は従来の金層と同様に半田濡れ性に優れ
ているだけでなく、実装後に半田ボールからなる端子９
に拡散しにくいので、鉛または錫との合金ができにく
い。さらに、パラジュウム層８は金ワイヤ１２とのボン
ディング性に優れた性質を備え、さらにまた、パラジュ
ウム層８は表面が僅かであるが酸化されるので、樹脂体
１３となじみ易くなるため樹脂との接着性が強くなる。The palladium layer 8 constituting the uppermost layer of the conductive pad 5 has not only excellent solder wettability like the conventional gold layer but also a terminal 9 made of a solder ball after mounting.
Alloys with lead or tin are difficult to form. Furthermore, the palladium layer 8 has a property excellent in bonding property with the gold wire 12, and the palladium layer 8 is slightly oxidized although its surface is slightly oxidized. Becomes stronger.
【００２７】次に、図面を参照して、本実施形態１の半
導体装置の製造方法を工程順に説明する。Next, a method of manufacturing the semiconductor device according to the first embodiment will be described in the order of steps with reference to the drawings.
【００２８】まず、図３に示すように、半導体チップの
パッド電極とワイヤボンディングされるべきインナーリ
ード４ａがキャビティ３に露出され他の部分のリード４
が絶縁被覆されたベース基板２を用意する。インナーリ
ード４ａを含むリード４はプリント基板製造技術によっ
て形成された銅層から構成されている。ベース基板２は
例えばガラスエポキシ樹脂、セラミックスなどの絶縁性
材料からなり、周知の積層技術、焼結技術などによって
製造される。First, as shown in FIG. 3, an inner lead 4a to be wire-bonded to a pad electrode of a semiconductor chip is exposed to a cavity 3 and leads 4 in other portions are exposed.
Is prepared. The leads 4 including the inner leads 4a are made of a copper layer formed by a printed circuit board manufacturing technique. The base substrate 2 is made of, for example, an insulating material such as glass epoxy resin or ceramics, and is manufactured by a well-known laminating technique, sintering technique, or the like.
【００２９】次に、図４に示すように、ベース基板２の
インナーリード４ａの周囲部に直径約０．４〜０．５μ
ｍのスルーホール１５を形成する。このスルーホール１
５によって、ベース基板２内に形成されているリード４
は部分的にカットされる。Next, as shown in FIG. 4, a diameter of about 0.4 to 0.5 μm is applied around the inner leads 4 a of the base substrate 2.
m through holes 15 are formed. This through hole 1
5, lead 4 formed in base substrate 2
Is partially cut.
【００３０】続いて、図５に示すように、ベース基板２
に対して無電解めっき処理を施してスルーホール１５内
及びスルーホール１５表面にリード４に導通するように
厚さ約１〜５μｍの銅層６を形成する。引き続いて、こ
の銅層６を電流通路として電解めっき処理を施して、銅
層６の厚さを約２０μｍ程度に増加させる。次に、電解
めっき処理を施して、銅層６上に厚さ約１〜５μｍのニ
ッケル層７を形成する。続いて、電解めっき処理を施し
て、ニッケル層７上に厚さ約０．５〜１．５μｍのパラ
ジュウム層８を形成する。以上のような処理によって、
図６に示すように、ベース基板２の実装面及びインナー
リード４ａに同時に導電性パッド５が形成される。Subsequently, as shown in FIG.
Then, a copper layer 6 having a thickness of about 1 to 5 μm is formed in the through-hole 15 and on the surface of the through-hole 15 so as to be electrically connected to the lead 4. Subsequently, an electrolytic plating process is performed using the copper layer 6 as a current path to increase the thickness of the copper layer 6 to about 20 μm. Next, an electrolytic plating process is performed to form a nickel layer 7 having a thickness of about 1 to 5 μm on the copper layer 6. Subsequently, an electrolytic plating process is performed to form a palladium layer 8 having a thickness of about 0.5 to 1.5 μm on the nickel layer 7. By the above processing,
As shown in FIG. 6, the conductive pads 5 are simultaneously formed on the mounting surface of the base substrate 2 and the inner leads 4a.
【００３１】次に、図７に示すように、半導体チップ１
０をベース基板２のキャビティ３の中央部に接着剤を介
してボンディングした後、この半導体チップ１０のパッ
ド電極１１とインナーリード４ａの導電性パッド５の最
上層であるパラジュウム層８との間に、金線からなるワ
イヤ１２をボンディングする。Next, as shown in FIG.
0 is bonded to the center of the cavity 3 of the base substrate 2 via an adhesive, and then between the pad electrode 11 of the semiconductor chip 10 and the palladium layer 8 which is the uppermost layer of the conductive pad 5 of the inner lead 4a. Then, the wire 12 made of a gold wire is bonded.
【００３２】続いて、図８に示すように、ベース基板２
のキャビティ３内に例えばエポキシ樹脂からなる樹脂を
ポッティング（充填）した後、熱硬化処理を施して、樹
脂体１３を形成して半導体チップ１０を封止する。Subsequently, as shown in FIG.
After potting (filling) a resin made of, for example, an epoxy resin into the cavity 3, a thermosetting treatment is performed to form a resin body 13 and seal the semiconductor chip 10.
【００３３】次に、図９に示すように、予め用意した半
田ボールからなる端子９を各導電性パッド５上に矢印の
ように位置決めした後、ベース基板２をリフロー炉を通
過させてその融点（例えば前記したような３２０℃）以
上に加熱処理して、半田ボールを溶融させて導電性パッ
ド５に接続する。Next, as shown in FIG. 9, after a terminal 9 made of a solder ball prepared in advance is positioned on each conductive pad 5 as shown by an arrow, the base substrate 2 is passed through a reflow furnace to obtain a melting point. (For example, at 320 ° C. as described above) or more, the solder balls are melted and connected to the conductive pads 5.
【００３４】以上の各工程によって、図１に示したよう
な半導体装置１が組立てられる。この半導体装置１は端
子９が配線基板に半田付けによって実装されることによ
り、各種電子機器に組み込まれる。Through the above steps, the semiconductor device 1 as shown in FIG. 1 is assembled. The semiconductor device 1 is incorporated in various electronic devices by mounting the terminals 9 on a wiring board by soldering.
【００３５】以上のような実施形態１によれば次のよう
な効果が得られる。According to the first embodiment, the following effects can be obtained.
【００３６】（１）半田ボールからなる端子９が接続さ
れる導電性パッド５の最上層にパラジュウム層８が形成
されており、実装後にパラジュウム層５は半田ボールに
拡散しにくいので、鉛または錫との合金ができにくくな
る。これにより、端子９の接続強度が向上する。従っ
て、端子を半田付けによって配線基板に実装する場合、
半田濡れ性に優れた材料として金を用いないことで、信
頼性を向上することが可能となる。(1) The palladium layer 8 is formed on the uppermost layer of the conductive pad 5 to which the terminal 9 made of a solder ball is connected. Since the palladium layer 5 hardly diffuses into the solder ball after mounting, the lead or tin is used. Alloys with the alloy become difficult. Thereby, the connection strength of the terminal 9 is improved. Therefore, when mounting the terminals on the wiring board by soldering,
By not using gold as a material having excellent solder wettability, reliability can be improved.
【００３７】（２）パラジュウム層８の表面に酸化膜を
形成できるので、樹脂との接着性を強めることができる
ため、信頼性を向上することが可能となる。(2) Since an oxide film can be formed on the surface of the palladium layer 8, the adhesiveness with the resin can be enhanced, and the reliability can be improved.
【００３８】（実施形態２）図１０は本発明の実施形態
２による半導体装置を示す断面図である。本実施形態２
の半導体装置１は、実施形態１による半導体装置１に比
較して、特に熱放散性の改善を図った例を示すものであ
る。(Embodiment 2) FIG. 10 is a sectional view showing a semiconductor device according to Embodiment 2 of the present invention. Embodiment 2
The semiconductor device 1 of the present embodiment shows an example in which heat dissipation is particularly improved as compared with the semiconductor device 1 according to the first embodiment.
【００３９】ベース基板２のキャビティ３内の中央部に
は例えば銅のような熱放散性に優れた熱拡散板１６が配
置されて、この熱拡散板１６の表面にも図２に示したよ
うな導電性パッド５が形成されている。そして、半導体
チップ１０は導電性パッド５の最上層であるパラジュウ
ム層８上にボンディングされている。At the center of the base substrate 2 in the cavity 3, a heat diffusion plate 16 such as copper, which has excellent heat dissipation, is disposed. The surface of the heat diffusion plate 16 is also shown in FIG. Conductive pad 5 is formed. The semiconductor chip 10 is bonded on the palladium layer 8, which is the uppermost layer of the conductive pad 5.
【００４０】この導電性パッド５の形成方法は、実施形
態１における半導体装置の製造方法と同様にして、電解
めっき処理を利用することができる。ただし、インナー
リード４ａにおける導電性パッド５とは絶縁されてい
る。The method for forming the conductive pad 5 can utilize electrolytic plating in the same manner as in the method for manufacturing a semiconductor device in the first embodiment. However, it is insulated from the conductive pad 5 in the inner lead 4a.
【００４１】以上のような本実施形態２によれば、実施
形態１と同様な効果が得られる他に、ベース基板２の一
部に熱拡散板１６を配置したことにより、特に熱放散性
を改善できるという効果が得られる。According to the second embodiment described above, the same effect as that of the first embodiment can be obtained. In addition, since the heat diffusion plate 16 is arranged in a part of the base substrate 2, the heat dissipation is particularly improved. The effect of improvement can be obtained.
【００４２】（実施形態３）図１１は本発明の実施形態
３による半導体装置を示す断面図で、ＰＧＡ構造を有す
るＬＳＩに適用した例を示すものである。(Embodiment 3) FIG. 11 is a sectional view showing a semiconductor device according to Embodiment 3 of the present invention, and shows an example in which the present invention is applied to an LSI having a PGA structure.
【００４３】インナーリード４ａには導電性パッド５が
形成されて、この最上層であるパラジュウム層８には金
ワイヤ１２がボンディングされている。また、ベース基
板２の実装面には例えば鉄−ニッケル合金からなるピン
状の端子１７が導電性接着剤を介して取り出されて、こ
の端子１７にはパラジュウム層８が形成されている。A conductive pad 5 is formed on the inner lead 4a, and a gold wire 12 is bonded to the uppermost palladium layer 8. Further, a pin-shaped terminal 17 made of, for example, an iron-nickel alloy is taken out from the mounting surface of the base substrate 2 via a conductive adhesive, and the terminal 17 is formed with a palladium layer 8.
【００４４】各パラジュウム層８の形成方法は、実施形
態１あるいは２と同様にして、電解めっき処理を利用し
て行うことができる。The method for forming each palladium layer 8 can be carried out by using an electrolytic plating process in the same manner as in the first or second embodiment.
【００４５】以上のような本実施形態３によれば、実施
形態１と比較して、パッケージの構造が異なるだけで他
の構造は同じなので、実施形態１と同様な効果を得るこ
とができる。According to the third embodiment, as compared with the first embodiment, only the structure of the package is different, and the other structures are the same. Therefore, the same effects as those of the first embodiment can be obtained.
【００４６】なお、各パラジュウム層８を酸化したまま
にしておくと、ＬＳＩを電子機器に組み込むために配線
基板に半田付けする際に、酸化膜の存在により付き具合
が悪くなる。このため、例えばアルゴンガスの雰囲気内
でスパッタ処理を施すと、その酸化膜を除去することが
できる。従って、半田付け処理の直前にそのようなスパ
ッタ処理を施すと、酸化膜が除去されて半田濡れ性が向
上させることができる。If each of the palladium layers 8 is left oxidized, the soldering of the LSI to a wiring board in order to incorporate the LSI into an electronic device may deteriorate the presence of the oxide film. Therefore, for example, when the sputtering process is performed in an atmosphere of an argon gas, the oxide film can be removed. Therefore, if such a sputtering process is performed immediately before the soldering process, the oxide film is removed and the solder wettability can be improved.
【００４７】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.
【００４８】例えば、前記実施形態では、ベース基板の
実装面及びインナーリードに同時にパラジュウム層を形
成した例を示したが、特に端子の接続強度を向上するこ
とを目的とするなら、端子を接続する実装面のみに導電
性パッドを形成するようにしても良い。For example, in the above embodiment, an example was shown in which the palladium layer was formed simultaneously on the mounting surface of the base substrate and the inner leads. However, if the purpose is to improve the connection strength of the terminals, the terminals are connected. A conductive pad may be formed only on the mounting surface.
【００４９】また、半導体チップを封止するために用い
る樹脂としては、エポキシ樹脂以外にも、ポリイミド樹
脂、フェノール樹脂、シリコーン樹脂などの他の樹脂を
用いる場合にも同様に適用可能である。The resin used for sealing the semiconductor chip can be similarly applied to the case where other resins such as a polyimide resin, a phenol resin and a silicone resin are used in addition to the epoxy resin.
【００５０】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野であるＬＳＩ
に適用した場合について説明したが、それに限定される
ものではない。本発明は、少なくとも回路部品を半田付
けによって配線基板に実装することを条件とするものに
は適用できる。In the above description, the invention made mainly by the present inventor has been described in the field of application of LSI
Has been described, but the present invention is not limited to this. The present invention can be applied to a device that requires at least a circuit component to be mounted on a wiring board by soldering.
【００５１】[0051]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００５２】（１）配線基板に半田付けされる端子にパ
ラジュウム層が形成されているので、実装後にパラジュ
ウム層は半田との合金ができにくいため、端子の接続強
度が向上する。従って、端子を半田付けによって配線基
板に実装する場合、半田濡れ性に優れた材料として金を
用いないことで、信頼性を向上することが可能となる。(1) Since the palladium layer is formed on the terminal to be soldered to the wiring board, the palladium layer hardly alloys with the solder after mounting, so that the connection strength of the terminal is improved. Therefore, when terminals are mounted on a wiring board by soldering, reliability can be improved by not using gold as a material having excellent solder wettability.
【００５３】（２）パラジュウム層の表面に酸化膜を形
成できるので、樹脂との接着性を強めることができるた
め、信頼性を向上することが可能となる。(2) Since an oxide film can be formed on the surface of the palladium layer, the adhesiveness with the resin can be strengthened, and the reliability can be improved.
【図１】本発明の実施形態１による半導体装置を示す断
面図である。FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.
【図２】図１の主要部の拡大構造を示す断面図である。FIG. 2 is a sectional view showing an enlarged structure of a main part of FIG.
【図３】本発明の実施形態１による半導体装置の製造方
法の一工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図４】本発明の実施形態１による半導体装置の製造方
法の他の工程を示す断面図である。FIG. 4 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図５】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 5 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図６】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 6 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図７】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 7 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図８】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 8 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図９】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 9 is a cross-sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図１０】本発明の実施形態２による半導体装置を示す
断面図である。FIG. 10 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図１１】本発明の実施形態３による半導体装置を示す
断面図である。FIG. 11 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
１…半導体装置、２…ベース基板、３…キャビティ、４
…リード、４ａ…インナーリード、５…導電性パッド、
６…銅層、７…ニッケル層、８…パラジュウム層、９…
ボール状の端子、１０…半田チップ、１１…パッド電
極、１２…金ワイヤ、１３…樹脂体、１４…パッケー
ジ、１５…スルーホール、１６…熱拡散板、１７…ピン
状の端子。DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Base substrate, 3 ... Cavity, 4
... Leads, 4a ... inner leads, 5 ... conductive pads,
6 ... copper layer, 7 ... nickel layer, 8 ... palladium layer, 9 ...
Ball-shaped terminal, 10: solder chip, 11: pad electrode, 12: gold wire, 13: resin body, 14: package, 15: through hole, 16: heat diffusion plate, 17: pin-shaped terminal.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 白石 智宏 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 黒田 宏 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 窪薗 実 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 白井 優之 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Tomohiro Shiraishi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Hiroshi Kuroda 2326, Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Ltd. (72) Inventor Minoru Kubozono 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd.Device Development Center, Hitachi, Ltd. (72) Inventor Yoshiyuki Shirai 2326 Imai, Ome-shi, Tokyo, Device Development Center, Hitachi, Ltd.
Claims (7)
される半導体装置であって、前記端子にパラジュウム層
が形成されたことを特徴とする半導体装置。1. A semiconductor device in which terminals are mounted on a wiring board by soldering, wherein a palladium layer is formed on the terminals.
り出される端子が半田ボールからなり半田付けによって
配線基板に実装される半導体装置であって、前記導電性
パッドにパラジュウム層が形成されたことを特徴とする
半導体装置。2. A semiconductor device in which terminals taken out of a package via conductive pads are solder balls and mounted on a wiring board by soldering, wherein a palladium layer is formed on the conductive pads. Semiconductor device.
ディングされるインナーリードにパラジュウム層が形成
されたことを特徴とする請求項１または２に記載の半導
体装置。3. The semiconductor device according to claim 1, wherein a palladium layer is formed on an inner lead wire-bonded to a pad electrode of the semiconductor chip.
散板にパラジュウム層が形成されたことを特徴とする請
求項１乃至３のいずれか１項に記載の半導体装置。4. The semiconductor device according to claim 1, wherein a palladium layer is formed on the heat diffusion plate to which the semiconductor chip is bonded.
ディングされるべきインナーリードが露出され他の部分
のリードが絶縁被覆されたベース基板を用意する工程
と、前記ベース基板のインナーリードの周囲部にスルー
ホールを形成する工程と、前記スルーホール内及びスル
ーホール表面に前記インナーリードを含むリードと導通
する配線層を形成する工程と、前記スルーホール表面及
びインナーリード上の前記配線層に同時にパラジュウム
層を形成する工程とを含むことを特徴とする半導体装置
の製造方法。5. A step of preparing a base substrate in which inner leads to be wire-bonded to pad electrodes of a semiconductor chip are exposed and other portions of the leads are insulated and covered, and a through hole is formed around the inner leads of the base substrate. A step of forming a hole, a step of forming a wiring layer in the through-hole and on the surface of the through-hole that is electrically connected to the lead including the inner lead, and simultaneously forming a palladium layer on the surface of the through-hole and the wiring layer on the inner lead. Forming a semiconductor device.
っき工程からなることを特徴とする請求項５に記載の半
導体装置の製造方法。6. The method according to claim 5, wherein the step of forming the palladium layer comprises a plating step.
端子にパラジュウム層を形成し、半田付け直前にスパッ
タ処理を施すことを特徴とする半導体装置の実装方法。7. A method for mounting a semiconductor device, comprising: forming a palladium layer on a terminal mounted on a wiring board by soldering; and performing a sputtering process immediately before soldering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8207027A JPH1050915A (en) | 1996-08-06 | 1996-08-06 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8207027A JPH1050915A (en) | 1996-08-06 | 1996-08-06 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1050915A true JPH1050915A (en) | 1998-02-20 |
Family
ID=16532998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8207027A Pending JPH1050915A (en) | 1996-08-06 | 1996-08-06 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1050915A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006024891A (en) * | 2004-06-10 | 2006-01-26 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method of the same |
| JP2007063042A (en) * | 2005-08-30 | 2007-03-15 | Hitachi Metals Ltd | Ceramic substrate and electronic component using it |
| JP2014022505A (en) * | 2012-07-17 | 2014-02-03 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
-
1996
- 1996-08-06 JP JP8207027A patent/JPH1050915A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006024891A (en) * | 2004-06-10 | 2006-01-26 | Sanyo Electric Co Ltd | Semiconductor device and manufacturing method of the same |
| JP4660259B2 (en) * | 2004-06-10 | 2011-03-30 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP2007063042A (en) * | 2005-08-30 | 2007-03-15 | Hitachi Metals Ltd | Ceramic substrate and electronic component using it |
| JP2014022505A (en) * | 2012-07-17 | 2014-02-03 | Renesas Electronics Corp | Semiconductor device and manufacturing method of the same |
| US9343395B2 (en) | 2012-07-17 | 2016-05-17 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of same |
| US9704805B2 (en) | 2012-07-17 | 2017-07-11 | Renesas Electronics Corporation | Semiconductor device and manufacturing method of same |
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