JP2943788B2 - Wiring board for mounting electronic components - Google Patents

Wiring board for mounting electronic components

Info

Publication number
JP2943788B2
JP2943788B2 JP10046382A JP4638298A JP2943788B2 JP 2943788 B2 JP2943788 B2 JP 2943788B2 JP 10046382 A JP10046382 A JP 10046382A JP 4638298 A JP4638298 A JP 4638298A JP 2943788 B2 JP2943788 B2 JP 2943788B2
Authority
JP
Japan
Prior art keywords
wiring board
hole
outer layer
bump
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10046382A
Other languages
Japanese (ja)
Other versions
JPH10340929A (en
Inventor
良治 杉浦
正幸 櫻井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP10046382A priority Critical patent/JP2943788B2/en
Publication of JPH10340929A publication Critical patent/JPH10340929A/en
Application granted granted Critical
Publication of JP2943788B2 publication Critical patent/JP2943788B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3478Applying solder preforms; Transferring prefabricated solder patterns

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電子部品を搭載す
るための電子部品搭載用配線基板であって、特にバンプ
を形成する電極パッドを有する電子部品搭載用配線基板
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting electronic components, and more particularly to a wiring board for mounting electronic components having electrode pads for forming bumps.

【0002】[0002]

【従来の技術】図3に基づいて従来の技術を説明する。
従来技術の電子部品搭載用の従来の配線基板31は、こ
の従来の配線基板31の上部表面に半導体回路部品、抵
抗、コンデンサあるいはモジュール部品などの電子部品
40をリフローはんだ付けをして表面面付実装するか、
または電子部品40と電子部品搭載面にある上面外層導
体33のボンディング・ランドにボンディング・ワイヤ
41で接続してワイヤ・ボンディング実装する。この電
子部品搭載面にある上面外層導体33とバンプ形成側の
下面外層導体35とは、スルーホール32のスルーホー
ルめっき層34で電気的に導通されている。 この下面
外層導体35の所定箇所の2次元の格子上交点に多数の
平面的な電極パッド36が設定配置されている。この電
子部品40を搭載する従来の配線基板31の外部へ接続
するための端子である平面的な電極パッド36の表面に
突出接点(以下、バンプと記す)を形成する。代表的な
バンプ45として、球形状のはんだボール45Aが一般
的に使用されているがその他に、たまご形状、半球形
状、長円球形状などのバンプ45も使用されている。前
記バンプ45を平面的な電極パッド36に取り付ける場
合、電極パッド36に接するバンプ45の先端面が球面
形状となっているため位置決めが非常に難しく問題とな
っている。
2. Description of the Related Art A conventional technique will be described with reference to FIG.
The conventional wiring board 31 for mounting the electronic parts of the prior art is formed by reflow soldering an electronic component 40 such as a semiconductor circuit component, a resistor, a capacitor or a module component on the upper surface of the conventional wiring board 31 to have a surface. Implement or
Alternatively, the electronic component 40 is connected to the bonding lands of the upper outer layer conductor 33 on the electronic component mounting surface by bonding wires 41 and mounted by wire bonding. The upper surface outer layer conductor 33 on the electronic component mounting surface and the lower surface outer layer conductor 35 on the bump formation side are electrically connected by the through-hole plating layer 34 of the through-hole 32. A large number of planar electrode pads 36 are set and arranged at predetermined two-dimensional grid intersections of the lower surface outer layer conductor 35. A protruding contact (hereinafter, referred to as a bump) is formed on the surface of the planar electrode pad 36 which is a terminal for connecting to the outside of the conventional wiring board 31 on which the electronic component 40 is mounted. As a typical bump 45, a spherical solder ball 45A is generally used, but in addition, a bump 45 having an egg shape, a hemispherical shape, an elliptical spherical shape, or the like is also used. When the bump 45 is attached to the planar electrode pad 36, positioning is very difficult because the tip surface of the bump 45 in contact with the electrode pad 36 has a spherical shape.

【0003】従来は、ICフラットパッケージ等の高密
度電子部品や電子部品を搭載したモジュール配線基板な
どの、いわゆる電子部品40を搭載した従来の配線基板
31の外部への接続端子と親配線基板(マザー・ボー
ド)22の接続用ランド26との接続には、導電性ペー
スト、例えばクリームはんだ28を用いたリフローはん
だ付けが利用されていたが、近年、ICフラットパッケ
ージ等の高密度化、小型化により接続端子数の増加、接
続端子間いわゆる端子ピッチ間隔が狭くなり、電子部品
40のリード端子径が細く、かつ変形しやすくなって従
来のはんだ付け技術の限界に直面し、はんだ付け不良率
が高くなっていた。
Conventionally, connection terminals to the outside of a conventional wiring board 31 on which a so-called electronic component 40 is mounted, such as a high-density electronic component such as an IC flat package and a module wiring board on which the electronic component is mounted, and a parent wiring board ( Reflow soldering using a conductive paste, for example, cream solder 28, has been used to connect the mother board 22 to the connection lands 26. In recent years, however, the density and size of IC flat packages and the like have been reduced. As a result, the number of connection terminals increases, so-called terminal pitch interval between the connection terminals becomes narrower, the lead terminal diameter of the electronic component 40 becomes thinner and easily deformed, and the limit of the conventional soldering technology is faced. Was higher.

【0004】そこで注目を集めている接続技術として、
電子部品40を搭載した従来の配線基板31の下面に外
部へ接続するための端子として多数の平面的な電極パッ
ド36に、はんだ等により形成された球形状のバンプ、
例えば、はんだボール45Aを2次元に配置しておい
て、このはんだボール45Aのバンプと親配線基板22
の接続用ランド26にクリームはんだ28を塗布した接
続端子群とを突き合わせてから、リフローはんだ付けに
より平面的な面付実装を行なうことが多くなっている。
球形状バンプを2次元に配置する方式はBGA(ball・
grid・array)パッケージ方式と呼び電子部品の高密度
化、小型化および、はんだ付け不良率の低減による品質
の向上が望める。
[0004] As a connection technology that has attracted attention,
A plurality of planar electrode pads 36 as terminals for external connection to the lower surface of the conventional wiring board 31 on which the electronic component 40 is mounted, spherical bumps formed by solder or the like,
For example, the solder balls 45A are two-dimensionally arranged, and the bumps of the solder balls 45A and the parent wiring board 22 are arranged.
In many cases, a flat surface mounting is performed by reflow soldering after abutting a connection terminal group coated with a cream solder 28 on the connection land 26.
The method of arranging spherical bumps in two dimensions is BGA (ball
It is called a “grid / array” package system, and it is expected that the quality of electronic components will be improved by increasing the density and miniaturizing them, and by reducing the defective soldering rate.

【0005】通常、ICフラットパッケージ等の高密度
化、小型化された電子部品40を従来の配線基板31に
実装する際、はんだ付け用のフラックスやはんだがスル
ーホールめっきの施こされているスルーホール32を通
じて電子部品40の搭載面に流出したり、また搭載した
電子部品40やボンディング・ワイヤ41をモールド樹
脂で被覆して保護する際にバンプ形成側へのモールド樹
脂の流出を防止するため、スルーホール32に充填物3
9を充填しなければならい。その後、外層導体表面の必
要な接続ランドや電極パッド36以外にはソルダーレジ
スト17を施すことが一般的である。
[0005] Usually, when mounting a high-density and miniaturized electronic component 40 such as an IC flat package on a conventional wiring board 31, a flux or solder for soldering is applied through-hole plating. In order to prevent the mold resin from flowing to the mounting surface of the electronic component 40 through the hole 32 and to prevent the molded resin from flowing to the bump formation side when the mounted electronic component 40 and the bonding wires 41 are covered with the mold resin and protected. Filling material 3 in through hole 32
9 must be filled. After that, it is common to apply a solder resist 17 to portions other than necessary connection lands and electrode pads 36 on the outer conductor surface.

【0006】[0006]

【発明が解決しようとする課題】しかしながら従来のB
GAパッケージ方式の一体化された電子部品搭載用配線
基板では球形状のバンプ45を2次元の格子上交点に平
面的に設定された電極パッド36に取り付ける場合、電
極パッド36に接するバンプ45の先端面が球面形状と
なっているため位置決めが非常に難しくなっている。さ
らに、球形状のバンプ45を従来の配線基板31の所定
箇所に2次元に配置されている平面的な電極パッド36
に正確に位置決めをし、固定する必要があるだけでな
く、バンプ45の先端面の高さのバラツキやバンプを形
成するはんだの量の多少で、親配線基板22の接続用ラ
ンド26へリフローはんだ付けする際に隣接バンプ45
または接続用ランド26とショートしたり、従来の配線
基板31に形成されているバンプ45と接続用ランド2
6のクリームはんだ28との接続不良が生じたり、球形
状のバンプ45を用いた平面的な面付接続による接続技
術は接続信頼性の確保が課題となっている。また、電子
部品40を従来の配線基板31に実装する際、はんだ付
け用のフラックス、はんだがスルーホール32を通じて
電子部品40の搭載面に流出したり、搭載した電子部品
40やボンディング・ワイヤ41をモールド樹脂で被覆
して保護する際にバンプ45形成側へのモールド樹脂の
流出を防止するため、スルーホール32に充填物39を
充填しなければならず、生産効率の低下となっている。
However, the conventional B
In the case of mounting a spherical bump 45 on an electrode pad 36 which is set two-dimensionally at an intersection on a two-dimensional grid in the integrated electronic component mounting wiring board of the GA package system, the tip of the bump 45 in contact with the electrode pad 36 Positioning is very difficult because the surface is spherical. Further, the spherical bumps 45 are formed on the planar electrode pads 36 two-dimensionally arranged at predetermined positions on the conventional wiring board 31.
In addition to the need for accurate positioning and fixing, the reflow soldering to the connection lands 26 of the parent wiring board 22 depends on the height of the bumps 45 and the amount of solder forming the bumps. When attaching, adjacent bump 45
Alternatively, the connection land 26 may be short-circuited or the bump 45 formed on the conventional wiring board 31 may be connected to the connection land 2.
In connection technology with the solder paste 28 of No. 6 or the connection technology by planar surface connection using the spherical bump 45, securing the connection reliability is an issue. When the electronic component 40 is mounted on the conventional wiring board 31, the flux and solder for soldering flow out to the mounting surface of the electronic component 40 through the through hole 32, and the mounted electronic component 40 and the bonding wire 41 are removed. In order to prevent the mold resin from flowing out to the side where the bumps 45 are formed when covering and protecting with the mold resin, it is necessary to fill the through hole 32 with the filling material 39, which reduces the production efficiency.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
本発明では、電子部品を搭載するための配線基板で外部
へ接続する端子にバンプを形成する配線基板において、
絶縁性基材を貫通する穴の一方の穴端面を塞ぐ上部表面
外層導体と、他方の開孔している穴端面の一部もしくは
全周に接して設けられた下部表面外層導体と、前記上部
表面外層導体と下部表面外層導体の両面の外層導体を電
気的に導通させる閉孔している非貫通穴内の導体層とを
備えた非貫通導通穴を有する配線基板において、絶縁性
基材の上部表面外層導体に電子部品をワイヤ・ボンディ
ング接続し、前記非貫通導通穴内には球形状のバンプを
取り付けるための外部接続用の凹形状の電極パッドする
電子部品搭載用配線基板とするものである。
According to the present invention, there is provided a wiring board for mounting electronic parts, wherein the wiring board has bumps formed on terminals to be connected to the outside.
An upper surface outer layer conductor that closes one end surface of a hole penetrating the insulating base material, a lower surface outer layer conductor provided in contact with a part or the entire circumference of the other open hole end surface; In a wiring board having a non-through conductive hole provided with a closed outer layer and a conductive layer in a closed non-through hole for electrically connecting outer surface conductors on both surfaces of the lower surface outer layer conductor and the lower surface outer layer conductor, An electronic component is connected to the outer surface conductor by wire bonding, and a concave electrode pad for external connection for mounting a spherical bump in the non-through conductive hole is used as an electronic component mounting wiring board.

【0008】前記の絶縁性基材の上部表面外層導体と下
部表面外層導体の両面の外層導体を電気的に導通させる
非貫通導通穴上の閉孔している上部表面外層導体を電子
部品をワイヤ・ボンディング接続するためのボンディン
グランドを形成する電子部品搭載用配線基板とするもの
である。
[0008] The electronic component is connected to a closed upper surface outer layer conductor on a non-through conductive hole for electrically connecting the outer surface conductors on both surfaces of the upper surface outer layer conductor and the lower surface outer layer conductor of the insulating substrate. A wiring board for mounting electronic components, which forms a bonding land for bonding connection.

【0009】両面配線基板,多層配線基板のいずれで
も、閉孔している非貫通穴内にメッキ法や蒸着法などで
導体層を形成し、電子部品搭載面にある上部表面外層導
体とバンプ形成側にある下部表面外層導体とを、非貫通
穴内の導体層で電気的に導通させて非貫通導通穴とし、
この非貫通導通穴内をバンプを形成するための電極パッ
ドとするものである。すなわち、配線基板の下部表面か
ら絶縁性基材側内部に、その表面中央部を凹形状に陥没
して形成し、球形状のバンプを凹形状の電極パッド内部
にはめ込むことにより、正しい電極パッド位置に容易に
位置決めをすることができる。また、凹形状の電極パッ
ド部は、電子部品搭載面の上部表面外層導体で穴の一方
の端面が塞がれているため従来の貫通スルーホール穴の
充填物による穴埋めを省略することが可能となる。
In both the double-sided wiring board and the multilayer wiring board, a conductor layer is formed in a closed non-through hole by a plating method or a vapor deposition method, and the upper surface outer layer conductor on the electronic component mounting surface and the bump forming side are formed. And the lower surface outer layer conductor is electrically conductive with the conductor layer in the non-through hole to form a non-through conductive hole,
The inside of the non-through conduction hole is used as an electrode pad for forming a bump. That is, by forming the center of the surface of the wiring substrate from the lower surface to the inside of the insulating base material in a concave shape, and fitting the spherical bump into the concave electrode pad, the correct electrode pad position is obtained. Can be easily positioned. In addition, since the concave electrode pad portion has one end face closed with an outer layer conductor on the upper surface of the electronic component mounting surface, it is possible to omit the filling of the conventional through-hole hole with the filling material. Become.

【0010】[0010]

【発明の実施の形態】以下、本発明の実施の形態を図に
基づいて説明する。まず、図1の本発明の電子部品搭載
状態の配線基板断面図において、ガラスエポキシ基材、
フェノール基材、合成樹脂基材、テフロン含有基材、ポ
リイミド樹脂基材、BTレジン(ビスマレィミド−トリ
アジン樹脂)基材、変性BTレジン基材またはセラミッ
ク等の絶縁性基材1の所定箇所にバンプを形成する側か
らレーザー加工をし、電子部品搭載面の上部表面外層導
体3に達する絶縁性基材1を貫通する穴7を設ける。次
に、めっきを施こし非貫通穴内の導体層4と、絶縁性基
材1の両方の表面の所定箇所には所定の電子部品搭載面
の上部表面外層導体3と、バンプ形成側の下部表面外層
導体5とを印刷法や写真法により形成し、電子部品搭載
面の上部表面外層導体3とバンプ形成側の下部表面外層
導体5との両面の外層導体を非貫通穴内の導体層4で従
来の貫通スルーホール穴と同様に両面の外層導体を電気
的に導通させる非貫通導通穴を形成する。上記に示すよ
うに形成された非貫通導通穴は、配線基板10の下部に
あるバンプ形成側の基板表面5Aから絶縁性基材1の内
部に、その箇所の表面中央部がへこんだ非貫通導通穴と
なる凹形状の電極パッド6を陥没して形成し、立体的
(3次元)な球形状のバンプ45を取り付ける外部接続
用の凹形状の電極パッドとするものである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. First, in the cross-sectional view of the wiring board in the electronic component mounted state of the present invention in FIG.
A bump is formed at a predetermined position on an insulating substrate 1 such as a phenolic substrate, a synthetic resin substrate, a Teflon-containing substrate, a polyimide resin substrate, a BT resin (bismaleimide-triazine resin) substrate, a modified BT resin substrate, or a ceramic. Laser processing is performed from the side to be formed, and a hole 7 penetrating the insulating base material 1 reaching the upper surface outer layer conductor 3 on the electronic component mounting surface is provided. Next, plating is applied to the conductor layer 4 in the non-through hole, the upper surface outer layer conductor 3 on a predetermined electronic component mounting surface at a predetermined location on both surfaces of the insulating substrate 1, and the lower surface on the bump formation side. The outer layer conductor 5 is formed by a printing method or a photographic method, and the outer layer conductors on both sides of the upper surface outer layer conductor 3 on the electronic component mounting surface and the lower surface outer layer conductor 5 on the bump forming side are conventionally formed by the conductor layer 4 in the non-through hole. A non-through conductive hole for electrically connecting the outer layer conductors on both sides is formed in the same manner as the through through hole. The non-through conduction hole formed as described above is a non-through conduction hole in which the center of the surface is dented from the substrate surface 5A on the bump formation side under the wiring substrate 10 to the inside of the insulating base material 1. A concave electrode pad 6 serving as a hole is formed by being depressed to form a concave electrode pad for external connection to which a three-dimensional (three-dimensional) spherical bump 45 is attached.

【0011】次に、配線基板10に形成されている凹形
状の電極パッド6の内部に、はんだ付用フラックスまた
は導電性ペースト8を塗布あるいは充填し、そこに球形
状のバンプ45をはめ込んだ状態で接着して仮固定をす
る。導電性ペースト8としては、銀ペースト、銅ペース
ト、はんだペースト、カーボンペースト、銀−銅の混合
ペースト、Sn−Ag−Cu系、Sn−Ag−Bi系の
ペーストなどがあるが一般的にはクリームはんだが使用
されている。なお、バンプ45の材質として金、銅、黄
銅、軟銅、はんだ、鋼球に金属めっきをしたもの、樹脂
に金属めっきをしたものなどが用いられる。
Next, a soldering flux or a conductive paste 8 is applied or filled into the concave electrode pads 6 formed on the wiring board 10, and spherical bumps 45 are fitted therein. And temporarily fix it. Examples of the conductive paste 8 include a silver paste, a copper paste, a solder paste, a carbon paste, a silver-copper mixed paste, a Sn-Ag-Cu-based paste, and a Sn-Ag-Bi-based paste. Solder is used. In addition, as a material of the bump 45, gold, copper, brass, soft copper, solder, a steel ball plated with metal, a resin plated with metal, or the like is used.

【0012】また、配線基板10の外部へ接続するため
の端子となるバンプ形成側にある下部表面外層導体5に
形成される凹形状の電極パッド6として配線基板下面に
ある開孔している穴端面の一部もしくは全周に接して表
面外層導体を設ける。しかし、高密度のパタ−ン設計を
する場合は、バンプ形成側にある下部表面外層導体5に
はバンプ形成用のランドを設けず、凹形状の非貫通穴の
内壁のみに非貫通穴内の導体層4を形成する、いわゆる
ランドレス形状とすることもできる。
Further, a hole formed in the lower surface of the wiring board as a concave electrode pad 6 formed on the lower surface outer layer conductor 5 on the bump forming side which is a terminal for connection to the outside of the wiring board 10. A surface outer layer conductor is provided in contact with a part or the entire circumference of the end face. However, when a high-density pattern is designed, the lower surface outer layer conductor 5 on the bump formation side is not provided with a land for bump formation, and the conductor in the non-through hole is provided only on the inner wall of the concave non-through hole. A so-called landless shape in which the layer 4 is formed can also be used.

【0013】配線基板10の上面には、抵抗、コンデン
サ、半導体回路部品、ICフラットパッケージあるいは
モジュール部品などの電子部品40を電子部品搭載面の
上部表面外層導体3の所定箇所にあるボンディングラン
ドにボンディング・ワイヤ41を介してワイヤ・ボンデ
ィング接続をする。特に、絶縁性基材1の上部表面外層
導体3と下部表面外層導体5の両面の外層導体を電気的
に導通させる非貫通導通穴上の閉孔している上部表面外
層導体3を電子部品をワイヤ・ボンディング接続するた
めのボンディングランドとすることにより電子部品搭載
用配線基板をより一層高密度化することができる。この
電子部品40の各電極端子と、配線基板10の所定箇所
に形成されている各接続ランドであるボンディングラン
ドとの接続はワイヤ・ボンディングだけに限らず導電性
ペ−スト8であるクリームはんだによる表面面付実装
や、あるいは溶接実装などでもよい。
On the upper surface of the wiring board 10, an electronic component 40 such as a resistor, a capacitor, a semiconductor circuit component, an IC flat package or a module component is bonded to a bonding land at a predetermined position on the upper surface outer layer conductor 3 on the electronic component mounting surface. -Wire bonding connection is performed via the wire 41. In particular, the upper surface outer layer conductor 3 closed on the non-through conduction hole for electrically connecting the outer surface conductors 3 on both surfaces of the upper surface outer layer conductor 3 and the lower surface outer layer conductor 5 of the insulating base material 1 to the electronic component. By using the bonding lands for wire bonding connection, the density of the wiring board for mounting electronic components can be further increased. The connection between the electrode terminals of the electronic component 40 and the bonding lands, which are connection lands formed at predetermined locations on the wiring board 10, is not limited to wire bonding, but can be achieved by cream solder, which is a conductive paste 8. Mounting with a surface or welding mounting may be used.

【0014】電子部品を搭載するための配線基板の外部
へ接続する端子にバンプを形成する配線基板10におい
て絶縁性基材1と、絶縁性基材を貫通する穴7と、絶縁
性基材を貫通する穴7の一方の穴端面を塞ぐ電子部品搭
載面の上部表面外層導体3と、閉孔している非貫通穴内
の導体層4とからなる非貫通導通穴である凹形状の電極
パッド6を有する電子部品搭載用配線基板とする。ま
た、この配線基板10には貫通孔は設けず非貫通穴とし
て、電子部品40を配線基板10に実装する際、はんだ
付け用のフラックスやはんだが貫通孔を通じて電子部品
40の搭載面に流出したり、搭載した電子部品40やボ
ンディング・ワイヤ41をモールド樹脂で被覆して保護
する際にバンプ45形成側へのモールド樹脂が流出する
ことを防止するものである。
In a wiring board 10 for forming a bump on a terminal connected to the outside of a wiring board for mounting an electronic component, an insulating base 1, a hole 7 penetrating the insulating base, and an insulating base A concave electrode pad 6 which is a non-through conductive hole composed of the upper surface outer layer conductor 3 of the electronic component mounting surface that closes one end face of the through hole 7 and the conductor layer 4 in the closed non-through hole. And a wiring board for mounting electronic components. In addition, when the electronic component 40 is mounted on the wiring board 10, when the electronic component 40 is mounted on the wiring substrate 10, flux or solder flows out to the mounting surface of the electronic component 40 through the through hole. Also, when the mounted electronic components 40 and the bonding wires 41 are covered with the mold resin and protected, the mold resin is prevented from flowing out to the bump 45 forming side.

【0015】本発明のバンプ45形成用の電極パッド
は、その表面中央部が凹形状に陥没しているため球形状
のバンプ45(はんだボール45A)を、その内部には
め込むことは簡単にでき、また凹形状の電極パッド6は
2次元の格子交点の正しい電極パッド位置に設定されて
いるので容易に位置決めをすることができる。さらに、
凹形状の電極パッド6の非貫通穴の内径は挿入する球形
状のバンプ45の外径Dより若干(0.05〜0.20
mm)大きくし、凹形状の電極パッド6の内径とバンプ
45の外径Dとの間隙を少なくして平面的な位置決め精
度を高くすることが出来る。
In the electrode pad for forming the bump 45 according to the present invention, the central portion of the surface is depressed in a concave shape, so that the spherical bump 45 (solder ball 45A) can be easily fitted into the inside thereof. In addition, since the concave electrode pad 6 is set at the correct electrode pad position at the two-dimensional grid intersection, it can be easily positioned. further,
The inner diameter of the non-through hole of the concave electrode pad 6 is slightly larger than the outer diameter D of the spherical bump 45 to be inserted (0.05 to 0.20).
mm), the gap between the inner diameter of the concave electrode pad 6 and the outer diameter D of the bump 45 can be reduced, and the planar positioning accuracy can be increased.

【0016】その次に、図2に基づいて本発明による球
形状のバンプ45を凹設する状態を説明する。配線基板
10の凹形状の電極パッド6の内部に導電性ペースト8
を塗布してから球形状バンプ45として例えば、球形状
のはんだボール45Aをはめ込み仮固定をした後、表面
がテフロン、セラミック、ガラスなどの非金属被膜で形
成されている平坦な治具47に球形状のはんだボール4
5Aの先端面が均一なレベルとなるように設定してリフ
ローはんだ付け等の熱処理によって、2次元に配置され
る多数の球形状のはんだボール45Aの突出する先端面
の高さが均一なレベルとなる。また、配線基板10のバ
ンプ形成側の基板表面5Aからバンプの先端面までの高
さHを均一にするため治具47には台座48を設け、配
線基板10の所定箇所を保持して熱処理を行なう。
Next, a state in which the spherical bump 45 according to the present invention is recessed will be described with reference to FIG. The conductive paste 8 is provided inside the concave electrode pads 6 of the wiring board 10.
After applying, for example, a spherical solder ball 45A is fitted as the spherical bump 45 and temporarily fixed, and then the ball is placed on a flat jig 47 whose surface is formed of a non-metallic coating such as Teflon, ceramic, or glass. Shaped solder ball 4
The height of the protruding tip surfaces of a large number of two-dimensionally arranged solder balls 45A two-dimensionally arranged by heat treatment such as reflow soldering is set so that the tip surfaces of 5A are set to a uniform level. Become. Also, a pedestal 48 is provided on the jig 47 to make the height H from the substrate surface 5A on the bump formation side of the wiring substrate 10 to the tip end surface of the bump uniform, and a predetermined portion of the wiring substrate 10 is held and heat treatment is performed. Do.

【0017】[0017]

【実施例】本発明における実施例として、配線基板10
は板厚0.2mmのBTレジン基材とし、BGAの端子
ピッチ1.0mmで2次元のマトリクス状に配列できる
凹形状の電極パッド6を短パルス炭酸ガスレーザーで穿
孔し、銅めっきを施こし非貫通導通穴とした。バンプ4
5として、球形状のはんだボール45Aの外径φ0.5
0mmを使用し、凹形状の電極パッド6の内径は0.5
5〜0.65mmとした。また、この凹形状の電極パッ
ド6の内部に、はんだボール45Aを仮固定する接着剤
として、はんだ付用フラックスを使用する場合には電極
パッド6の内径は0.55〜0.60mmが良く、クリ
ームはんだを使用する場合には0.60〜0.65mm
が良好であった。
DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, a wiring board 10 will be described.
Is a BT resin base material with a plate thickness of 0.2 mm, and a concave electrode pad 6 that can be arranged in a two-dimensional matrix at a BGA terminal pitch of 1.0 mm is perforated with a short pulse carbon dioxide laser and copper-plated. It was a non-through conduction hole. Bump 4
5, the outer diameter φ0.5 of the spherical solder ball 45A
The inner diameter of the concave electrode pad 6 is 0.5 mm.
5 to 0.65 mm. When a soldering flux is used as an adhesive for temporarily fixing the solder ball 45A inside the concave electrode pad 6, the inner diameter of the electrode pad 6 is preferably 0.55 to 0.60 mm. 0.60 to 0.65 mm when using cream solder
Was good.

【0018】[0018]

【発明の効果】以上、説明したように、従来の電子部品
を搭載した従来の配線基板の下面外層導体に形成されて
いる電極パッドは平面的で多数の球形状バンプを正確に
位置決めをし、さらに球形状バンプのバンプ形成側の基
板表面から先端面の高さまでのバラツキをなくして固定
することは非常に難しいが、本発明では、従来の平面的
な電極パッドを配線基板の表面から絶縁性基材側内部に
陥没して非貫通導通穴を形成し凹形状の電極パッドとす
ることにより凹形状の電極パッド内部に球形状バンプを
簡単にはめ込むことが可能となり、正しい電極パッド位
置に容易に位置決めをすることができる。
As described above, the electrode pads formed on the outer conductor on the lower surface of the conventional wiring board on which the conventional electronic components are mounted can accurately position a large number of spherical bumps in a plane. Furthermore, it is very difficult to fix the spherical bumps from the surface of the substrate on the bump forming side to the height of the front end surface, but in the present invention, the conventional flat electrode pads are electrically insulated from the surface of the wiring substrate. Depressed inside the base material side to form a non-through conduction hole to form a concave electrode pad, it is possible to easily fit a spherical bump inside the concave electrode pad, and easily to the correct electrode pad position Positioning can be done.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明を説明する電子部品搭載状態の配線基板
断面図。
FIG. 1 is a cross-sectional view of a wiring board in a state where electronic components are mounted, illustrating the invention.

【図2】本発明による球形状のバンプを凹設する状態を
示した断面図。
FIG. 2 is a sectional view showing a state where a spherical bump according to the present invention is recessed.

【図3】従来の電子部品搭載用の配線基板断面図。FIG. 3 is a cross-sectional view of a conventional wiring board for mounting electronic components.

【符号の説明】[Explanation of symbols]

1…絶縁性基材 3…上部表面外層導体 4…非貫通穴内
の導体層 5…下部表面外層導体 5A…バンプ形成側の基板表面 6…凹形状の電極パッド 7…絶縁性基材を貫通する穴 8…導電性ペースト 10…配線基板 17…ソルダーレジスト 22…親配線基板(マザーボ
ード) 26…接続用ランド 28…クリームはんだ 31…従来の配線基板 32…スルーホール 33…上面外層導体 34…スルーホールめっき層 35…下面外層導体 36…電極パッド 39…充填物 40…電子部品 41…ボンディング・ワ
イヤ 45…バンプ 45A…はんだボール 47…治具 48
…台座。
DESCRIPTION OF SYMBOLS 1 ... Insulating base material 3 ... Upper surface outer layer conductor 4 ... Conductor layer in a non-through hole 5 ... Lower surface outer layer conductor 5A ... Bump forming side substrate surface 6 ... Recessed electrode pad 7 ... Penetrate insulating base material Hole 8: Conductive paste 10: Wiring board 17: Solder resist 22: Parent wiring board (mother board) 26: Connection land 28: Cream solder 31: Conventional wiring board 32: Through hole 33: Upper surface outer layer conductor 34: Through hole Plating layer 35 Lower surface outer conductor 36 Electrode pad 39 Filler 40 Electronic component 41 Bonding wire 45 Bump 45A Solder ball 47 Jig 48
…pedestal.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.6,DB名) H01L 23/12 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 23/12

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 絶縁性基材を貫通する穴と、この絶縁性
基材を貫通する穴の一方の穴端面を塞ぐ上部表面外層導
体と、他方の開孔している穴端面に接する下部表面外層
導体と、前記両表面の外層導体を電気的に導通させる非
貫通穴内の導体層と、を備えた非貫通導通穴において、
該非貫通導通穴の上部表面外層導体をボンディングラン
ドとし、該非貫通導通穴内を外部接続用のバンプを取り
付ける電極パッドとすることを特徴とする電子部品搭載
用配線基板。
1. A hole penetrating an insulating base material, an upper surface outer layer conductor closing one end surface of the hole penetrating the insulating base material, and a lower surface contacting the other open hole end surface. An outer layer conductor, and a conductor layer in a non-through hole that electrically connects the outer layer conductors on both surfaces,
A wiring board for mounting electronic components, characterized in that an upper surface outer layer conductor of the non-through conductive hole is used as a bonding land, and the inside of the non-through conductive hole is used as an electrode pad for mounting a bump for external connection.
JP10046382A 1997-04-10 1998-02-13 Wiring board for mounting electronic components Expired - Fee Related JP2943788B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10046382A JP2943788B2 (en) 1997-04-10 1998-02-13 Wiring board for mounting electronic components

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP10683097 1997-04-10
JP9-106830 1997-04-10
JP10046382A JP2943788B2 (en) 1997-04-10 1998-02-13 Wiring board for mounting electronic components

Publications (2)

Publication Number Publication Date
JPH10340929A JPH10340929A (en) 1998-12-22
JP2943788B2 true JP2943788B2 (en) 1999-08-30

Family

ID=26386489

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10046382A Expired - Fee Related JP2943788B2 (en) 1997-04-10 1998-02-13 Wiring board for mounting electronic components

Country Status (1)

Country Link
JP (1) JP2943788B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4075306B2 (en) * 2000-12-19 2008-04-16 日立電線株式会社 Wiring board, LGA type semiconductor device, and method of manufacturing wiring board
JP4501936B2 (en) 2005-07-27 2010-07-14 株式会社村田製作所 Multilayer electronic component, electronic device, and method of manufacturing multilayer electronic component
JP2007157620A (en) * 2005-12-08 2007-06-21 D D K Ltd Electrical contact structure
JP4854738B2 (en) * 2006-06-15 2012-01-18 三洋電機株式会社 Electronic components
KR100900182B1 (en) 2007-12-13 2009-06-02 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP2009246300A (en) * 2008-03-31 2009-10-22 Tdk Corp Surface mounted part, method for manufacturing therefor, and mounting method
US20150237732A1 (en) * 2014-02-18 2015-08-20 Qualcomm Incorporated Low-profile package with passive device
KR102345061B1 (en) * 2019-11-20 2021-12-30 (주)에이티세미콘 Semiconductor package

Also Published As

Publication number Publication date
JPH10340929A (en) 1998-12-22

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