JP2942401B2 - Jig for plating - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a jig for performing electroplating for wire bonding when manufacturing a package with outer lead pins for mounting a semiconductor.

[0002]

2. Description of the Related Art Conventionally, to manufacture a package 1 with outer lead pins for mounting a semiconductor as shown in FIG. 8, a circuit 3 is formed on a substrate 2 made of an inorganic material such as ceramics by using a metal paste. Then, after applying a noble metal plating 4 for wire bonding, the outer lead pins 5 were brazed.

Recently, there is a substrate 2 of the package 1 with outer lead pins using an organic material such as glass epoxy or polyimide. In any case, the noble metal plating 4 on a second pad for wire bonding is performed by using an outer lead pin. After the mounting of No. 5, since there is no appropriate jig, it is usually performed in a process before attaching the outer lead pin 5. Moreover, because of electroplating, FIG.
As shown in (1), a circuit which is essentially unnecessary from the lead pin land 6 as the plating lead 7 is formed and plated from the outside.

In addition, Japanese Utility Model Application Laid-Open No. 2-44350 (Jpn.
As disclosed in Japanese Unexamined Patent Publication No. 3-123603), a method of plating after attaching an outer lead pin using a lead frame has been proposed. However, this method increases the cost of a die for punching the lead frame, The dimensions of the slits punched by the mold are naturally limited.

[0005] Accordingly, the inventor of the present invention mounts the outer lead pins on the semiconductor mounting package before plating the noble metal for wire bonding, and obtains stable electrical continuity from tens to hundreds of outer lead pins. As an inexpensive plating jig that can apply precious metal plating for wire bonding with a uniform thickness,
A hole larger than the outer lead pin diameter is formed in a single-sided copper clad plate made of an organic material in accordance with the outer lead pin pitch of the package for mounting a semiconductor. We developed a plating jig in which metal plating is covered and the hole opening diameter is smaller than the outer lead pin diameter. (Japanese Patent Application No. 3-
No. 49040)

To apply a noble metal plating for wire bonding to a package with outer lead pins for mounting a semiconductor using the plating jig, first place the plating jig on a backing plate, and then put the plating jig on the upper surface of the plating jig. Mask so that only the contact part of the metal plating at the opening edge of the hole remains,
Next, the outer lead pins of the semiconductor mounting package are pushed into the holes, and the outer lead pins are pressed against the metal plating on the opening edges of the holes, and then these are set facing the electrodes in an electrolytic cell containing a noble metal plating bath. Then, current is supplied to the plating jig, current flows to the outer lead pin through the metal plating at the opening edge of the hole, and a noble metal plating of uniform thickness for wire bonding is applied on the package by electrolytic plating method. .

By the way, when the plating jig pushes the outer lead pin of the semiconductor mounting package into the hole, the metal plating covering the opening edge of the hole may fall off or break. Some did not come into contact with the outer lead pins, or some were in poor contact, and the yield of energization between the outer lead pins and the plating jig was poor.

[0008]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a plating jig capable of surely making contact with an outer lead pin and improving the yield of energization.

[0009]

A plating jig according to the present invention for solving the above-mentioned problems is provided on a double-sided copper-clad plate made of an organic material by adjusting the outer lead pin diameter according to the outer lead pin pitch of a semiconductor mounting package. A large hole is drilled, the inner surface of this hole is metal-plated to form a tapered through hole, and the upper end maximum diameter of this tapered through hole is larger than the outer lead pin diameter, and the lower end minimum diameter is smaller than the outer lead pin diameter. It is characterized by having.

[0010]

In order to apply the noble metal plating for wire bonding to the package with the outer lead pins for mounting the semiconductor using the plating jig having the above structure, first place the plating jig on the backing plate, and then place the plating jig on the plate. Mask the upper surface so that only the contact portion of the metal plating at the upper opening edge of the tapered through hole remains, and then push the outer lead pin of the semiconductor mounting package into the tapered through hole, and place the outer lead pin on the inner surface of the tapered through hole. From the part to the lower metal plating, then set them facing the electrodes in the electrolytic bath containing the noble metal plating bath, supply current to the plating jig, and apply the inner peripheral surface of the tapered through hole. Apply current to the outer lead pins through the metal plating of It was subjected to noble metal plating of uniform thickness for grayed.

In the coating of the precious metal plating on the package by the electrolytic plating method, the outer lead pin is pressed against the metal plating from the middle to the high part without peeling off the metal plating on the inner surface of the tapered through hole, thereby making good contact. As a result, the yield of energization between the outer lead pins and the plating jig was significantly improved.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the plating jig of the present invention will be described with reference to the drawings. A rectangular jig made of an organic material such as glass epoxy and having a thickness of 0.1 to 3.0 mm, in this example, 0.5 mm in this example, as shown in FIG. Copper-clad board with 35 μm copper foil 11 on both sides of board 10
12, a hole 13 with an inner diameter of 0.60 mm 0.15 mm larger than the outer lead pin diameter (φ0.45 mm) is punched (or drilled) with a mold to match the outer lead pin pitch of the semiconductor mounting package as shown in FIG. Then, copper through-hole plating is applied to this double-sided copper clad plate 12 as shown in FIG.
14 is applied, copper plating 15 is applied on the copper through-hole plating 14 so that the lower surface side is thickened, and a tapered through-hole 16 is formed.The upper end maximum diameter of the tapered through-hole 16 is 0.55 mm and the outer diameter is 0.55 mm. The diameter is larger than the lead pin diameter and the minimum diameter at the lower end is 0.35 mm, which is smaller than the outer lead pin diameter.

In order to apply the noble metal plating for wire bonding to the package with the outer lead pins for mounting the semiconductor using the plating jig 17 of the embodiment configured as described above, as shown in FIG. The epoxy resin 19 is masked so that only the contact portions of the copper plating 15 at the upper and lower edges of the tapered through hole 16 on the upper surface of the through hole 16 remain, and then the outer lead pins 5 of the semiconductor mounting package 1 are tapered as shown in FIG. Push the outer lead pin 5 into the through hole 16
An electrolytic cell in which a gold plating bath 22 was placed as shown in FIG.
An electric current is supplied from a plating jig 17 to the outer lead pin 5 through the copper plating 15 on the inner peripheral surface of the tapered through hole 16, and the electric current is supplied to the outer lead pin 5, and the electrolytic solution is placed on the package 1. As shown in FIG. 8, gold plating 23 for wire bonding was applied by a plating method.

In the coating of the gold plating 23 on the package 1 by the electrolytic plating method, the outer lead pins 5 are pressed against the copper plating 15 from the middle to the lower corners without peeling off the copper plating 15 on the inner surface of the tapered through hole 16. And good contact, the yield of energization between the outer lead pin 5 and the plating jig 17 is:
The yield of energization using the plating jig of the prior application (Japanese Patent Application No. Hei 3-49040) was about 60%, which was 80% at once.
Improved above.

The gold plating 23 for wire bonding thus applied on the package 1 has a uniform thickness.
Unnecessary circuits in the product can be omitted, and the electrical performance can be improved such as the signal speed of the package 1 can be increased.

[0016]

As can be seen from the above description, according to the plating jig of the present invention, the outer lead pins are mounted before the noble metal plating for wire bonding is applied to the package for mounting the semiconductor, and the plating jig is passed through the plating jig. Noble metal plating for wire bonding can be applied by electroplating by taking electrical conduction from tens to hundreds of outer lead pins, in which case the outer lead pins are removed from the middle and lower parts without peeling off the metal plating on the inner surface of the tapered through hole. Since the metal plating can be satisfactorily brought into contact with the metal plating over the lower corner, the yield of energization between the outer lead pin and the plating jig is significantly improved, and the noble metal plating for wire bonding has a uniform thickness. Therefore, a circuit with an outer lead pin for mounting a semiconductor with improved electrical performance such as an increase in the signal speed of the package can be eliminated by eliminating unnecessary circuits in the product.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of an embodiment of a plating jig of the present invention.

FIG. 2 is a manufacturing process diagram of an embodiment of the plating jig of the present invention.

FIG. 3 is a manufacturing process diagram of one embodiment of the plating jig of the present invention.

FIG. 4 is a view showing a step of applying a noble metal plating for wire bonding to an outer lead pin package for mounting a semiconductor using the plating jig of the present invention.

FIG. 5 is a view showing a step of applying a noble metal plating for wire bonding to an outer lead pin package for mounting a semiconductor using the plating jig of the present invention.

FIG. 6 is a view showing a step of applying a noble metal plating for wire bonding to an outer lead pin package for mounting a semiconductor using the plating jig of the present invention.

FIG. 7 is a view showing a step of applying a noble metal plating for wire bonding to an outer lead pin package for mounting a semiconductor using the plating jig of the present invention.

FIG. 8 is a diagram showing a package with outer lead pins for mounting a semiconductor.

FIG. 9 is an enlarged view of a portion A in FIG. 8;

[Explanation of symbols]

 1 Package for mounting semiconductor 5 Outer lead pin 12 Double-sided copper clad plate 13 Hole 14 Copper through hole plating 15 Copper plating 16 Tapered through hole 17 Plating jig

Claims (1)

(57) [Claims] 1. A hole larger than an outer lead pin diameter is formed in a double-sided copper-clad plate made of an organic material in accordance with an outer lead pin pitch of a semiconductor mounting package, and an inner surface of the hole is metal-plated to be tapered. A plating jig characterized by being a through hole, wherein the upper end maximum diameter of the tapered through hole is larger than the outer lead pin diameter and the lower end minimum diameter is smaller than the outer lead pin diameter.