JPH0697318A - Wiring board for semiconductor device - Google Patents

Wiring board for semiconductor device

Info

Publication number
JPH0697318A
JPH0697318A JP4246566A JP24656692A JPH0697318A JP H0697318 A JPH0697318 A JP H0697318A JP 4246566 A JP4246566 A JP 4246566A JP 24656692 A JP24656692 A JP 24656692A JP H0697318 A JPH0697318 A JP H0697318A
Authority
JP
Japan
Prior art keywords
wiring
external
metal
semiconductor device
internal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4246566A
Other languages
Japanese (ja)
Inventor
Hideji Sagara
秀次 相楽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP4246566A priority Critical patent/JPH0697318A/en
Publication of JPH0697318A publication Critical patent/JPH0697318A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Abstract

PURPOSE:To maintain high rigidity of the micro work of an internal wiring, an external wiring and the external terminals formed in one body with the external wiring by electrically interconnecting the internal wiring and the external wiring with the electrically connecting holes provided in an insulating base board. CONSTITUTION:The electrically conductive connection between an internal wiring and an external wiring is formed with electrically connecting holes 16 formed in an insulating board. Further, an external terminal 15 is so formed as to stride over an annular insulator 17 used for external terminal support to project outwardly. Thereby, the internal wiring is constituted of thin metal which excels in electrical conductivity, and the external wiring is constituted of a metal plate of large rigidity, so that the flatness of the external wiring of a semiconductor device may be maintained, though the semiconductor device has a very fine internal wiring, and the semiconductor device may be handled by the same method as before.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】半導体装置用配線基板、特に多端
子を有するASIC、マイクロプロセッサ等の半導体装
置の製造に好適な配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for semiconductor devices, and more particularly to a wiring board suitable for manufacturing semiconductor devices such as ASICs and microprocessors having multiple terminals.

【0002】[0002]

【従来の技術】従来、MPU(Micro Proce
ssor Unit)、ASIC(Applicati
on Specific Integrated Ci
rcuits)等をはじめとする多端子半導体装置を低
コストで製造する方法として4方向に延びた外部リード
を有するリードフレームを用いてエポキシ系樹脂にて封
止したプラスチックQFP(Quad Flat Pa
ckage)あるいはプラスチックQFJ(Quad
Flat J−Lead Package)等が多く用
いられている。このような従来型QFP,QFJに用い
られている信号伝送、電源供給等の役割りを担うリード
フレームは、図7に示すように42合金(42%ニッケ
ル含有鉄系合金)あるいは42合金に近い電気伝導率及
び剛性をを有する銅合金等の薄板をフォトエッチング法
などにより製造するものであり、半導体素子を搭載する
ためのダイパッド部61、半導体素子とのボンディング
結線を行うためのインナーリード部62、半導体素子と
の外部回路との接続を行うアウターリード部63等によ
り構成されるものである。
2. Description of the Related Art Conventionally, MPU (Micro Process)
sor unit), ASIC (Applicati)
on Specific Integrated Ci
As a method of manufacturing a multi-terminal semiconductor device such as rcuits) at a low cost, a plastic QFP (Quad Flat Pa) sealed with an epoxy resin using a lead frame having external leads extending in four directions.
package) or plastic QFJ (Quad)
Flat J-Lead Package) and the like are often used. As shown in FIG. 7, the lead frame used for such conventional QFPs and QFJs, which plays a role of signal transmission, power supply, etc., is close to 42 alloy (42% nickel-containing iron-based alloy) or 42 alloy. A thin plate of copper alloy or the like having electrical conductivity and rigidity is manufactured by a photo-etching method or the like, and a die pad portion 61 for mounting a semiconductor element and an inner lead portion 62 for performing bonding connection with the semiconductor element. , The outer lead portion 63 for connecting the semiconductor element to an external circuit, and the like.

【0003】近年、半導体素子形成におけるリソグラフ
ィー技術の進展に伴い、半導体素子の集積度は高まると
ともに、MPU、ASIC等に代表される高機能半導体
素子の多端子化が進んでいる。この様な状況の中で、リ
ードフレームのインナーリードのピッチを小さなものと
することが必要となるが、フォトエッチング法による金
属薄板の加工では、ピッチの加工限界は板厚に依存し、
例えば板厚が0.150mmの金属板の場合には、0.
220mmピッチが半導体素子上の外部電極とのホンデ
ィング結線をなし得る平坦幅を確保できる最小ピッチと
なる。したがって、さらに半導体素子の多端子化に対応
するためには金属板厚さをより薄くするという対策によ
らざるをえない。
In recent years, with the progress of lithography technology in the formation of semiconductor elements, the degree of integration of semiconductor elements has increased, and the number of high-performance semiconductor elements represented by MPU, ASIC, etc. has been increasing. In such a situation, it is necessary to make the pitch of the inner leads of the lead frame small, but in the processing of the metal thin plate by the photo etching method, the processing limit of the pitch depends on the plate thickness,
For example, in the case of a metal plate having a plate thickness of 0.150 mm,
The 220 mm pitch is the minimum pitch that can secure a flat width capable of forming a bonding connection with the external electrode on the semiconductor element. Therefore, in order to cope with the increase in the number of terminals of semiconductor elements, it is unavoidable to take measures to reduce the thickness of the metal plate.

【0004】インナーリードのピッチを小さくするため
に、金属板厚を薄くすると、取扱時における微細リード
部の曲がりを生じたり、外部回路との接続用に使用する
外部リードの平坦性を維持することが困難になる等の問
題点を生じる。現状では剛性が高い、すなわち変位が加
えられても変形が少ない42合金の場合でも、板厚0.
10mm程度が薄肉化の許容限界であり、0.190〜
0.200mmピッチ程度がインナーリードの限界とさ
れている。この様な問題点に対し、プラスチックQF
P、QFJのインナーリードのピッチをより小さくする
ために、インナーリードとアウターリードを別々の部材
によって形成したリードフレームが提案されている。
When the thickness of the metal plate is reduced in order to reduce the pitch of the inner leads, the fine lead portions are bent during handling, and the flatness of the outer leads used for connection with an external circuit is maintained. Causes problems such as difficulty. At present, even in the case of 42 alloy, which has a high rigidity, that is, a deformation is small even when a displacement is applied, the plate thickness is 0.
About 10 mm is the allowable limit for thinning, 0.190-
The limit of the inner lead is about 0.200 mm pitch. For such problems, plastic QF
In order to further reduce the pitch of the inner leads of P and QFJ, there has been proposed a lead frame in which the inner leads and the outer leads are formed by separate members.

【0005】その一つは、図8(A)に示すようにリー
ドフレームをガラストリアジン系のプリント配線板によ
って挟持し、プリント基板上に設けた配線パターン71
へ、ダイパッド72上に載置する半導体素子の外部電極
を結合し、配線パターンはスルーホール73で電気的に
接続し、QFP(Quad FlatPackage)
のように突出したアウターリード74を形成したもので
ある。この方法によれば、インナーリードをプリント配
線板に積層した35μmの厚さの銅箔をエッチングする
ことによって形成できるため、リードの狭ピッチ化が図
れる等の特長を有している反面、あらかじめ形成したリ
ードフレームのプリント配線板のスルーホール形成部と
の正確な位置合わせが要求されることに加え、従来の多
層プリント配線板製造プロセスに加えてリードフレーム
の製造プロセスも必要となるため、製造プロセスが複雑
であることに加え、コストアップを招くという問題点を
有している。
One of them is a wiring pattern 71 provided on a printed circuit board by sandwiching a lead frame by a glass triazine-based printed wiring board as shown in FIG. 8 (A).
To the external electrode of the semiconductor element mounted on the die pad 72, and the wiring pattern is electrically connected through the through hole 73, and QFP (Quad Flat Package)
The outer lead 74 protruding as described above is formed. According to this method, the inner leads can be formed by etching a copper foil with a thickness of 35 μm laminated on a printed wiring board, which has the advantage that the pitch of the leads can be narrowed, but on the other hand, it can be formed beforehand. In addition to requiring accurate alignment of the lead frame with the through-hole formation part of the printed wiring board, the manufacturing process of the lead frame is required in addition to the conventional multilayer printed wiring board manufacturing process. In addition to being complicated, there is a problem that the cost is increased.

【0006】他の例として、図8(B)に示すようにイ
ンナーリード部をTAB(TapeAutomated
Bonding)にて構成し、ダイパッドを持たない
リードフレーム75とTABリード76とを直接接続し
て半導体素子の多端子化に対応するといった技術の提示
もなされている。しかしながら、前述のプリント配線板
にてリードフレームをサンドイッチするものと同様に、
この方法によるリードフレームの構成にはTABの製造
プロセスとリードフレームの製造プロセスが独立してい
る上にさらに、お互いのリード同士を微細領域にて接続
する必要が生じるため、製造歩留まりの向上を図ること
が難しく、さらに製造コストの低減困難といった問題点
を有している。
As another example, as shown in FIG. 8B, the inner lead portion is provided with TAB (Tape Automated).
Bonding), and a technique is proposed in which a lead frame 75 having no die pad and a TAB lead 76 are directly connected to cope with the multi-terminal of a semiconductor element. However, similar to the above-mentioned printed wiring board sandwiching the lead frame,
In the structure of the lead frame by this method, the manufacturing process of the TAB and the manufacturing process of the lead frame are independent of each other, and further, it is necessary to connect the leads to each other in a fine region, so that the manufacturing yield is improved. However, there is a problem that it is difficult to reduce the manufacturing cost.

【0007】[0007]

【発明が解決しようとする課題】この様に、従来の金属
板をフォトエッチング加工して形成するリードフレーム
にあっては、アウターリードの平坦性を維持した状態で
の、内部リードの狭ピッチ化は限界に達している。ま
た、インナーリード領域をプリント基板にて構成した
り、あるいはTABにて構成する方法にあっては、別部
材の製造プロセスを伴うため、工程が複雑化することに
加え、リードフレームの配線部とプリント基板上に形成
された回路部、あるいはTABリードとの微細領域での
接続工程を必要とするため、製造歩留まりの向上を図る
ことが困難などの問題点を有しており実用段階には至っ
ていない。
As described above, in the conventional lead frame formed by photoetching a metal plate, the inner leads are made narrower in pitch while maintaining the flatness of the outer leads. Is at the limit. Further, in the method of forming the inner lead region by the printed circuit board or the TAB, the manufacturing process of another member is involved, so that the process is complicated, and the wiring part of the lead frame and Since a circuit part formed on a printed circuit board or a connection process in a fine area with a TAB lead is required, there is a problem that it is difficult to improve the manufacturing yield, and it reaches a practical stage. Not in.

【0008】[0008]

【課題を解決するための手段】本発明は、絶縁性基板の
両面に導電性金属を積層した両面金属積層基板から構成
される半導体用配線基板において、絶縁性基板の一方の
面に半導体素子の接続端子からのボンディングワイヤと
の接続用の内部配線が形成され、他方の面には外部回路
との接続用の外部配線が形成されており、外部配線は絶
縁性基板から外へ延びた外部回路との接続用端子と一体
に形成されており、内部配線と外部配線は絶縁性基板に
設けた電気的接続孔によって導電接続されている半導体
装置用配線基板である。
DISCLOSURE OF THE INVENTION The present invention is a wiring board for a semiconductor, which is composed of a double-sided metal laminated substrate in which conductive metals are laminated on both sides of an insulating substrate. Internal wiring for connection with the bonding wire from the connection terminal is formed, and external wiring for connection with the external circuit is formed on the other surface, and the external wiring is an external circuit extending from the insulating substrate. Is a wiring board for a semiconductor device, which is formed integrally with a connection terminal for connection with the internal wiring and the external wiring is conductively connected by an electrical connection hole provided in the insulating substrate.

【0009】さらに内部配線は、厚みの薄い金属によっ
て形成されており、外部配線は内部配線よりも厚み、あ
るいは剛性が大きな金属によって形成されたものであ
り、好ましくは内部配線は絶縁性基板に積層した銅箔の
エッチングによって形成したものであり、外部配線は絶
縁性基板に積層した内部配線よりも厚さ、剛性が大きな
銅箔、銅合金、42合金などをエッチングするととも
に、絶縁性基板のエッチングにより外部配線の端部を絶
縁性基板の端部から張り出して外部回路との接続用の端
子としたものである。また、絶縁性基板には、ダイパッ
ド部もしくはダイパッド部を支持するポリイミド樹脂か
らなるフレキシブルな絶縁性基板が好ましい。
Further, the internal wiring is made of a metal having a small thickness, and the external wiring is made of a metal having a thickness or rigidity larger than that of the internal wiring. Preferably, the internal wiring is laminated on an insulating substrate. The external wiring is formed by etching the copper foil, and the external wiring etches the copper foil, the copper alloy, the 42 alloy, etc., which have a greater thickness and rigidity than the internal wiring laminated on the insulating substrate, and also etch the insulating substrate. Thus, the end portion of the external wiring is projected from the end portion of the insulating substrate to serve as a terminal for connection with an external circuit. Further, the insulating substrate is preferably a flexible insulating substrate made of a die pad portion or a polyimide resin supporting the die pad portion.

【0010】[0010]

【作用】本発明の半導体装置用配線基板を用いて半導体
素子を組立れば、外部電極を多数有する半導体素子との
接続に対し容易に対応することが可能となる。また、内
部配線を電気電導性に優れた薄肉金属にて構成し、外部
配線を剛性の大きな金属板にて構成できるため、微細な
内部配線を有していながらも半導体装置の外部配線の平
坦性を維持することが可能であり、従来と同様の方法に
て半導体装置を扱うことができる。さらに、従来のプリ
ント配線板とリードフレームあるいはTABとリードフ
レームといった別部材を一体化するものに比べて本発明
の配線基板は製造プロセスを分けることなく構成可能で
あるため、製造プロセスが簡単となる。また、半導体装
置を製造した場合には、従来のプラスチックQFPある
いはQFJを構成するリードフレームに比べ、より大形
の半導体素子搭載用金属ダイパッドを任意の金属板によ
って形成することも可能であるため、効果的な放熱が可
能な半導体装置を提供することができる。
By assembling a semiconductor element using the wiring board for a semiconductor device of the present invention, it is possible to easily cope with connection with a semiconductor element having a large number of external electrodes. Further, since the internal wiring can be made of a thin metal having excellent electric conductivity and the external wiring can be made of a metal plate having high rigidity, the flatness of the external wiring of the semiconductor device can be achieved even though it has fine internal wiring. Can be maintained, and the semiconductor device can be handled in the same manner as the conventional method. Further, the wiring board of the present invention can be constructed without dividing the manufacturing process, as compared with the conventional one in which separate members such as a printed wiring board and a lead frame or a TAB and a lead frame are integrated, so that the manufacturing process is simplified. . Further, when a semiconductor device is manufactured, it is possible to form a larger metal die pad for mounting a semiconductor element with an arbitrary metal plate as compared with a lead frame forming a conventional plastic QFP or QFJ. A semiconductor device capable of effective heat dissipation can be provided.

【0011】[0011]

【実施例】以下図面を参照して本発明の実施例について
詳細な説明を行う。図1は本発明の一実施例の半導体装
置用配線基板を示したものであり、図1(a)は平面図
を示し、図1(b)についてそれぞれ示したものであ
る。半導体素子との導電接続用の内部配線11は、絶縁
性基板12の表面に積層された金属箔、例えば銅箔等の
電気伝導性の高い金属箔によって構成されている。絶縁
性基板には誘電率及び誘電損失の低い、例えばポリイミ
ド、ガラスポリイミドあるいはポリテトラフルオロエチ
レン等が使用される。内部配線の一方の端部は、ダイパ
ッド13に載置する半導体素子の接続用端子との間で金
線等のワイヤボンディングによって導電接続される。絶
縁性基板の内部配線が形成される面との反対の面には、
外部配線14が積層されており、外部配線は絶縁性基板
の周囲に延びる外部回路接続用の外部端子15と一体に
形成されいる。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a wiring board for a semiconductor device according to an embodiment of the present invention. FIG. 1 (a) is a plan view and FIG. 1 (b) is shown respectively. The internal wiring 11 for conductive connection with the semiconductor element is formed of a metal foil laminated on the surface of the insulating substrate 12, for example, a metal foil having a high electric conductivity such as a copper foil. For the insulating substrate, polyimide, glass polyimide, polytetrafluoroethylene, or the like, which has a low dielectric constant and dielectric loss, is used. One end of the internal wiring is conductively connected to the connection terminal of the semiconductor element mounted on the die pad 13 by wire bonding such as a gold wire. On the surface opposite to the surface where the internal wiring of the insulating substrate is formed,
The external wiring 14 is laminated, and the external wiring is integrally formed with an external terminal 15 for connecting an external circuit, which extends around the insulating substrate.

【0012】外部配線および外部端子は、コバール、4
2合金等の鉄系合金、あるいは銅系合金等の剛性の大き
な金属板あるいは金属箔にて構成される。また、内部配
線と外部配線は絶縁性基板に形成した電気的接続孔16
によって導電接続を形成している。さらに、外部端子1
5は外部端子支持用のリング状絶縁物17を跨いで外方
向に突出形成されている。リング状絶縁物は内部回路お
よび外部回路を形成する絶縁性基体と同一の材料をはじ
め各種の材料を使用することができる。
External wiring and external terminals are Kovar, 4
It is composed of a metal plate or metal foil having high rigidity such as an iron-based alloy such as 2 alloys or a copper-based alloy. Further, the internal wiring and the external wiring are electrically connected holes 16 formed on the insulating substrate.
To form a conductive connection. In addition, external terminal 1
Reference numeral 5 is formed so as to project outward in a manner straddling a ring-shaped insulator 17 for supporting external terminals. For the ring-shaped insulator, various materials can be used, including the same material as the insulating substrate forming the internal circuit and the external circuit.

【0013】図2は、図1に示した半導体装置用配線基
板の裏面図を示したものである。絶縁性基板12の内部
配線とは反対側に半導体素子搭載用のダイパッド13を
設け、内部配線形成面に設けた開孔部に半導体素子を搭
載する場合には、電気的接続孔16の内側の領域の大き
さのダイパッドを使用することが可能であるので、ダイ
パッドとして熱伝導率の優れた金属等を使用することに
よって効果的な放熱が可能となる。また、金属製のダイ
パッドに直接に熱伝導性の高い接着剤等を用いて半導体
素子を取り付けることによってより効果的な放熱が可能
である。
FIG. 2 is a rear view of the semiconductor device wiring board shown in FIG. When the semiconductor element mounting die pad 13 is provided on the side opposite to the internal wiring of the insulating substrate 12 and the semiconductor element is mounted in the opening provided on the internal wiring forming surface, the inside of the electrical connection hole 16 is Since it is possible to use a die pad having a size of the region, effective heat dissipation can be achieved by using a metal or the like having excellent thermal conductivity as the die pad. Further, more effective heat dissipation can be achieved by directly attaching the semiconductor element to the metal die pad using an adhesive having a high thermal conductivity or the like.

【0014】図3は、本発明の半導体装置用配線基板を
用いて製造した半導体装置の一実施例を示す断面図であ
る。半導体素子18上の外部電極19と内部配線11の
端部を金線、アルミニウム線等の金属細線20で接続し
ており、外部端子15はガルウイング状に折曲げられて
おり、外部端子には42合金等のようにJ型もしくはガ
ルウイング状に成形しても金属疲労を生じない材質のも
のが使用されている。
FIG. 3 is a sectional view showing an embodiment of a semiconductor device manufactured by using the wiring board for a semiconductor device of the present invention. The external electrode 19 on the semiconductor element 18 and the end of the internal wiring 11 are connected by a thin metal wire 20 such as a gold wire or an aluminum wire. The external terminal 15 is bent in a gull wing shape, and the external terminal is 42 A material such as an alloy that does not cause metal fatigue even if it is formed into a J-shape or a gull-wing shape is used.

【0015】図4には、他の半導体装置の実施例を示
す。内部配線11の先端部分を絶縁性基板12より突出
させてフィンガーリード21を形成し、フィンガーリー
ド21と半導体素子上の外部電極上に形成した突起電極
22とを直接ボンディングするTABアセンブリ方式に
よって半導体装置を組み立てる場合を示している。
FIG. 4 shows another embodiment of the semiconductor device. The semiconductor device is manufactured by the TAB assembly method in which the tip end portion of the internal wiring 11 is projected from the insulating substrate 12 to form the finger lead 21, and the finger lead 21 and the protruding electrode 22 formed on the external electrode on the semiconductor element are directly bonded. It shows the case of assembling.

【0016】以上の図1ないし図4では、外部端子支持
用のリング状絶縁物にて外部端子を支持し、リング状絶
縁物をモールディングの際のダムバーとすることを示し
たが、半導体装置の組立において、ダムバーを残すか否
かはいずれでもよく、さらにリング状絶縁物を形成して
もしなくてもいずれでも良い。また、本発明のリング状
絶縁物として絶縁性に優れた材料を使用したので、半導
体装置の組立後にも切断する必要がないばかりではな
く、半導体装置の外部端子の平坦性をより確実たらしめ
ることが可能である。
1 to 4 described above, the external terminal is supported by the ring-shaped insulator for supporting the external terminal, and the ring-shaped insulator is used as a dam bar for molding. In the assembly, whether or not the dam bar is left may be left, and whether or not the ring-shaped insulator is formed may be left or right. Further, since a material having excellent insulating properties is used as the ring-shaped insulator of the present invention, not only does it not need to be cut after the semiconductor device is assembled, but also the flatness of the external terminals of the semiconductor device can be more surely ensured. Is possible.

【0017】さらに、本発明の半導体装置用配線基板
は、図1ないし図4に示すように、シングルチップパッ
ケージ用のMPU、ASIC等として説明したが、複数
の半導体素子を有する例えばMCM(Multi Ch
ip Module)を製造するための半導体装置用配
線基板としても使用することができる。このような半導
体装置に使用する場合には、絶縁性基板として、ガラス
ポリイミド、ポリテトラスフロオエチレン、ポリフェニ
レンオキサイド等高周波領域での誘電率、誘電損失の小
さい絶縁物を使用することによって、信頼性の高い高速
動作の半導体装置を提供することができる。
Further, the wiring board for a semiconductor device of the present invention has been described as an MPU, an ASIC, etc. for a single chip package as shown in FIGS. 1 to 4, but, for example, an MCM (Multi Ch) having a plurality of semiconductor elements.
It can also be used as a wiring board for a semiconductor device for manufacturing an ip module). When used in such a semiconductor device, reliability is improved by using an insulating substrate such as glass polyimide, polytetrafluoroethylene, polyphenylene oxide, etc., which has a low dielectric constant in the high frequency region and a low dielectric loss. A high-speed and high-speed operation semiconductor device can be provided.

【0018】次に、図5を示し、本発明の半導体装置用
配線基板の製造方法の一例を説明する。絶縁性基板とし
てポリイミド基板を用いて半導体装置用配線基板を製造
した例を示す。外部配線用金属として、大きさ500m
m×500mm、厚さ0.1mmの42合金を用い、N
−メチル−2−ピロリドン溶媒中にピロメリット酸無水
物より合成したポリアミド酸固形分を30重量%溶解し
たポリアミド酸ワニスを、42合金板31上にスクリー
ン印刷法にて塗布し、乾燥後の厚さが10μmのポリア
ミド酸塗布膜32を形成した。一方、内部配線金属とし
て、大きさ500mm×500mm、厚さ0.018m
mの圧延銅箔33の片面に、42合金と同様にポリアミ
ド酸ワニスをスクリーン印刷法にて乾燥後の厚さ10μ
mのポリアミド酸塗布膜34を得た(図5(a))。
Next, referring to FIG. 5, an example of a method for manufacturing a wiring board for a semiconductor device of the present invention will be described. An example of manufacturing a wiring board for a semiconductor device using a polyimide substrate as an insulating substrate will be described. 500m in size as metal for external wiring
m × 500 mm, thickness 0.1 mm 42 alloy, N
-Methyl-2-pyrrolidone A polyamic acid varnish obtained by dissolving 30% by weight of a polyamic acid solid compound synthesized from pyromellitic acid anhydride in a solvent is applied onto a 42 alloy plate 31 by a screen printing method, and a thickness after drying. A polyamic acid coating film 32 having a thickness of 10 μm was formed. On the other hand, as internal wiring metal, size 500 mm x 500 mm, thickness 0.018 m
On one side of the rolled copper foil 33 having a thickness of 10 m, a polyamic acid varnish was dried by a screen printing method in the same manner as the 42 alloy to have a thickness of 10 μm.
A polyamic acid coating film 34 of m was obtained (FIG. 5 (a)).

【0019】次に、図5(a)で得た両金属面を外側に
して、50μmのポリイミドフィルム35を間に設け
て、15〜30kgf/cm2 、260℃、120秒の
条件で加圧昇温を行い、ポリアミド酸の重合反応を促進
してポリイミドとし、金属を両面に積層したポリイミド
基板を得た(図5(b))。
Next, with both metal surfaces obtained in FIG. 5 (a) outside, a polyimide film 35 of 50 μm is provided between them, and pressure is applied under the conditions of 15 to 30 kgf / cm 2 , 260 ° C. and 120 seconds. The temperature was raised to accelerate the polymerization reaction of polyamic acid to obtain polyimide, and a polyimide substrate having a metal laminated on both sides was obtained (FIG. 5 (b)).

【0020】得られた両面金属積層ポリイミド基板を、
0.5mm厚よりなるアルミ板にて挟持して、0.1m
m径ドリル36(東芝タンガロイ製)を取りつけたドリ
ル加工機(オイレス工業製)の加工ステージにセットし
てスピンドル回転数80,000rpm、ドリル送り速
度6.2m/分の加工条件にて内部リードと外部リード
との接続を行うべき箇所に穴37を設けた(図5
(c))。
The obtained double-sided metal laminated polyimide substrate is
0.1m when sandwiched by 0.5mm thick aluminum plates
Set it on the processing stage of a drilling machine (manufactured by OILES Co., Ltd.) equipped with an m-diameter drill 36 (manufactured by Toshiba Tungaloy) and use it as an internal lead under the processing conditions of spindle rotation speed 80,000 rpm and drill feed speed 6.2 m / min. A hole 37 is provided at a place where connection with an external lead should be made (see FIG. 5).
(C)).

【0021】ついで、穴あき両面金属ポリイミド基板
を、塩化パラジウム溶液によって処理した後に無電解銅
めっきを施し、さらに30℃の硫酸銅浴中にて3A/d
2 の電流密度で10分間通電して厚さ15μmの金属
銅のスルーホール38を形成した(図5(d))。次
に、ネガ型ドライフィルムレジスト39(モートン・イ
ンターナショナル製ラミナーAG)を両面に積層し、半
導体素子搭載用ダイパッド部40、外部配線形成用窓部
41、窓部42等を形成するためのパターンを形成し
た。(図5(e))。
Then, the perforated double-sided metal polyimide substrate is treated with a palladium chloride solution, then electroless copper plated, and further 3 A / d in a copper sulfate bath at 30 ° C.
A current density of m 2 was applied for 10 minutes to form a through hole 38 of metallic copper having a thickness of 15 μm (FIG. 5D). Next, a negative dry film resist 39 (Laminar AG manufactured by Morton International) is laminated on both sides to form a pattern for forming a semiconductor element mounting die pad portion 40, an external wiring forming window portion 41, a window portion 42 and the like. Formed. (FIG.5 (e)).

【0022】レジストのパターンを形成した両面金属積
層ポリイミド基板を塩化第2鉄からなるエッチング液を
用いて金属部分に所定のパターンを形成した後に、アル
カリ剥離液を用いてドライフィルムレジストを剥離した
(図5(f))。
After forming a predetermined pattern on the metal portion of the double-sided metal-laminated polyimide substrate on which a resist pattern has been formed using an etching solution composed of ferric chloride, the dry film resist is peeled off using an alkali peeling solution ( FIG. 5 (f)).

【0023】次に1N水酸化カリウムに調整した80容
量%エタノール溶液中にて金属除去部より露出したポリ
イミド43の溶解除去を行った(図5(g))。さら
に、カチオン型電着レジスト44を金属部部分の全域に
電気泳動によって被覆し、内部配線、外部配線、スルー
ホールランド部等の形成に必要な部分のレジストパター
ンを形成した(図5(h))。
Next, the polyimide 43 exposed from the metal removing part was dissolved and removed in an 80% by volume ethanol solution adjusted to 1N potassium hydroxide (FIG. 5 (g)). Further, a cation-type electrodeposition resist 44 was electrophoretically coated on the entire metal portion to form a resist pattern of a portion necessary for forming internal wiring, external wiring, through hole lands, etc. (FIG. 5 (h)). ).

【0024】また、図5(f)にて実施した方法と同様
にレジストから露出した金属部分のエッチングを行な
い、内部配線45、外部配線46、半導体素子搭載用ダ
イパッド47等を形成し、次いで、10%水酸化ナトリ
ウム溶液からなるアルカリ剥離液を用いてレジスト除去
を行った(図5(i))。この様にして製造を行った回
路基板(i)に無電解ニッケルめっきを3μmの厚さに
形成し、次いで電気金めっきを3μmの厚さに行って金
属表面処理を施し、半導体装置用回路基板を完成した。
Further, the metal portion exposed from the resist is etched to form the internal wiring 45, the external wiring 46, the semiconductor element mounting die pad 47, etc. in the same manner as in the method shown in FIG. 5F, and then, The resist was removed using an alkaline stripping solution consisting of a 10% sodium hydroxide solution (FIG. 5 (i)). The circuit board (i) thus manufactured is electroless nickel plated to a thickness of 3 μm, and then electro-gold plated to a thickness of 3 μm to perform a metal surface treatment. Was completed.

【0025】また、本発明の半導体装置用配線基板に
は、両面の金属をエポキシ系接着剤あるいはアクリル系
接着剤を用いて絶縁性基体となるポリイミド、ポリアミ
ド、ガラスポリイミド、PEEK、PETあるいはポリ
テトラフルオロエチレン等の耐熱性及び絶縁性を有した
絶縁物に貼りあわせて構成してもよいし、あるいは無接
着剤型片面ポリイミド基板(例えばESPANEX:新
日鐵化学製)のポリイミド面側に接着剤を用いて第2の
金属箔あるいは金属板を貼り合わせて構成してもよい。
内部配線となる銅箔等の電気伝導性に優れる金属箔を接
着剤を用いてポリイミド樹脂と貼り合わせた後、あるい
は片面銅箔ポリイミド基板の状態で、外部配線形成部と
なる金属及びポリイミド樹脂をパンチング除去して外部
リードの形成面となる第2の金属箔あるいは金属板を接
着剤を用いて貼りあわせることで本発明の配線基板を構
成できる。
Further, in the wiring board for semiconductor device of the present invention, polyimide, polyamide, glass polyimide, PEEK, PET or polytetra which serves as an insulating substrate is prepared by using an epoxy adhesive or an acrylic adhesive for the metal on both sides. It may be formed by bonding it to an insulator having heat resistance and insulation such as fluoroethylene, or an adhesive on the polyimide side of a non-adhesive type single-sided polyimide substrate (for example, ESPANEX: Nippon Steel Chemical). Alternatively, the second metal foil or the metal plate may be bonded together by using.
After bonding a metal foil with excellent electrical conductivity such as copper foil to be the internal wiring with a polyimide resin using an adhesive, or in the state of a single-sided copper foil polyimide substrate, remove the metal and polyimide resin to be the external wiring formation part. The wiring board of the present invention can be constructed by removing the punching and adhering the second metal foil or the metal plate, which will be the surface on which the external leads are formed, with an adhesive.

【0026】図6は、パンチングによってポリイミド樹
脂を除去して製造する方法を示す。銅箔51を絶縁性基
板52に、接着剤53で積層し、絶縁性基板の他方の面
には、金属を積層用の接着剤層を形成した基板(図6
(a))を、金型54で、窓部55、導電接続用穴部5
6、外部配線形成用窓部57を形成する(図6
(b))。 接着剤層に42合金板58を積層し(図6
(c))、導電接続用穴部を残してレジストを59を塗
布し、無電解めっきによって表裏の導電接続を形成する
(図6(d))。
FIG. 6 shows a method of manufacturing by removing the polyimide resin by punching. A copper foil 51 is laminated on an insulating substrate 52 with an adhesive 53, and an adhesive layer for laminating metal is formed on the other surface of the insulating substrate (see FIG. 6).
(A)), the mold 54, the window 55, the conductive connection hole 5
6. Form the external wiring forming window 57 (see FIG. 6).
(B)). The 42 alloy plate 58 is laminated on the adhesive layer (see FIG. 6).
(C)) A resist 59 is applied while leaving the conductive connection holes, and electroconductive plating is used to form the front and back conductive connections (FIG. 6D).

【0027】次いで、レジスト59を除去し、以降の操
作は図5(i)と同様に表裏にエッチングパターン形成
用のレジストを塗布して、内部配線、外部配線をエッチ
ングによって形成して、配線基板を形成する。絶縁性基
板の除去は、金型を使用した方法以外にも、エキシマレ
ーザ等を使用して除去する方法等によっても形成するこ
とができる。
Next, the resist 59 is removed, and in the subsequent operations, resists for forming an etching pattern are applied on the front and back surfaces in the same manner as in FIG. 5 (i), and internal wiring and external wiring are formed by etching, and a wiring board. To form. The insulating substrate can be removed by a method using an excimer laser or the like instead of the method using a mold.

【0028】さらに、半導体素子が消費する電力が大き
い場合には、半導体素子搭載部となる金属ダイパッド部
を、外部配線用の金属とは別の熱伝導性の高い金属にて
構成し、本発明の半導体装置用回路基板の製造後あるい
は製造過程の一部において貼り合わせるなどして本半導
体装置用回路基板を完成させてもよい。また、本発明の
回路基板における配線部の製造方法は、本実施例にて示
したエッチングのように不要な部分を除去する方法に限
らず、無電解めっき、スパッタリングリング等の成膜手
段によって、配線部を形成したり、あるいはこのような
成膜手段によって形成した配線部に、さらに電気めっき
等の方法によって、所定の厚さの配線部を形成しても良
い。
Further, when the semiconductor element consumes a large amount of power, the metal die pad portion, which is the semiconductor element mounting portion, is made of a metal having a high thermal conductivity, which is different from the metal for external wiring. The present semiconductor device circuit board may be completed by, for example, bonding the semiconductor device circuit board after or during part of the manufacturing process. Further, the manufacturing method of the wiring portion in the circuit board of the present invention is not limited to the method of removing an unnecessary portion like the etching shown in the present embodiment, electroless plating, by a film forming means such as a sputtering ring, A wiring portion may be formed, or a wiring portion having a predetermined thickness may be further formed on the wiring portion formed by such a film forming means by a method such as electroplating.

【0029】[0029]

【発明の効果】本発明の半導体装置用配線基板は、微細
なピッチで形成することが必要な内部配線用金属と、機
械的強度等を要求される外部配線用金属を絶縁性基体の
両面に、形成してそれぞれをエッチングすることによっ
て配線部分を形成し、内部配線と外部配線を電気的接続
孔によって導電接続したので、内部配線の微細加工と外
部配線および外部配線と一体の外部端子の剛性を高く維
持することができる。その結果、極めて微細な内部配線
を有する配線基板でありながら、半導体装置の組み立て
後の取扱い性も良く、特に外部端子部をガルウイング状
に成形した後の端子の同一平面性を保持するのに十分な
強度を有する半導体装置を提供しえるため、外部端子と
回路基板とのはんだ付けを行う上での信頼性を維持する
ことができる。また、ファインピッチ化に好適なTCP
(Tape Carrier Package)の利点
と、外部リードの高硬度を有するリードフレームの利点
を合わせ持つ特長を有する配線基板を容易に製造できる
という特長を有している。
According to the wiring board for a semiconductor device of the present invention, the metal for internal wiring, which needs to be formed with a fine pitch, and the metal for external wiring, which is required to have mechanical strength, are provided on both surfaces of the insulating substrate. , The wiring part was formed by forming and etching each, and the internal wiring and the external wiring were conductively connected by the electrical connection hole. Therefore, the internal wiring is finely processed and the rigidity of the external terminal integrated with the external wiring and the external wiring. Can be kept high. As a result, even though the wiring board has extremely fine internal wiring, it is easy to handle after assembling the semiconductor device, and is particularly sufficient to maintain the coplanarity of the terminals after molding the external terminal portion into a gull wing shape. Since it is possible to provide a semiconductor device having various strengths, it is possible to maintain reliability in soldering the external terminal and the circuit board. TCP suitable for fine pitch
(Tape Carrier Package) and the advantage of the lead frame having the high hardness of the external leads are combined, and thus the wiring board having the advantage can be easily manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の半導体装置用回路基板の平
面図及び断面図を示したもの。
FIG. 1 is a plan view and a sectional view of a semiconductor device circuit board according to an embodiment of the present invention.

【図2】図1の実施例の半導体装置用回路基板の裏面図
を示したもの。
2 is a rear view of the circuit board for a semiconductor device of the embodiment of FIG.

【図3】本発明の半導体用配線基板を使用した半導体装
置の断面図を示したもの。
FIG. 3 is a cross-sectional view of a semiconductor device using the semiconductor wiring board of the present invention.

【図4】半導体装置用回路基板の他の実施例を示した正
面図及びこれを用いた半導体装置の断面図をしめす。
FIG. 4 shows a front view showing another embodiment of a semiconductor device circuit board and a cross-sectional view of a semiconductor device using the same.

【図5】本発明の半導体装置用回路基板の製造方法の一
例を示した図。
FIG. 5 is a diagram showing an example of a method for manufacturing a circuit board for a semiconductor device of the present invention.

【図6】本発明の半導体装置用回路基板の製造方法の他
の例を示した図。
FIG. 6 is a diagram showing another example of the method for manufacturing a circuit board for a semiconductor device of the present invention.

【図7】従来のリードフレームの平面図。FIG. 7 is a plan view of a conventional lead frame.

【図8】従来のプラスチックQFP、QFJ用のプリン
ト基板とリードフレームとを組み合わせたもの。
FIG. 8 shows a combination of a conventional printed circuit board for plastic QFP and QFJ and a lead frame.

【符号の説明】[Explanation of symbols]

11…内部配線、12…絶縁性基板、13…ダイパッ
ド、14…外部配線、15…外部端子、16…導電接続
孔、17…リング状絶縁物、18…半導体素子、19…
外部電極、20…金属細線、21…フィンガーリード、
22…突起電極、31…42合金板、32…ポリアミド
酸塗布膜、33…圧延銅箔、34…ポリアミド酸塗布
膜、35…ポリイミドフィルム、36…ドリル、37…
穴、38…スルーホール、39…ネガ型ドライフィルム
レジスト、40…半導体素子搭載用ダイパッド部、41
…外部配線形成用窓部、42…窓部、43…ポリイミ
ド、44…カチオン型電着レジスト、45…内部配線、
46…外部配線、47…半導体素子搭載用ダイパッド、
51…銅箔、52…絶縁性基板、53…接着剤、54…
金型、55…窓部、56…導電接続用穴部、57…外部
配線形成用窓部、58…42合金板、59…レジスト
11 ... Internal wiring, 12 ... Insulating substrate, 13 ... Die pad, 14 ... External wiring, 15 ... External terminal, 16 ... Conductive connection hole, 17 ... Ring insulator, 18 ... Semiconductor element, 19 ...
External electrode, 20 ... fine metal wire, 21 ... finger lead,
22 ... Projection electrode, 31 ... 42 Alloy plate, 32 ... Polyamic acid coating film, 33 ... Rolled copper foil, 34 ... Polyamic acid coating film, 35 ... Polyimide film, 36 ... Drill, 37 ...
Holes, 38 ... Through holes, 39 ... Negative dry film resist, 40 ... Semiconductor element mounting die pad section, 41
... window portion for forming external wiring, 42 ... window portion, 43 ... polyimide, 44 ... cationic type electrodeposition resist, 45 ... internal wiring,
46 ... External wiring, 47 ... Die pad for mounting semiconductor element,
51 ... Copper foil, 52 ... Insulating substrate, 53 ... Adhesive, 54 ...
Mold, 55 ... Window portion, 56 ... Conductive connection hole portion, 57 ... External wiring forming window portion, 58 ... 42 Alloy plate, 59 ... Resist

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/46 Q 6921−4E // C23F 1/02 8414−4K ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H05K 3/46 Q 6921-4E // C23F 1/02 8414-4K

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板の両面に導電性金属を積層し
た両面金属積層基板から構成される半導体装置用配線基
板において、半導体素子の搭載部、半導体素子との接続
用の内部配線を絶縁性基板の一方の面に有し、他方の面
には外部回路との接続用の外部配線および外部配線と一
体の外部回路との接続用の外部端子を有し、内部配線と
外部配線とは絶縁性基板に設けた電気的接続孔を介して
導電接続を形成したことを特徴とする半導体装置用配線
基板。
1. A wiring board for a semiconductor device comprising a double-sided metal laminated board in which a conductive metal is laminated on both sides of an insulating board, wherein the mounting portion of the semiconductor element and the internal wiring for connection with the semiconductor element are insulated. It is provided on one side of the board, and the other side has external wiring for connecting to an external circuit and external terminals for connecting to an external circuit integrated with the external wiring, and insulates the internal wiring from the external wiring. A wiring board for a semiconductor device, characterized in that a conductive connection is formed through an electrical connection hole provided in the flexible substrate.
【請求項2】 内部配線用の金属と外部回路用の金属
は、厚さまたは材質が異なる金属であって、外部回路用
の金属は内部配線用金属に比べて厚みが厚い金属もしく
は剛性が大きな金属であることを特徴とする請求項1記
載の半導体装置用配線基板。
2. The metal for internal wiring and the metal for external circuit are metals having different thicknesses or materials, and the metal for external circuit is thicker or has higher rigidity than the metal for internal wiring. The wiring board for a semiconductor device according to claim 1, wherein the wiring board is a metal.
【請求項3】 絶縁性基体がポリイミド樹脂、内部配線
用の金属が銅もしくは銅合金であり、外部配線用の金属
が銅合金、ニッケル鉄系合金であることを特徴とする請
求項1もしくは2のいずれかに記載の半導体装置用配線
基板。
3. The insulating substrate is a polyimide resin, the metal for the internal wiring is copper or a copper alloy, and the metal for the external wiring is a copper alloy or a nickel-iron alloy. The wiring board for a semiconductor device according to any one of 1.
JP4246566A 1992-09-16 1992-09-16 Wiring board for semiconductor device Pending JPH0697318A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4246566A JPH0697318A (en) 1992-09-16 1992-09-16 Wiring board for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4246566A JPH0697318A (en) 1992-09-16 1992-09-16 Wiring board for semiconductor device

Publications (1)

Publication Number Publication Date
JPH0697318A true JPH0697318A (en) 1994-04-08

Family

ID=17150324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4246566A Pending JPH0697318A (en) 1992-09-16 1992-09-16 Wiring board for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0697318A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004082019A1 (en) * 2003-03-11 2004-09-23 The Furukawa Electric Co. Ltd. Printed wiring board, method for manufacturing same, lead frame package and optical module
JP2009055055A (en) * 2002-12-27 2009-03-12 Kyushu Hitachi Maxell Ltd Method of manufacturing semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009055055A (en) * 2002-12-27 2009-03-12 Kyushu Hitachi Maxell Ltd Method of manufacturing semiconductor device
WO2004082019A1 (en) * 2003-03-11 2004-09-23 The Furukawa Electric Co. Ltd. Printed wiring board, method for manufacturing same, lead frame package and optical module
JPWO2004082019A1 (en) * 2003-03-11 2006-06-15 古河電気工業株式会社 Printed wiring board, manufacturing method thereof, lead frame package, and optical module
US7355862B2 (en) 2003-03-11 2008-04-08 The Furukawa Electric Co., Ltd. Printed wiring board, method of manufacturing the printed wiring board, lead frame package, and optical module
CN100440500C (en) * 2003-03-11 2008-12-03 古河电气工业株式会社 Printed wiring board, method for manufacturing same, lead frame package and optical module
JP4514709B2 (en) * 2003-03-11 2010-07-28 古河電気工業株式会社 Printed wiring board, manufacturing method thereof, lead frame package, and optical module
US7832092B2 (en) 2003-03-11 2010-11-16 The Furukawa Electric Co., Ltd. Method of manufacturing a printed wiring board lead frame package

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