JPH10294549A - Manufacture of printed wiring board and printed wiring board - Google Patents

Manufacture of printed wiring board and printed wiring board

Info

Publication number
JPH10294549A
JPH10294549A JP11763797A JP11763797A JPH10294549A JP H10294549 A JPH10294549 A JP H10294549A JP 11763797 A JP11763797 A JP 11763797A JP 11763797 A JP11763797 A JP 11763797A JP H10294549 A JPH10294549 A JP H10294549A
Authority
JP
Japan
Prior art keywords
wiring board
printed wiring
component
plating
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11763797A
Other languages
Japanese (ja)
Inventor
Hiroyuki Fujimi
見 浩 之 藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP11763797A priority Critical patent/JPH10294549A/en
Publication of JPH10294549A publication Critical patent/JPH10294549A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/24Reinforcing the conductive pattern
    • H05K3/243Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

PROBLEM TO BE SOLVED: To increase the density and to improve the electric characteristics by mounting a bare chip component, a surface mount component, and a pin insertion type component together. SOLUTION: When the printed wiring board on which the bare chip component and a soldered component are both mounted is manufactured by this method, plating resist is applied to circuit wires formed on an insulating substrate 2 and bonding pads 7 are plated. Then the plating resist is peeled off and solder resist 1 is applied to the substrate except soldered component pads to form a solder coat. Cutting is performed in a coating range 9 of resin sealing the bare chip component to expose the bonding pads 7, thereby giving a step to the coating range.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はプリント配線基板の
製造方法及びプリント配線基板に関し、特にベアチップ
部品、表面実装部品、ピン挿入型部品が混在し、高密度
化、電気的特性の向上を図ったプリント配線基板の製造
方法及びプリント配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a printed wiring board and a printed wiring board, and more particularly to a method of mixing a bare chip component, a surface mount component, and a pin insertion type component to achieve higher density and improved electrical characteristics. The present invention relates to a method for manufacturing a printed wiring board and a printed wiring board.

【0002】[0002]

【従来の技術】多数のチップ部品とベアチップICを混
載したプリント基板を製造する際、多数のメッキリード
を必要とせず接続の信頼性を確保しつつ、高密度配線を
可能として、製造コストを低減させるプリント配線基板
の製造方法が、特開平4−221881号公報に開示さ
れている。
2. Description of the Related Art When manufacturing a printed circuit board on which a large number of chip components and bare chip ICs are mixedly mounted, high-density wiring is possible while maintaining connection reliability without requiring a large number of plated leads, thereby reducing manufacturing costs. A method of manufacturing a printed wiring board to be performed is disclosed in Japanese Patent Application Laid-Open No. H4-222181.

【0003】この公報に開示されているプリント配線基
板の製造方法では、プリント基板に導体パターンを形成
した後、この導体パターン上全体に無電解メッキにより
ニッケル及び金をメッキし、次いでベアチップICを実
装する領域を除いた領域をメッキレジストで覆い、続い
て、このメッキレジスト以外の領域に、電解メッキによ
り金メッキを施す。こうすることにより、はんだ付けに
より電気的接続を行うチップ部品と、ワイヤーボンデイ
ングにより電気的接続を行うベアチップICをどちらも
良好な条件下で実装できる。
In the method of manufacturing a printed wiring board disclosed in this publication, after a conductor pattern is formed on a printed board, nickel and gold are plated on the entire conductor pattern by electroless plating, and then a bare chip IC is mounted. The area excluding the area to be covered is covered with a plating resist, and subsequently, the area other than the plating resist is plated with gold by electrolytic plating. By doing so, both a chip component electrically connected by soldering and a bare chip IC electrically connected by wire bonding can be mounted under favorable conditions.

【0004】図7及び図8には、プリント配線基板の上
面図及び断面図が示されている。絶縁基板2上にボンデ
ィングパッド7が形成されるとともに表面実装部品パッ
ド5が形成される。図中、9は封止樹脂塗布範囲を示
す。絶縁基板2上のCu(銅)配線をエッチングして形
成されたボンディングパッド7上に、Ni+Auメッキ
層19が無電解メッキにより各5μm、0.05μm厚
に配線全体に対して形成される。その後、ソルダレジス
ト1及びワイヤーボンディング箇所以外の配線をマスク
するメッキレジスト10を塗布し、電解メッキによりA
uメッキ層12を0.5μ1m厚に形成する。最後に、
メッキレジスト10を剥離する。
FIGS. 7 and 8 are a top view and a sectional view of a printed wiring board. Bonding pads 7 are formed on insulating substrate 2 and surface mount component pads 5 are formed. In the figure, reference numeral 9 denotes a sealing resin application range. On the bonding pad 7 formed by etching the Cu (copper) wiring on the insulating substrate 2, a Ni + Au plating layer 19 is formed to a thickness of 5 μm and 0.05 μm on the entire wiring by electroless plating. Thereafter, a plating resist 10 for masking the wiring other than the solder resist 1 and the wire bonding portion is applied, and A is applied by electrolytic plating.
The u-plated layer 12 is formed to a thickness of 0.5 μm. Finally,
The plating resist 10 is peeled off.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
た従来のプリント配線基板の製造方法は、次のような問
題を有する。すなわち、 (1)表面実装部品パッド5に対し予備はんだが施され
ていないため、はんだ付けの信頼性、及び部品ずれ修正
など生産性が低下する。 (2)表面実装部品パッド5に予備はんだを行う場合
は、はんだ印刷を行った後、リフローをする必要があり
工数が増加する。 (3)ベアチップ部品に樹脂封止を行う場合、樹脂の塗
布範囲9を限定する構造でないため、塗布範囲の影響に
よる部品実装不可範囲が大きくなる。 (4)ベアチップ部品を封止するための樹脂の塗布範囲
を制限するためには、シルク印刷などの絶緑体を印刷す
る必要があり、電気的特性が変動する。 (5)回路配線すべてにAuメッキが施されているた
め、はんだ付け部品においては、はんだとAuとの金属
化合物が生成し、接合部が脆性となる。
However, the above-mentioned conventional method for manufacturing a printed wiring board has the following problems. That is, (1) Since the preliminary soldering is not applied to the surface mount component pad 5, the reliability of soldering and the productivity such as the correction of component misalignment decrease. (2) When performing preliminary soldering on the surface mount component pad 5, it is necessary to perform reflow after performing solder printing, which increases the number of steps. (3) When resin sealing is performed on the bare chip component, the structure in which the resin application range 9 is not limited is not used, so that the component mounting impossible range becomes large due to the influence of the application range. (4) In order to limit the application range of the resin for sealing the bare chip component, it is necessary to print a green body such as silk printing, and the electrical characteristics fluctuate. (5) Since all the circuit wirings are plated with Au, in a soldered component, a metal compound of the solder and Au is generated, and the joint becomes brittle.

【0006】[0006]

【課題を解決するための手段】前述の課題を解決するた
め、本発明によるプリント配線基板の製造方法及びプリ
ント配線基板は、ベアチップ部品とはんだ付け部品を混
在実装するプリント配線基板の製造方法において、絶縁
基板上に形成された回路配線にメッキレジストを塗布
し、ボンディングパッドにメッキを施す工程と、前記メ
ッキレジストを剥離し、はんだ付け部品パッド以外にソ
ルダレジストを塗布し、はんだコートを施す工程と、前
記ベアチップ部品を封止する樹脂の塗布範囲について切
削加工を行い、ボンディングパッドを露出させ、前記塗
布範囲に段差をつける工程とを備えて構成される。
According to the present invention, there is provided a method of manufacturing a printed wiring board and a method of manufacturing a printed wiring board in which bare chip components and soldered components are mixedly mounted. A step of applying a plating resist to circuit wiring formed on the insulating substrate and plating the bonding pads, a step of peeling the plating resist, applying a solder resist other than the soldering component pads, and applying a solder coat; And performing a cutting process on an application range of the resin for sealing the bare chip component, exposing a bonding pad, and forming a step in the application range.

【0007】ここで、前記メッキレジストを剥離した
後、剥離方法の異なる2種類のソルダレジストを使用
し、一方のソルダレジストを剥離して、ボンディングパ
ッドを露出させ、同時に塗布範囲に段差をつける工程を
有する。また、前記メッキはNi及びAuメッキであ
る。
Here, after the plating resist is stripped, a step of using two types of solder resists having different stripping methods, stripping one of the solder resists, exposing the bonding pads, and simultaneously forming a step in the application range. Having. The plating is Ni and Au plating.

【0008】本発明によるプリント配線基板は、ベアチ
ップ部品とはんだ付け部品を混在実装するプリント配線
基板であり、ボンディングパッドにAuメッキが、前記
はんだ付け部品にはんだコートが施され、前記ベアチッ
プ部品を封止する樹脂の塗布範囲を制限する構造を有す
る。
A printed wiring board according to the present invention is a printed wiring board on which bare chip components and soldered components are mixedly mounted. Au plating is applied to bonding pads, solder coating is applied to the soldered components, and the bare chip components are sealed. It has a structure that limits the application range of the resin to be stopped.

【0009】[0009]

【発明の実施の形態】次に本発明によるプリント配線基
板の製造方法及びプリント配線基板の実施形態を図面を
参照しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for manufacturing a printed wiring board and a printed wiring board according to the present invention will be described with reference to the drawings.

【0010】図1にはベアチップ部品、表面実装部品、
ピン挿入型部品の混在実装用プリント配線基板の上面図
が示されている。
FIG. 1 shows bare chip components, surface mount components,
A top view of a printed wiring board for mixed mounting of pin insertion components is shown.

【0011】ボンディングパッド7を囲むベアチップ部
品を封止する樹脂の塗布範囲9を、ハッチング部分のソ
ルダレジスト1に対し段差を持たせ低く作ることで、封
止する樹脂を堰ぎ止める範囲を限定する。この範囲の形
状は、機械的に切削する場合にはコーナー部にRを設け
るのが好ましい。また、この範囲が小さい場合などは円
形を採用すれば良い。ボンディングパッド7及び表面実
装部品パッド5について、点線の切断位置8の断面図で
ある図2、図3及び図4を参照して以下にその製造方法
を説明する。
The range of application of the resin for sealing the bare chip component surrounding the bonding pad 7 is made lower by providing a step with respect to the solder resist 1 in the hatched portion, thereby limiting the range for blocking the resin to be sealed. . In the shape in this range, it is preferable to provide an R at a corner when mechanically cutting. When this range is small, a circle may be used. The manufacturing method of the bonding pad 7 and the surface mount component pad 5 will be described below with reference to FIGS.

【0012】先ず、絶縁基板2上のCu配線のうち、ボ
ンディングパッド7のみにAuメッキを行う製造工程を
説明する。図2において、ボンディングパッド7及び表
面実装部品パッド5のCu配線をサブトラクティブ法ま
たはアディティブ法により、配線厚を18μmに形成
し、ボンディングパッド7以外をマスクしたメッキレジ
スト10を塗布する。
First, a description will be given of a manufacturing process in which only the bonding pads 7 of the Cu wiring on the insulating substrate 2 are plated with Au. In FIG. 2, Cu wiring of the bonding pad 7 and the surface mounting component pad 5 is formed to a wiring thickness of 18 μm by a subtractive method or an additive method, and a plating resist 10 masking portions other than the bonding pad 7 is applied.

【0013】メッキレジスト10はスクリーン印刷用ま
たは液状フォトレジストインクを使用する。硬化方法と
しては、加熱乾燥型、UV硬化型があり、剥離方法とし
てアルカリ剥離型、溶剤剥離型がある。組成成分はアル
カリ剥離型では高酸価のロジン変性マレイン酸樹脂、ロ
ジン変成フェノール樹脂、ノボラックフェノール樹脂、
アクリル共重合体、スチレン・マレイン酸樹脂などを使
用し、溶剤剥離型では、ゴム系の樹脂、塩素化ボリオレ
フィヒン、クマロン樹脂などを使用する。
The plating resist 10 uses a screen printing or liquid photoresist ink. As a curing method, there are a heat drying type and a UV curing type, and as a peeling method, there are an alkali peeling type and a solvent peeling type. The composition component is a high acid value rosin-modified maleic resin, a rosin-modified phenol resin, a novolak phenol resin,
Acrylic copolymers, styrene / maleic acid resins, etc. are used. For the solvent stripping type, rubber-based resins, chlorinated polyolefin, cumarone resins, etc. are used.

【0014】次に、下地Niメッキ及びAuメッキを行
うことでボンディングパッド7のみに下地Niメッキ1
1及びAuメッキ12を形成する。Niメッキは改良ワ
ット浴、硫酸浴、スルファミンサン浴などによって行
う。Auメッキはハードゴールド浴、ソフトゴールド浴
があるが、ボンディング用として、電導塩にリン塩酸あ
るいはクエン酸を使用したソフトゴールド浴を採用す
る。メッキ厚はNi5μm、Au0・5μm以上に形成
する。Auメッキ後、メッキレジスト10を剥離する。
絶縁基板2は、組立時にボンディング工程があることか
ら、耐熱ガラスエポキシ、ガラスポリイミド、ビスマレ
イドトリアジン等、高ガラス転移温度の材料を使用す
る。
Next, the underlying Ni plating 1 is applied only to the bonding pad 7 by performing the underlying Ni plating and Au plating.
1 and Au plating 12 are formed. Ni plating is performed by a modified Watts bath, a sulfuric acid bath, a sulfamine sun bath, or the like. Au plating includes a hard gold bath and a soft gold bath. For bonding, a soft gold bath using phosphoric acid or citric acid as a conductive salt is employed. The plating thickness is 5 μm for Ni and 0.5 μm for Au. After Au plating, the plating resist 10 is peeled off.
The insulating substrate 2 is made of a material having a high glass transition temperature, such as heat-resistant glass epoxy, glass polyimide, and bismaleid triazine, since there is a bonding step during assembly.

【0015】続いて、表面実装部品パッド5、ピン挿入
型部品用スルーホール3など、はんだコートが必要な箇
所のみにはんだコートを施す製造工程を説明する。図3
の表面実装部品パッド5、ピン挿入型部品用スルーホー
ル3など、はんだコートを行う箇所以外をマスクしたソ
ルダレジスト1を塗布し、ばんだレベラ等、一括したは
んだコート13を行う。ソルダレジスト1は、スクリー
ン印刷または感光性レジストを使った写真法があり、材
質はべ一スポリマに主として加熱硬化型エポキシ樹脂
系、紫外線硬化型アクリレート系樹脂を使用する。はん
だコート13は、はんだレベラにより一括して行う。は
んだレベラでは、プリント配線基板をプレヒート後、は
んだディップ槽ではんだ付けし、エアーナイフで余分な
はんだを除去する。
Next, a description will be given of a manufacturing process in which a solder coat is applied only to a portion requiring a solder coat, such as the surface mount component pad 5 and the through hole 3 for a pin insertion type component. FIG.
A solder resist 1 masking portions other than the portions where solder coating is to be performed, such as the surface mounting component pads 5 and the through holes 3 for pin insertion components, is applied, and a batch solder coating 13 such as a bump leveler is performed. The solder resist 1 includes a screen printing method or a photographic method using a photosensitive resist. The material is a base polymer mainly composed of a heat-curable epoxy resin or an ultraviolet-curable acrylate resin. The solder coating 13 is performed collectively by a solder leveler. In the solder leveler, after pre-heating the printed wiring board, it is soldered in a solder dipping bath, and excess solder is removed with an air knife.

【0016】次に、ボンディングパッドを表面に露出さ
せ、かつベアチップ部品を封止する樹脂の塗布範囲を制
限する為の段差を持たせる製造工程を図4を参照して説
明する。図4のソルダレジスト1に樹脂を塗布する範囲
に切削加工を行い、ボンディングパッドのAuメッキ1
2を露出させ、プリント配線基板の製造工程を完了す
る。切削加工には、座ぐり加工に一般的に用いる、ドリ
ル状の刃先を回転させて切削範囲を水平移動するタイプ
のものを用いる。
Next, a manufacturing process for exposing the bonding pad to the surface and providing a step for limiting the application range of the resin for sealing the bare chip component will be described with reference to FIG. A cutting process is performed in a range where the resin is applied to the solder resist 1 shown in FIG.
2 are exposed, and the manufacturing process of the printed wiring board is completed. For the cutting, a type generally used for spot facing, in which a drill-shaped cutting edge is rotated and a cutting range is horizontally moved, is used.

【0017】本発明において製造したプリント配線基板
に部品を実装した状態の断面図が図5に示されている。
通常、ベアチップ部品14の実装は、部品保護、機械的
保持のために樹脂封止を行うが、封止樹脂16は半練り
状で塗布するため、その塗布範囲は自重により平面上に
拡大する。本発明では、樹脂封止の塗布範囲9を、凹形
状に座ぐり加工することで、その段差が樹脂ダムの働き
をするため、封止樹脂16の塗布範囲が自動的に制御で
きる。
FIG. 5 is a sectional view showing a state where components are mounted on the printed wiring board manufactured in the present invention.
Normally, when mounting the bare chip component 14, resin sealing is performed for component protection and mechanical holding. However, since the sealing resin 16 is applied in a semi-pulverized state, the application range expands on a plane due to its own weight. In the present invention, the application range 9 of the resin sealing is formed into a concave shape by counterbore processing, so that the step acts as a resin dam, so that the application range of the sealing resin 16 can be automatically controlled.

【0018】ベアチップ部品14の搭載には、接着剤、
導体ぺ一ストなどを使用する。図5はワイヤボンディン
グの場合で、φ30μm程度のAu線を用い、ボンディ
ングには熱、圧力、超音波を併用して接続する。封止樹
脂16には吸湿性の低いエポキシ系樹脂、フェノール系
樹脂が使われる。表面実装用部品17は印刷法またはデ
ィスペンス法によりクリームはんだを供給し、部品を搭
載した後、リフローを行う。クリームはんだの組成とし
ては、Sn(すず)60%−Pb(鉛)40%、Sn6
3%一Pb37%共晶が汎用で、表面実装用部品17の
Ag−Pd(パラジウム)電極のAg食われを防止する
ためにSn62%−Ag2%−Pb36%のものなどを
使用する‘
For mounting the bare chip component 14, an adhesive,
Use conductor paste. FIG. 5 shows a case of wire bonding, in which an Au wire having a diameter of about 30 μm is used, and bonding is performed by using heat, pressure, and ultrasonic waves together. As the sealing resin 16, an epoxy resin or a phenol resin having low hygroscopicity is used. The surface mounting component 17 supplies cream solder by a printing method or a dispensing method, and after mounting the component, reflow is performed. The composition of the cream solder is as follows: Sn (tin) 60% -Pb (lead) 40%, Sn6
A 3% -Pb 37% eutectic is commonly used, and a material such as Sn 62% -Ag 2% -Pb 36% is used to prevent the Ag-Pd (palladium) electrode of the surface mounting component 17 from being eroded by Ag.

【0019】次に他の実施形態について説明する。この
実施形態が上述実施形態と異なる工程は、ソルダレジス
トを塗布する工程と、樹脂の封止範囲を制限する為に段
差を加工する工程である。
Next, another embodiment will be described. The steps in which this embodiment is different from the above-described embodiments are a step of applying a solder resist and a step of processing a step to restrict the sealing range of the resin.

【0020】本実施形態のソルダレジストを塗布する工
程が図6に示されている。2種類のソルダレジスト18
を図6に示すように塗布する。次に、ボンディングパッ
ドを露出させる工程では、異なるレジスト材を使用した
ことで選択加工が可能であり、はんだコート13を行っ
た後にソルダレジスト18のみ剥離を行い、上述実施形
態と同様な構造を得ることができる。
FIG. 6 shows a process of applying a solder resist according to the present embodiment. Two types of solder resist 18
Is applied as shown in FIG. Next, in the step of exposing the bonding pad, it is possible to perform selective processing by using a different resist material. After the solder coat 13 is performed, only the solder resist 18 is peeled off to obtain a structure similar to the above-described embodiment. be able to.

【0021】上述実施形態によれば、表面実装パッドは
Auメッキが施されていないため、AuとSn/Pbに
よる合金生成が生じることがなく、はんだ付けの信頼性
が向上する。また、予備はんだを施すので、リフロ−で
のチップ立ちの抑制、はんだ濡れ性の向上により、信頼
性及び生産性が向上する。更に、ベアチップ部品を封止
する樹脂の塗布範囲を最小限にできるため、ベアチップ
部品の近傍に部品を搭載することが可能になり、実装密
度を向上することができる。
According to the above-described embodiment, since the surface mounting pad is not plated with Au, no alloy is generated by Au and Sn / Pb, and the reliability of soldering is improved. Further, since the preliminary soldering is performed, reliability and productivity are improved by suppressing chip standing during reflow and improving solder wettability. Furthermore, since the application range of the resin for sealing the bare chip component can be minimized, the component can be mounted near the bare chip component, and the mounting density can be improved.

【0022】以上、本発明のプリント配線基板の製造方
法及びプリント配線基板の好適実施形態を説明したが、
しかし、本発明はかかる特定実施形態のみに限定される
べきではなく、特定用途に応じて種々の変形変更が可能
であることが当業者には容易に理解されよう。従って、
本発明にはかかる変形変更をも包含する。
The preferred embodiments of the method for manufacturing a printed wiring board and the printed wiring board according to the present invention have been described above.
However, those skilled in the art will readily understand that the present invention is not limited to only such specific embodiments, and that various modifications and alterations are possible in accordance with specific applications. Therefore,
The present invention includes such modifications.

【0023】[0023]

【発明の効果】以上説明したように、本発明のプリント
配線基板の製造方法及びプリント配線基板によれば、ベ
アチップ部品、表面実装部品、ピン挿入型部品が混在
し、高密度化、電気的特性の向上を図ることができる。
As described above, according to the method for manufacturing a printed wiring board and the printed wiring board of the present invention, bare chip parts, surface mount parts, and pin insertion parts are mixed, and high density and electrical characteristics are obtained. Can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施形態によるプリント配線基板の製
造方法を説明するためのベアチップ部品、表面実装部
品、オイン挿入型部品の混在実装用ブリント配線基抜上
面図である。
FIG. 1 is a top plan view of a printed wiring board according to an embodiment of the present invention, with bare chip base for mixed mounting of bare chip components, surface mount components, and oin insertion type components.

【図2】本発明の実施形態によるプリント配線基板の製
造方法を説明するためのボンディングパッドのAuメッ
キ工程図(断面位置8基板断面図)である。
FIG. 2 is a view showing a step of Au plating of a bonding pad (cross-sectional position 8 substrate cross-sectional view) for explaining the method of manufacturing a printed wiring board according to the embodiment of the present invention.

【図3】本発明の実施形態によるプリント配線基板の製
造方法を説明するためのはんだコート工程図である。
FIG. 3 is a solder coating process diagram for explaining a method of manufacturing a printed wiring board according to an embodiment of the present invention.

【図4】本発明の実施形態によるプリント配線基板の製
造方法を説明するための封止樹脂塗布範囲の切削工程図
である。
FIG. 4 is a view illustrating a process of cutting a sealing resin application range for describing a method of manufacturing a printed wiring board according to an embodiment of the present invention.

【図5】本発明の実施形態によるプリント配線基板部品
実装図である。
FIG. 5 is a printed circuit board component mounting diagram according to the embodiment of the present invention.

【図6】本発明の実施形態によるプリント配線基板の製
造方法を説明するためのソルダレジスト塗布図である。
FIG. 6 is a solder resist application diagram for explaining a method of manufacturing a printed wiring board according to an embodiment of the present invention.

【図7】従来のプリント配線基板の製造方法を説明する
ための基板上面図である。
FIG. 7 is a board top view for explaining a conventional method for manufacturing a printed wiring board.

【図8】従来のプリント配線基板の製造方法を説明する
ための基板断面図である。
FIG. 8 is a cross-sectional view of a substrate for describing a conventional method of manufacturing a printed wiring board.

【符号の説明】[Explanation of symbols]

1,18 ソルダレジスト 2 絶縁基板 3 ピン挿入型部品用スルーホール 4 回路配線 5 表面実装部品パッド 6 接続用スルーホール及びランド 7 ボンディングパッド 8 切断位置 9 封止樹脂塗布範囲 l0 メッキレジスト l1 下地Niメッキ 12 Auメッキ層 13 はんだコート 14 ベアチップ部品 15 Auワィヤ 16 封止樹脂 17 表面実装用部品 19 Ni+Auメッキ層 1, 18 Solder resist 2 Insulating board 3 Through hole for pin insertion type component 4 Circuit wiring 5 Surface mount component pad 6 Connection through hole and land 7 Bonding pad 8 Cutting position 9 Sealing resin coating range 10 Plating resist 11 Ni plating under ground 12 Au plating layer 13 Solder coat 14 Bare chip component 15 Au wire 16 Sealing resin 17 Surface mounting component 19 Ni + Au plating layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】ベアチップ部品とはんだ付け部品を混在実
装するプリント配線基板の製造方法において、 絶縁基板上に形成された回路配線にメッキレジストを塗
布し、ボンディングパッドにメッキを施す工程と、前記
メッキレジストを剥離し、はんだ付け部品パッド以外に
ソルダレジストを塗布し、はんだコートを施す工程と、
前記ベアチップ部品を封止する樹脂の塗布範囲について
切削加工を行い、ボンディングパッドを露出させ、前記
塗布範囲に段差をつける工程とを備えて成ることを特徴
とするプリント配線基板の製造方法。
1. A method of manufacturing a printed wiring board in which bare chip components and soldered components are mixedly mounted, wherein a plating resist is applied to circuit wiring formed on an insulating substrate, and a bonding pad is plated. Removing the resist, applying a solder resist other than the soldering component pads, and applying a solder coat;
Performing a cutting process on an application range of the resin for sealing the bare chip component, exposing a bonding pad, and providing a step in the application range.
【請求項2】前記メッキレジストを剥離した後、剥離方
法の異なる2種類のソルダレジストを使用し、一方のソ
ルダレジストを剥離して、ボンディングパッドを露出さ
せ、同時に塗布範囲に段差をつける工程を有する請求項
1に記載のプリント配線基板の製造方法。
2. A method of removing the plating resist, using two types of solder resists having different peeling methods, removing one of the solder resists, exposing a bonding pad, and simultaneously forming a step in a coating range. The method for manufacturing a printed wiring board according to claim 1.
【請求項3】前記メッキはNi及びAuメッキである請
求項1に記載のプリント配線基板。
3. The printed wiring board according to claim 1, wherein said plating is Ni and Au plating.
【請求項4】ベアチップ部品とはんだ付け部品を混在実
装するプリント配線基板であり、ボンディングパッドに
Auメッキが、前記はんだ付け部品にはんだコートが施
され、前記ベアチップ部品を封止する樹脂の塗布範囲を
制限する構造を有することを特徴とするプリント配線基
板。
4. A printed wiring board on which bare chip components and soldered components are mixedly mounted, wherein Au plating is applied to bonding pads, solder coating is applied to the soldered components, and a resin application area for sealing the bare chip components. A printed wiring board, having a structure for limiting the size of the printed circuit board.
JP11763797A 1997-04-21 1997-04-21 Manufacture of printed wiring board and printed wiring board Pending JPH10294549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11763797A JPH10294549A (en) 1997-04-21 1997-04-21 Manufacture of printed wiring board and printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11763797A JPH10294549A (en) 1997-04-21 1997-04-21 Manufacture of printed wiring board and printed wiring board

Publications (1)

Publication Number Publication Date
JPH10294549A true JPH10294549A (en) 1998-11-04

Family

ID=14716640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11763797A Pending JPH10294549A (en) 1997-04-21 1997-04-21 Manufacture of printed wiring board and printed wiring board

Country Status (1)

Country Link
JP (1) JPH10294549A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100407413C (en) * 2002-10-11 2008-07-30 精工爱普生株式会社 Circuit substrate, installing structure of solder ball network display and electro-light device
JP2009099799A (en) * 2007-10-17 2009-05-07 Phoenix Precision Technology Corp Package board and its manufacturing method
JP2010109104A (en) * 2008-10-29 2010-05-13 Kyocer Slc Technologies Corp Wiring board, and method of manufacturing the same
US8067698B2 (en) 2008-02-13 2011-11-29 Panasonic Corporation Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100407413C (en) * 2002-10-11 2008-07-30 精工爱普生株式会社 Circuit substrate, installing structure of solder ball network display and electro-light device
JP2009099799A (en) * 2007-10-17 2009-05-07 Phoenix Precision Technology Corp Package board and its manufacturing method
US8067698B2 (en) 2008-02-13 2011-11-29 Panasonic Corporation Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
JP2010109104A (en) * 2008-10-29 2010-05-13 Kyocer Slc Technologies Corp Wiring board, and method of manufacturing the same

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