JP2009099799A - Package board and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high-density wiring and fine pitch without arranging an electrically-plated conductor, to improve a bonding property to a gold wire of wire bonding junction, and to respond to usage of a high pin number of a fine pitch. <P>SOLUTION: A package board includes: two facing chip arrangement side and solder ball arrangement side; a plurality of wire bonding pads 401 and a plurality of solder ball pads 402 on the respective sides; and a first insulation protective layer and a second insulation protective layer on the chip arrangement side and the solder ball arrangement side, respectively. The package board includes: a board body on which a plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads are opened on the first and second insulation protective layers, respectively; chemically-plated metal layers 42 formed on the surfaces of the wire bonding pads and the solder ball pads; and a wire bonding metal layer 45 formed on the surface of the chemically-plated metal layer 42 on the wire bonding pads. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a package substrate and a manufacturing method thereof, and more particularly to a package substrate structure in which a wire bonding metal layer is formed on a wire bonding pad and a manufacturing method thereof.

  With the development of the electronic industry, research and development of electronic products are gradually progressing toward multifunction and high performance. In order to meet the requirements for high integration and miniaturization of semiconductor packages, the package substrate on which the semiconductor chip is mounted is changing from a single-layer board to a multi-layer board. In this space, the circuit area that can be used on the package substrate is increased by an interlayer connection technique to meet the demand for using an integrated circuit having a high density of electronic elements.

  Conventionally, as a package substrate for mounting a semiconductor chip, a wire bonding type package substrate, a chip size package (CSP) substrate, a flip chip ball grid array (FCBGA) substrate, or the like is used. ing. The circuit board on which the circuit is wired needs to improve its functions such as chip signal transmission, bandwidth improvement, impedance control, etc. as required by microprocessors, chipsets and graphics chips. It corresponds to the development of I / O number package. However, circuit boards are being developed into fine circuits and small diameters in accordance with the development direction of light and thin semiconductor packages, multifunction, high speed and high frequency. In the current circuit board manufacturing method, the circuit size, for example, line width, line pitch, etc. is reduced from the conventional 100 micron (μm) to 25 micron (μm) or less, and further development of smaller line accuracy is achieved. Progressing.

  1A and 1B are sectional views showing a manufacturing method for forming a wire bonding metal layer on a wire bonding pad of a conventional package substrate. First, a substrate body 10 is prepared, a plurality of wire bonding pads 101 are provided on at least one surface of the substrate body 10, and an electroplating lead wire 102 is provided on the wire bonding pad 101. An insulating protective layer 11 is formed on the pad 101, and a plurality of insulating protective layer openings 110 are formed in the insulating protective layer 11, so that a part of each surface of the wire bonding pad 101 and the substrate body 10 is formed. Are exposed (eg, as shown in FIG. 1A). By using the electroplating lead 102 as a current conduction route, a wire bonding metal layer 12 made of, for example, nickel / gold is formed on the wire bonding pad 101 (for example, shown in FIG. 1B).

  However, in order to form the wire bonding metal layer 12 on the wire bonding pad 101 by electroplating with the electroplating conductor 102, it is necessary to wire the electroplating conductor 102 on the substrate body 10. The area of 10 is occupied by that amount, and a fine pitch between the high density wiring and the wire bonding pad may not be achieved.

  2A and 2B show cross-sectional views of another manufacturing method for forming a wire bonding metal layer on a wire bonding pad of a conventional package substrate. First, a substrate body 20 is prepared, and a plurality of wire bonding pads 201 are provided on at least one surface of the substrate body 20, and an insulating protective layer 21 is formed on the substrate body 20 and the wire bonding pads 201. By forming a plurality of insulating protective layer openings 210 in the protective layer 21, a part of each surface of the wire bonding pad 201 and the substrate body 20 is exposed (for example, shown in FIG. 2A). A wire bonding metal layer 22 is formed on the wire bonding pad 201 by chemical vapor deposition (eg, as shown in FIG. 2B).

  The above-described chemical vapor deposition method can form the wire bonding metal layer 22 on the wire bonding pad 201. However, in order to obtain the wire bonding metal layer 22 having a sufficient thickness, the manufacturing cost is high, and the chemical vapor deposition is performed. Since the quality of the wire bonding metal layer 22 formed by the phase deposition is soft and the bonding property with the gold wire of the subsequent wire bonding bonding is inconvenient, it may be disadvantageous for the use of a high pin count.

  3A to 3H show a manufacturing method in which a wire bonding metal layer is formed on a wire bonding pad by electroplating using a non-plating conductive wire (NPL) manufacturing method. First, the substrate body 30 having a plurality of wire bonding pads 301 on the surface is prepared. A conductive layer 32 (for example, shown in FIG. 3B) is formed on a part of the surface of the substrate body 30 and the wire bonding pad 301. A first resist layer 33a is formed on the conductive layer 32, and a first opening 330a is formed in the first resist layer 33a, so that the conductive layer 32 in the region of the wire bonding pad 301 is exposed. (For example, as shown in FIG. 3C). The conductive layer 32 in the first opening 330a is removed (for example, as shown in FIG. 3D). A second resist layer 33b is formed in the first resist layer 33a and the first opening 330a thereof, and a second opening 330b is formed in the second resist layer 33b, whereby the wire bonding pad 301 is formed. Is exposed and covers the conductive layer 32 not covered by the first resist layer 33a in the first opening 330a (for example, as shown in FIG. 3E). The conductive layer 32 is electrically connected to the wire bonding pad 301, and a wire bonding metal layer 34 is formed on the wire bonding pad 301 in the second opening 330B by electroplating with the conductive layer 32 (eg, FIG. 3F). To show). By removing the second resist layer 33b, the first resist layer 33a, and the conductive layer 32 covered thereby, the wire bonding pad 301 and the wire bonding metal layer 34 thereon are exposed (for example, (Shown in FIG. 3G). An insulating protective layer 35 is formed on the wire bonding metal layer 34, and an insulating protective layer opening 350 is formed in the insulating protective layer 35, so that the wire bonding metal layer 34 on the wire bonding pad 301 is exposed. (Shown in FIG. 3H).

  In the NPL manufacturing method described above, the wire bonding metal layer 34 having a sufficient thickness is obtained by electroplating because the cost is lower than that of chemical vapor deposition and the quality of the wire bonding metal layer 34 formed by electroplating is hard. Although the bonding property with the gold wire in the subsequent wire bonding is improved, the manufacturing cost increases because the steps of the manufacturing method are complicated. In addition, since the insulating protective layer 35 is formed after the wire bonding metal layer 34, the wire bonding metal layer 34 is easily contaminated, which affects the quality of the subsequent wire bonding.

  Therefore, a package substrate structure capable of forming a wire bonding metal layer on the wire bonding pad and improving the connectivity required for the use of a fine pitch between the high density wiring and the wire bonding pad and a high pin count. And methods have become very important issues to be solved in the industry.

  Then, in view of the circumstances as described above, an object of the present invention is to provide a package substrate that can achieve a fine pitch between high-density wiring and wire bonding pads, and a manufacturing method thereof.

  In addition, the present invention is advantageous for the use of a high pin count with a fine pitch, and therefore provides a package substrate and a method for manufacturing the same that can improve the bondability between wire bonding and a gold wire. Objective.

  In order to solve the above-described problems, a package substrate according to the present invention has two opposing chip placement sides and solder ball placement sides, and a plurality of wire bonding pads on each of the chip placement side and the solder ball placement side. And a plurality of solder ball pads, each having a first insulating protective layer and a second insulating protective layer on each of the chip arrangement side and the solder ball arrangement side, and the first and second insulation protective layers. A substrate body on which a plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads are respectively exposed, and on the surfaces of the wire bonding pads and the solder ball pads Provided chemical plating metal layer and wire bonding metal layer provided on the surface of the chemical plating metal layer on the wire bonding pad , And a.

  According to the structure described above, the chemical plating metal layer is one of nickel / gold (Ni / Au) and nickel / palladium / gold (Ni / Pd / Au), and gold (Au) is It is formed in the outermost layer. The wire bonding metal layer is an electroplated metal, and the wire bonding metal layer is gold (Au).

In the present invention, a method for manufacturing a package substrate is further provided. A substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of chip placement sides and solder ball placement sides are provided. A wire bonding pad and a plurality of solder ball pads are provided, and a first insulating protective layer and a second insulating protective layer are formed on each of the chip arrangement side and the solder ball arrangement side, and the first and second insulation layers are formed. Forming a plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads to each of the protective layers;
Forming a chemically plated metal layer on the surface of the wire bonding pad and solder ball pad;
Forming a first conductive layer on the first insulating protective layer and the chemically plated metal layer of the wire bonding pad;
Forming a first resist layer on the first conductive layer, and exposing a first conductive layer in the wire bonding pad region to the first resist layer on the chip arrangement side of the substrate body. A first opening is formed, the first opening is larger than the first opening, and the first resist layer is provided in the first opening so as to cover a part of the first conductive layer. And having an extension on the wire bonding pad;
Exposing the chemically plated metal layer on the wire bonding pad by removing the first conductive layer in the first opening;
Forming a wire bonding metal layer on the surface of the chemical plating metal layer on the wire bonding pad by electroplating;
Removing the first resist layer and the first conductive layer covered thereby, exposing the first insulating protective layer and the wire bonding metal layer on the wire bonding pad in the first opening; It is equipped with.

  According to the manufacturing method described above, the chemical plating metal layer is one of nickel / gold (Ni / Au) and nickel / palladium / gold (Ni / Pd / Au), and gold (Au). Is formed in the outermost layer. The method for forming the first conductive layer is one of chemical deposition and physical deposition, the first conductive layer is copper (Cu), and the wire bonding metal layer is gold (Au). .

  According to the manufacturing method described above, the method further includes the step of forming the second conductive layer on the chemical plating metal layer of the second insulating protective layer and the solder ball pad.

Furthermore, in the present invention, a method for manufacturing a package substrate is provided, and a substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of each is provided on each of the chip placement side and the solder ball placement side. A wire bonding pad and a plurality of solder ball pads, and a first insulating protective layer and a second insulating protective layer are formed on the chip arrangement side and the solder ball arrangement side, respectively. Forming a plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads in each of the insulating protective layers;
Forming a chemically plated metal layer on the surface of the wire bonding pad and solder ball pad;
Forming a first conductive layer on the first insulating protective layer and the chemically plated metal layer of the wire bonding pad;
Forming a first resist layer on the first conductive layer, and exposing a first conductive layer in the wire bonding pad region to the first resist layer on the chip arrangement side of the substrate body. Forming a first opening and making the first opening smaller than the first opening to cover a portion of the first conductive layer on the wire bonding pad;
Exposing the chemically plated metal layer on the wire bonding pad by removing the first conductive layer in the first opening;
Forming a third resist layer on the first resist layer on the chip arrangement side of the substrate body and exposing the chemical plating metal layer on the wire bonding pad to the third resist layer; Forming a smaller third opening;
Forming a wire bonding metal layer on the surface of the chemical plating metal layer on the wire bonding pad by electroplating;
Wire bonding on the wire bonding pad in the first insulating protective layer and the first opening by removing the third resist layer, the first resist layer, and the first conductive layer covered thereby. Exposing the metal layer.

  According to the manufacturing method described above, the chemical plating metal layer is one of nickel / gold (Ni / Au) and nickel / palladium / gold (Ni / Pd / Au), and gold (Au). Is formed in the outermost layer. The method for forming the first conductive layer is one of chemical deposition and physical deposition, the first conductive layer is copper (Cu), and the wire bonding metal layer is gold (Au). .

  Moreover, according to the manufacturing method mentioned above, the process of forming a 2nd conductive layer on the chemical plating metal layer of this 2nd insulation protective layer and a solder ball pad is further provided.

Furthermore, in the present invention, a method for manufacturing a package substrate is provided, and a substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of each is provided on each of the chip placement side and the solder ball placement side. A wire bonding pad and a plurality of solder ball pads, and a first insulating protective layer and a second insulating protective layer are formed on the chip arrangement side and the solder ball arrangement side, respectively. A plurality of first openings and a plurality of second openings for exposing the wire bonding pads and the solder ball pads are formed in each of the insulating protective layers, and the substrate body further electrically connects the wire bonding pads. Having a plurality of electroplating conductors for connection to,
Forming a chemically plated metal layer on the surface of the wire bonding pad and solder ball pad;
Forming a second resist layer on the chemically plated metal layer on the solder ball pad in the second insulating protective layer and the second opening;
Forming a wire bonding metal layer by electroplating on the surface of the chemical plating metal layer on the wire bonding pad with the electroplating lead; and
Removing the second resist layer to expose the chemical plating metal layer on the solder ball pad in the second insulating protective layer and the second opening.

  According to the manufacturing method described above, the chemical plating metal layer is one of nickel / gold (Ni / Au) and nickel / palladium / gold (Ni / Pd / Au), and gold (Au). Is formed in the outermost layer. The wire bonding metal layer is gold (Au).

  In the package substrate and the manufacturing method thereof according to the present invention, the first and second insulating protective layers are respectively formed on the chip arrangement side and the solder ball arrangement side of the substrate body, and then the chemical plating is performed on the wire bonding pad. Since the metal layer and the wire bonding metal layer of electroplated gold are sequentially formed, the thickness of the gold layer is thicker than the solder ball pad by the thickness of the gold layer of the metal layer formed by chemical plating. By making the quality of the material harder than that of the chemically plated metal, it is possible to improve the bondability with the gold wire of the subsequent wire bonding joint, and according to the two types of manufacturing methods of the present invention, the electroplating lead wire Without using a fine pitch between the high-density wiring and the wire bonding pad.

  In the following, specific embodiments of the present invention will be described with reference to specific embodiments. Those skilled in the art can easily understand the other advantages and effects of the present invention described in the specification.

[First Embodiment]
4A to 4G schematically show a first embodiment of a manufacturing method of a package substrate according to the present invention.

  As shown in FIG. 4A, first, a substrate body 40 having two opposing chip arrangement sides 40a and solder ball arrangement sides 40b is prepared. Each of the chip placement side 40a and the solder ball placement side 40b has a plurality of wire bonding pads 401 and a plurality of solder ball pads 402, and each of the chip placement side 40a and the solder ball placement side 40b has a first insulation protection. A layer 41a and a second insulating protective layer 41b are formed, and the wire bonding pad 401 and the solder ball pad 402 are exposed to the first insulating protective layer 41a and the second insulating protective layer 41b, respectively. A plurality of first openings 410a and a plurality of second openings 410b are formed. Since the technology of the substrate body manufacturing method is very frequent and well known in the industry, it is not the main technical feature of the present application and will not be described in detail here.

  As shown in FIG. 4B, a chemical plating metal layer 42 is formed on the surfaces of the wire bonding pad 401 and the solder ball pad 402 by chemical deposition. The chemical plating metal layer 42 is one of nickel / gold (Ni / Au) and nickel / palladium / gold (Ni / Pd / Au), and gold (Au) is formed in the outermost layer.

  As shown in FIGS. 4C and 4Ca, a first conductive layer 43a made of copper (Cu) is formed on the chemical plating metal layer 42 of the first insulating protective layer 41a and the wire bonding pad 401, and the second A second conductive layer 43b is formed on the insulating protection layer 41b and the chemical plating metal layer 42 of the solder ball pad 402 (for example, as shown in FIG. 4C). Alternatively, the first conductive layer 43a is formed only on the chemical plating metal layer 42 of the first insulating protective layer 41a and the wire bonding pad 401, and the chemical plating of the second insulating protective layer 41b and the solder ball pad 402 is performed. A conductive layer is not formed on the metal layer 42 (for example, shown in FIG. 4Ca). The method for forming the first and second conductive layers 43a and 43b is chemical deposition or physical deposition.

  As shown in FIGS. 4D and 4Da, FIG. 4Da is a perspective sectional view corresponding to FIG. 4D. Next, a first resist layer 44a is formed on the first conductive layer 43a. A plurality of first openings 440a for exposing each of the first conductive layers 43a in the region of the wire bonding pads 401 is formed in the first resist layer 44a on the chip arrangement side 40a of the substrate body 40, The first opening 440a is larger than the first opening 410a, and the first resist layer 44a is provided in the first opening 440a so as to cover a part of the first conductive layer 43a. And an extending portion 441 a located on the wire bonding pad 401. A second resist layer 44b is formed on the second conductive layer 43b. According to the structure shown in FIG. 4Ca, the second resist layer 44b is formed on the second insulating protective layer 41b and the chemical plating metal layer 42 of the solder ball pad 402. The first and second resist layers 44a and 44b may be a dry film or a photoresist layer such as a liquid photoresist (Photoresist), and the first conductive layer may be printed by a method such as printing, spin coating, or bonding. 43a and the second conductive layer 43b are formed, and then patterned by exposure and development, whereby a first opening 440a for exposing a part of the surface of the first conductive layer 43a is formed in the first resist. The layer 44a is formed.

  As shown in FIG. 4E, by removing the first conductive layer 43a in the first opening 440a, the chemical plating metal layer 42 on the wire bonding pad 401 is exposed.

  Thereafter, as shown in FIG. 4F, a wire bonding metal layer 45 made of gold (Au) is formed on the surface of the chemical plating metal layer 42 on the wire bonding pad 401 by electroplating, thereby wiring the electroplating lead wires. In this case, a fine pitch between the high-density wiring and the wire bonding pad can be achieved, and after the chemical plating metal layer 42 is formed on the wire bonding pad 401 in advance, the wire bonding metal layer 45 is formed. By improving the bondability, it is necessary to use a high pin count with a fine pitch.

  As shown in FIGS. 4G, 4Ga, and 4Gb, FIGS. 4Ga and 4Gb are perspective cross-sectional views corresponding to different directions of FIG. 4G. Finally, by removing the first resist layer 44a and the first conductive layer 43a covered thereby, the first insulating protective layer 41a and the first opening 410a on the wire bonding pad 401 are removed. By exposing the wire bonding metal layer 45 and forming a rectangular notch 450 above the wire bonding pad 401 in proximity to the end of the first insulating protective layer 41a, the wire bonding metal layer 45 forms the wire bonding pad. The chemical plating metal layer 42 on 401 is exposed. At the same time, the second resist layer 44b and the second conductive layer 43b are removed, or according to the structure shown in FIG. 4Ca, the second resist layer 44b is removed to remove the second resist layer 44b. Insulating protective layer 41b and chemical plating metal layer 42 of solder ball pad 402 are exposed.

[Second Embodiment]
5A to 5E schematically show a second embodiment of a method for manufacturing a package substrate according to the present invention.

  As shown in FIGS. 5A and 5Aa, first, the structure shown in FIG. 4C of the embodiment is prepared, and a first resist layer 44a is formed on the first conductive layer 43a, and the first resist layer 44a is formed. Forming a plurality of first openings 440a to expose the first conductive layer 43a in the region of the wire bonding pad 401, and the first openings 440a are formed as first openings of the first insulating protective layer 41a. By making it smaller than 410a, a part of the first conductive layer 43a on the wire bonding pad 401 is covered, and a second resist layer 44b is formed on the second conductive layer 43b (for example, in FIG. 5A). Show). According to the structure shown in FIG. 4Ca, the second resist layer 44b is formed on the second insulating protective layer 41b and the chemical plating metal layer 42 of the solder ball pad 402 (for example, shown in FIG. 5Aa).

  As shown in FIG. 5B, by removing the first conductive layer 43a in the first opening 440a, the chemical plating metal layer 42 on the wire bonding pad 401 is exposed.

  As shown in FIGS. 5C and 5Ca, FIG. 5Ca is a perspective sectional view of FIG. 5C. The wire bonding pad 401 is formed by forming a third resist layer 44c on the first resist layer 44a and making the third resist layer 44c smaller than the third opening 440c of the first opening 440a. The upper chemical plating metal layer 42 is exposed to cover the first conductive layer 43a from which the first resist layer 44a is exposed.

  As shown in FIG. 5D, a wire bonding metal layer 45 is formed on the surface of the chemical plating metal layer 42 on the wire bonding pad 401 by electroplating.

  As shown in FIGS. 5E, 5Ea and 5Eb, FIGS. 5Ea and 5Eb are perspective sectional views corresponding to different directions of FIG. 5E. Finally, the first insulating protective layer 41a and the first opening 410a are removed by removing the third resist layer 44c, the first resist layer 44a, and the first conductive layer 43a covered thereby. The wire bonding metal layer 45 on the wire bonding pad 401 is exposed, and the wire bonding metal layer 45 is close to the end of the first insulating protective layer 41a to form a notch 450 ′ straddling the wire bonding pad 401. The chemical plating metal layer 42 is exposed. At the same time, the second conductive layer 43b and the second resist layer 44b are removed, or according to the structure shown in FIG. 5Aa, finally, only the second resist layer 44b is removed, The second insulating protective layer 41b and the chemical plating metal layer 42 of the solder ball pad 402 are exposed.

[Third Embodiment]
6A to 6E schematically show a third embodiment of the package substrate manufacturing method according to the present invention. The difference from the above embodiment is that the wire bonding pad is advantageous in forming a wire bonding metal layer on the wire bonding pad by electroplating by using the electroplating lead as a current conduction route of electroplating. It is.

  As shown in FIG. 6A, first, the structure shown in FIG. 4A of the above embodiment is prepared, and the wire bonding pad 401 is electrically connected to the electroplating lead wire 403.

  As shown in FIG. 6B, a chemical plating metal layer 42 is formed on the wire bonding pad 401 and the solder ball pad 402 on the chip arrangement side 40 a and the solder ball arrangement side 40 b of the substrate body 40.

  As shown in FIG. 6C, a second resist layer 44B is formed on the second insulating protective layer 41b and the chemical plating metal layer 42 in the solder ball pad 402, and a resist layer is formed on the first insulating protective layer 41a. Not formed.

  Thereafter, as shown in FIG. 6D, a wire bonding metal layer 45 made of gold (Au) is formed on the surface of the chemical plating metal layer 42 on the wire bonding pad 401 by electroplating with the electroplating lead wire 403. Since the wire-bonding metal layer 45 is formed after the chemical-plating metal layer 42 is formed on the wire-bonding pad 401 in advance, the bondability is improved and the use requirement for a high pin count with a fine pitch is met. ing.

As shown in FIG. 6E, by removing the second resist layer 44b, the second insulating protective layer 41b and the chemical plating metal layer 42 of the solder ball pad 402 are exposed.
The present invention further provides a package substrate, which has two opposed chip placement sides 40a and solder ball placement sides 40b, and each of the chip placement side 40a and the solder ball placement side 40b has a plurality of wire bonding pads. 401 and a plurality of solder ball pads 402, and each of the chip placement side 40a and the solder ball placement side 40b has a first insulation protection layer 41a and a second insulation protection layer 41b. Each of the protective layer 41a and the second insulating protective layer 41b has a plurality of first openings 410a and a plurality of second openings 410b for exposing the wire bonding pads 401 and the solder ball pads 402, respectively. A chemical plating provided on the substrate main body, the wire bonding pad 401 and the solder ball pad 402. A metal layer 42, and a, a wire bonding metal layer 45 formed on the chemical plating metal layer 42 on the wire bonding pad 401.
An electroplating lead 403 may be further electrically connected to the wire bonding pad 401. The chemical plating metal layer 42 is nickel / gold (Ni / Au) or nickel / palladium / gold (Ni / Pd / Au), and gold (Au) is provided on the outermost layer. The wire bonding metal layer 45 is an electroplated metal, and the wire bonding metal layer 45 is gold (Au).
In the package substrate and the manufacturing method thereof according to the present invention, the first and second insulating protective layers are formed in advance on the chip arrangement side and the solder ball arrangement side of the substrate body, respectively, and then the chemical plating metal is formed on the wire bonding pad. Layer and electroplating gold wire bonding metal layer are formed in sequence, so that the thickness of the gold layer is thicker than the thickness of the metal layer of the solder pole pad metal layer formed only by chemical plating. By making the quality of the material harder than that of the chemically plated metal, it is possible to improve the bondability with the gold wire of the subsequent wire bonding joint, and according to the two types of manufacturing methods of the present invention, the electroplating lead wire Without using a fine pitch between the high-density wiring and the wire bonding pad.

  As described above, these embodiments are illustrative of the principles, effects, and functions of the present invention, and the present invention is not limited thereto. The substantial technical contents of the present invention are defined in the appended claims. The present invention can be modified and changed in various ways by those skilled in the art without departing from the scope of the claims, and such modifications and changes are included in the technical scope of the present invention. .

It is sectional drawing which showed typically the manufacturing method which forms by electroplating a wire bonding metal layer with an electroplating conducting wire on the wire bonding pad of the conventional package substrate. It is sectional drawing which showed typically the manufacturing method which forms by electroplating a wire bonding metal layer with an electroplating conducting wire on the wire bonding pad of the conventional package substrate. It is sectional drawing which showed typically the manufacturing method which forms a wire bonding metal layer by chemical deposition on the wire bonding pad of the conventional package substrate. It is sectional drawing which showed typically the manufacturing method which forms a wire bonding metal layer by chemical deposition on the wire bonding pad of the conventional package substrate. It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically the manufacturing method which electroplats and forms a wire bonding metal layer on a wire bonding pad of the conventional package board | substrate by electroless-plating conducting wire (NPL). It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically other embodiment of FIG. 4C. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is the perspective view which showed the cross section of FIG. 4D typically. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 1st Embodiment of the package board | substrate concerning this invention, and its manufacturing method. It is the perspective view which showed the cross section of FIG. 4G typically. It is the perspective view which showed the cross section of FIG. 4G typically. It is sectional drawing which showed typically 2nd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed other embodiment of FIG. 5A typically. It is sectional drawing which showed typically 2nd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 2nd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is the perspective view which showed the cross section of FIG. 5C typically. It is sectional drawing which showed typically 2nd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 2nd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is the perspective view which showed the cross section of FIG. 5E typically. It is the perspective view which showed the cross section of FIG. 5E typically. It is sectional drawing which showed typically 3rd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 3rd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 3rd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 3rd Embodiment of the package substrate concerning this invention, and its manufacturing method. It is sectional drawing which showed typically 3rd Embodiment of the package substrate concerning this invention, and its manufacturing method.

Explanation of symbols

10, 20, 30, 40 Substrate body 101, 201, 301, 401 Wire bonding pad 102, 403 Electroplating lead 11, 21, 35 Insulating protective layer 110, 210, 350 Insulating protective layer opening 12, 22, 34, 45 Wire bonding metal layer 32 Conductive layer 33a, 44a First resist layer 330a, 440a First opening 33b, 44b Second resist layer 330b Second opening 402 Solder ball pad 40a Chip placement side 40b Solder ball placement side 41a First 1st insulating protective layer 410a 1st opening 41b 2nd insulating protective layer 410b 2nd opening 42 Chemical plating metal layer 43a 1st conductive layer 43b 2nd conductive layer 44c 3rd resist layer 440c 3rd Opening 441a extension 450 rectangular notch 450 'notch

Claims (19)

There are two opposing chip placement sides and solder ball placement sides, and each of the chip placement side and the solder ball placement side has a plurality of wire bonding pads and a plurality of solder ball pads, and the chip placement side and the solder balls A first insulating protective layer and a second insulating protective layer are formed on each of the arrangement sides, and the wire bonding pad and the solder ball pad are exposed on each of the first and second insulating protective layers. A substrate body in which a plurality of first openings and a plurality of second openings are opened;
A chemical plating metal layer provided on the surfaces of the wire bonding pad and the solder ball pad;
A wire bonding metal layer provided on the surface of the chemical plating metal layer on the wire bonding pad;
A package substrate comprising:   The package substrate according to claim 1, wherein the chemical plating metal layer is one of nickel / gold and nickel / palladium / gold, and gold is formed in an outermost layer.   The package substrate according to claim 1, wherein the wire bonding metal layer is an electroplated metal.   The package substrate according to claim 1, wherein the wire bonding metal layer is gold. A substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of wire bonding pads and a plurality of solder ball pads are provided on each of the chip placement side and the solder ball placement side, and the chip placement side And forming a first insulating protective layer and a second insulating protective layer on each of the solder ball arrangement sides, and exposing the wire bonding pad and the solder ball pad to each of the first and second insulating protective layers. Forming a plurality of first apertures and a plurality of second apertures for,
Forming a chemical plating metal layer on the surface of the wire bonding pad and the solder ball pad;
Forming a first conductive layer on the first insulating protective layer and the chemical plating metal layer of the wire bonding pad;
Forming a first resist layer on the first conductive layer, and exposing the first conductive layer in the wire bonding pad region to the first resist layer on the chip arrangement side of the substrate body. A first opening is formed, the first opening is larger than the first opening, and the first resist layer is provided in the first opening so as to cover a part of the first conductive layer. Having an extension on the wire bonding pad;
Exposing the chemically plated metal layer on the wire bonding pad by removing the first conductive layer in the first opening;
Forming a wire bonding metal layer by electroplating on the surface of the chemical plating metal layer on the wire bonding pad;
Removing the first resist layer and the first conductive layer covered therewith to expose the first insulating protective layer and the wire bonding metal layer on the wire bonding pad in the first opening; ,
A method for manufacturing a package substrate, comprising:   6. The package substrate according to claim 5, wherein the chemical plating metal layer is one of nickel / gold and nickel / palladium / gold, and gold is provided in the outermost layer. Method.   6. The method of manufacturing a package substrate according to claim 5, further comprising a step of forming a second conductive layer on the second insulating protective layer and the chemical plating metal layer of the solder ball pad.   6. The method of manufacturing a package substrate according to claim 5, wherein the method of forming the first conductive layer is one of chemical deposition and physical deposition.   The method for manufacturing a package substrate according to claim 5, wherein the first conductive layer is copper.   6. The method of manufacturing a package substrate according to claim 5, wherein the wire bonding metal layer is gold. A substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of wire bonding pads and a plurality of solder ball pads are provided on each of the chip placement side and the solder ball placement side, and the chip placement side And forming a first insulating protective layer and a second insulating protective layer on each of the solder ball arrangement sides, and exposing the wire bonding pad and the solder ball pad to each of the first and second insulating protective layers. Forming a plurality of first apertures and a plurality of second apertures for,
Forming a chemical plating metal layer on the surface of the wire bonding pad and the solder ball pad;
Forming a first conductive layer on the first insulating protective layer and the chemical plating metal layer of the wire bonding pad;
Forming a first resist layer on the first conductive layer, and exposing the first conductive layer in the wire bonding pad region to the first resist layer on the chip arrangement side of the substrate body. Forming the first opening and making the first opening smaller than the first opening so as to cover a part of the first conductive layer on the wire bonding pad;
Exposing the chemically plated metal layer on the wire bonding pad by removing the first conductive layer in the first opening;
Forming a third resist layer on the first resist layer on the chip arrangement side of the substrate body and exposing the chemical plating metal layer on the wire bonding pad to the third resist layer; Forming a smaller third opening;
Forming a wire bonding metal layer by electroplating on the surface of the chemical plating metal layer on the wire bonding pad;
Wire bonding on the wire bonding pad in the first insulating protective layer and the first opening by removing the third resist layer, the first resist layer and the first conductive layer covered thereby. Exposing the metal layer;
A method for manufacturing a package substrate, comprising:   12. The manufacturing of a package substrate according to claim 11, wherein the chemical plating metal layer is one of nickel / gold and nickel / palladium / gold, and gold is provided in the outermost layer. Method.   6. The method of manufacturing a package substrate according to claim 5, further comprising a step of forming a second conductive layer on the second insulating protective layer and the chemical plating metal layer of the solder ball pad.   The method for manufacturing a package substrate according to claim 11, wherein the method for forming the conductive layer is one of chemical deposition and physical deposition.   The method for manufacturing a package substrate according to claim 11, wherein the first conductive layer is copper.   12. The method of manufacturing a package substrate according to claim 11, wherein the wire bonding metal layer is gold. A substrate body having two opposing chip placement sides and solder ball placement sides is prepared, and a plurality of wire bonding pads and a plurality of solder ball pads are provided on each of the chip placement side and the solder ball placement side, and the chip placement side And forming a first insulating protective layer and a second insulating protective layer on each of the solder ball arrangement sides, and exposing the wire bonding pad and the solder ball pad to each of the first and second insulating protective layers. Forming a plurality of first apertures and a plurality of second apertures for the substrate body to further include a plurality of electroplating leads for electrical connection to the wire bonding pads; ,
Forming a chemical plating metal layer on the surface of the wire bonding pad and the solder ball pad;
Forming a second resist layer on the chemical plating metal layer on the solder ball pad in the second insulating protective layer and the second opening;
Forming a wire bonding metal layer by electroplating on the surface of the chemical plating metal layer on the wire bonding pad by the electroplating lead; and
Exposing the chemical plating metal layer on the solder ball pad in the second insulating protective layer and the second opening by removing the second resist layer;
A method for manufacturing a package substrate, comprising:   18. The package substrate manufacturing method according to claim 17, wherein the chemical plating metal layer is one of nickel / gold and nickel / palladium / gold, and gold is provided on the outermost layer. Method.   The method of manufacturing a package substrate according to claim 17, wherein the wire bonding metal layer is gold.

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