JPH0424923A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0424923A
JPH0424923A JP12602790A JP12602790A JPH0424923A JP H0424923 A JPH0424923 A JP H0424923A JP 12602790 A JP12602790 A JP 12602790A JP 12602790 A JP12602790 A JP 12602790A JP H0424923 A JPH0424923 A JP H0424923A
Authority
JP
Japan
Prior art keywords
wiring
interconnection
layer
semiconductor device
buried
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12602790A
Other languages
Japanese (ja)
Inventor
Mika Okumura
美香 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12602790A priority Critical patent/JPH0424923A/en
Publication of JPH0424923A publication Critical patent/JPH0424923A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve a step generated on multilayer interconnections and to flatten its surface by forming an interconnection groove in which first layer interconnection is entirely or partly buried on an insulating film under the first layer interconnection, and burying the first interconnection. CONSTITUTION:An interconnection groove 6 in which a first layer interconnection 3 can be entirely or partly buried is provided on an insulating film 2 under the interconnection 3, and the interconnection 3 is buried to alleviate a step of an interlayer insulating film 4. Further, even if a second layer interconnection 5 is crossed at the part, the flatness of a semiconductor surface is held, and the fault of the interconnection at the step can be reduced. When the interconnection 3 is buried in the groove 6 and covered with a protective film 7, a stress to be applied to the interconnection 3 can be absorbed in the manufacture of the semiconductor, and distortions of the interconnection due to a stress generated at the four corners of a semiconductor device can be alleviated.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、多層配線により生じろ段差の改善および半
導体製造過程において配線が受ける応力による歪みを緩
和した半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device that improves steps caused by multilayer wiring and alleviates distortion due to stress applied to the wiring during the semiconductor manufacturing process.

〔従来の技術〕[Conventional technology]

第5図は多層配線を有する場合の従来例を示す半導体装
置の断面図である。この図において、1は半導体基板、
2は配線下の絶縁膜、3は第1層配線、4は第1層配線
3と第2層配線の間にある層間絶縁膜、5は第2層配線
である。
FIG. 5 is a sectional view of a conventional semiconductor device having multilayer wiring. In this figure, 1 is a semiconductor substrate,
2 is an insulating film under the wiring, 3 is a first layer wiring, 4 is an interlayer insulation film between the first layer wiring 3 and the second layer wiring, and 5 is a second layer wiring.

このように構成された半導体装置において、絶縁膜2の
上に第1層配線3が堆積されており、第1層配線3が配
置される、部分はその配線の厚み(高さ)の分だけ段差
が生じる。
In the semiconductor device configured in this way, the first layer wiring 3 is deposited on the insulating film 2, and the portion where the first layer wiring 3 is arranged is equal to the thickness (height) of the wiring. A difference in level occurs.

したがって、多層配線においてもその分厚みが厚くなる
Therefore, the thickness of the multilayer wiring also increases accordingly.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の多層配線を有する半導体装置は、以上のように構
成されているので、第1層配線3が配置される部分は、
その第1層配線3の厚みの分、上層で段差が生じ、さら
にその部分に第2M配線5が交差する場合は、その段差
により第2層配線5の形成が平坦部に比べ容易でなかっ
た。
Since the conventional semiconductor device having multilayer wiring is configured as described above, the portion where the first layer wiring 3 is arranged is
If a step occurs in the upper layer due to the thickness of the first layer wiring 3 and the second M wiring 5 intersects with that portion, the formation of the second layer wiring 5 is not easier due to the step than in a flat area. .

また、上層部に配線がない一層配線のみの場合において
、半導体装置の四辺の隅に配線が受ける応力による配線
の歪み(スライド)が生じるなどの問題点があった。
Furthermore, in the case of only one layer of wiring without wiring in the upper layer, there are problems such as distortion (sliding) of the wiring due to stress applied to the wiring at the four corners of the semiconductor device.

この発明は、上記のような問題点を解消するためになさ
れたもので、多層配線により生しる段差を改善するとと
もに、応力による配線のスライド対策を施した半導体装
置を得ることを目的とする〔課題を解決するための手段
〕 この発明に係る半導体装置は、第1層配線下の絶縁膜に
、第1層配線が全部または一部分が埋設される配線溝を
形成し、この配線溝に第1層配線を埋設したものである
This invention was made in order to solve the above-mentioned problems, and aims to improve the level difference caused by multilayer wiring and to obtain a semiconductor device that takes measures against sliding of wiring due to stress. [Means for Solving the Problems] A semiconductor device according to the present invention includes forming a wiring groove in which the first layer wiring is entirely or partially buried in an insulating film under the first layer wiring, and a first layer wiring groove in which the first layer wiring is buried. One layer of wiring is buried.

〔作用〕[Effect]

この発明においては、第1層配線は下部の絶縁膜に設け
られた配線溝により、全部または部分的に埋設され、そ
の分段差が解消される。
In this invention, the first layer wiring is completely or partially buried in the wiring groove provided in the lower insulating film, and the level difference is eliminated accordingly.

また、上層部に配線がない場合も配線溝に第1層配線を
埋めることにより、その後の半導体装置の製造において
配線が受ける応力による歪み(スライド)が緩和される
Further, even when there is no wiring in the upper layer, by burying the first layer wiring in the wiring groove, strain (sliding) due to stress applied to the wiring in subsequent manufacturing of the semiconductor device is alleviated.

〔実施例〕〔Example〕

第1図はこの発明の一実施例を示す半導体装置の断面図
で、第2図は、第1図の平面図である。
FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention, and FIG. 2 is a plan view of FIG. 1.

これらの図において、1〜5は第5図に示したものと同
等のものであり、6は前記絶縁膜2に形成された配線溝
で、この配線溝6に第1層配線3が埋設される。なお、
この配線溝6の深さは第1層配線3が全部または一部分
が埋設されるように形成される。
In these figures, 1 to 5 are equivalent to those shown in FIG. 5, and 6 is a wiring groove formed in the insulating film 2, and the first layer wiring 3 is buried in this wiring groove 6. Ru. In addition,
The depth of this wiring trench 6 is formed such that the first layer wiring 3 is buried in whole or in part.

第1図のような多層配線を有する半導体装置において、
第1層配[3の下部の絶縁#2に第1層配線3を全部ま
たは部分的に埋め込むことができる配線溝6を設け、第
1層配線3を埋設することにより層間絶縁膜4の段差を
軽減し、さらに、その部分に第2層配線5が交差する場
合でも、半導体表面の平坦性が保たれ、段差部での配線
の断線を低減することができる。
In a semiconductor device having multilayer wiring as shown in FIG.
A wiring groove 6 in which the first layer wiring 3 can be completely or partially buried is provided in the insulation #2 under the first layer wiring [3, and the step difference in the interlayer insulating film 4 is formed by burying the first layer wiring 3. Further, even if the second layer wiring 5 intersects with that portion, the flatness of the semiconductor surface is maintained, and disconnection of the wiring at the stepped portion can be reduced.

第3図はこの発明の他の実施例を示す半導体装置の断面
図であり、第4図は、第3図の平面図である。この実施
例は上層部に配線のない第1層配線3だけの場合である
FIG. 3 is a sectional view of a semiconductor device showing another embodiment of the invention, and FIG. 4 is a plan view of FIG. 3. This embodiment is a case where only the first layer wiring 3 has no wiring in the upper layer.

この半導体装置においては、第1層配線3を配線溝6に
埋め込み、その上を保護膜7で覆ったものである。この
場合、その後の半導体製造において第1層配線3が受け
る応力を吸収することができ、半導体装置の四辺の隅に
発生する応力による配線の歪み(スライド)を緩和する
ことができる。
In this semiconductor device, a first layer wiring 3 is buried in a wiring trench 6 and covered with a protective film 7. In this case, the stress applied to the first layer wiring 3 during subsequent semiconductor manufacturing can be absorbed, and the distortion (sliding) of the wiring due to the stress generated at the four corners of the semiconductor device can be alleviated.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、第1層配線下の絶縁
膜に、第1層配線が全部または一部分が埋設される配線
溝を形成し、乙の配線溝に第1層配線を埋設したので、
多層配線で生じる段差を改善し、表面平坦化により半導
体装置の製造が容易となる。さらに、眉間耐圧の向上、
およびアルミマイグレーションの低減といった信頼性の
向上が得られろ効果がある。
As explained above, the present invention forms a wiring groove in which the first layer wiring is buried in whole or in part in the insulating film under the first layer wiring, and buries the first layer wiring in the wiring groove B. So,
It improves the level difference that occurs in multilayer wiring and makes the surface flattened, making it easier to manufacture semiconductor devices. In addition, improved glabellar pressure resistance,
This has the effect of improving reliability, such as reducing aluminum migration.

また、第1層配線の場合でも、(アルミ)配線のスライ
ドを防止することのできる半導体装置が得られるという
効果がある。
Further, even in the case of the first layer wiring, there is an effect that a semiconductor device that can prevent the (aluminum) wiring from sliding can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1因はこの発明の一実施例を示す半導体装置の断面図
、第2図は、第1図の平面図、第3図はこの発明の他の
実施例を示す半導体装置の断面図、第4図は、第3図の
平面図、第5図は従来の半導体装置を示す断面図である
。 は第1層配線、4は層間絶縁膜、5は第2層配線、6は
配線溝である。 なお、各図中の同一符号は同一または相当部分を示す。 代理人 大 岩 増 雄   (外2名)第 図 第 図 第 図 第 図 第 図
The first factor is a sectional view of a semiconductor device showing one embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is a sectional view of a semiconductor device showing another embodiment of the invention. 4 is a plan view of FIG. 3, and FIG. 5 is a sectional view showing a conventional semiconductor device. 4 is a first layer wiring, 4 is an interlayer insulating film, 5 is a second layer wiring, and 6 is a wiring trench. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent: Masuo Oiwa (2 others)

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上の絶縁膜上に少なくとも第1層配線が形
成された半導体装置において、前記第1層配線下の絶縁
膜に、前記第1層配線が全部または一部分が埋設される
配線溝を形成し、この配線溝に前記第1層配線を埋設し
たことを特徴とする半導体装置。
In a semiconductor device in which at least a first layer wiring is formed on an insulating film on a semiconductor substrate, a wiring groove in which the first layer wiring is buried in whole or in part is formed in the insulating film below the first layer wiring. . A semiconductor device, characterized in that the first layer wiring is buried in the wiring groove.
JP12602790A 1990-05-15 1990-05-15 Semiconductor device Pending JPH0424923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12602790A JPH0424923A (en) 1990-05-15 1990-05-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12602790A JPH0424923A (en) 1990-05-15 1990-05-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0424923A true JPH0424923A (en) 1992-01-28

Family

ID=14924883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12602790A Pending JPH0424923A (en) 1990-05-15 1990-05-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0424923A (en)

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