JPH01241117A - Alignment-mark - Google Patents
Alignment-markInfo
- Publication number
- JPH01241117A JPH01241117A JP63068421A JP6842188A JPH01241117A JP H01241117 A JPH01241117 A JP H01241117A JP 63068421 A JP63068421 A JP 63068421A JP 6842188 A JP6842188 A JP 6842188A JP H01241117 A JPH01241117 A JP H01241117A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- alignment
- wiring layer
- forming
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置製造の配線工程で使われるアライ
メント・マークに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an alignment mark used in the wiring process of manufacturing semiconductor devices.
半導体装置製造の配線工程で使われる、従来のアライメ
ント・マークは、第２図に示されるように、配】腺工程
以前に、基板２１上に形成された層間絶縁酸化膜２２−
層分の段差を有する凹部、または、凸部の上に配線層２
３が形成された構造であった。As shown in FIG. 2, the conventional alignment mark used in the wiring process of semiconductor device manufacturing is an interlayer insulating oxide film 22- formed on a substrate 21 before the wiring process.
A wiring layer 2 is placed on a concave portion or a convex portion having a level difference corresponding to the layer.
3 was formed.
しかし、前述の従来技術では、凹部、または凸部の段差
が眉間絶縁酸化膜−層分の厚さしかなく小さいために、
配線層が形成されると、第２図のように、段差は更に小
さくなり、また、段差のテーパー角も小さく、段差の上
、下部エツジが不鮮明になってしまう。これは、配線層
がより厚かったり、また、平担性の高い膜形成法により
、配線層が形成される場合、より顕著となる。従って、
このようなアライメント・マークから得られるアライメ
ント信号は、分散の大きい不明確のものとなり、アライ
メント精度が大きく低下するという課題を有している。However, in the above-mentioned conventional technology, the difference in level between the concave portion or the convex portion is small and is only the thickness of the insulating oxide film between the eyebrows.
When the wiring layer is formed, as shown in FIG. 2, the step becomes even smaller and the taper angle of the step becomes smaller, causing the upper and lower edges of the step to become unclear. This becomes more noticeable when the wiring layer is thicker or when the wiring layer is formed using a film forming method with high flatness. Therefore,
The alignment signal obtained from such an alignment mark has a problem that it has a large dispersion and is unclear, resulting in a significant decrease in alignment accuracy.
そこで本発明は、このような課題を解決するもので、そ
の目的とするところは、配線工程のアライメント精度を
大きく向上するアライメント・マ−クを提供するところ
にある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide an alignment mark that greatly improves alignment accuracy in wiring processes.
本発明のアライメント・マークは、基板上に形成、され
た第１の酸化膜の少なくとも一部と、第２の酸化膜の全
層とからなる段差を有する凹部、または、凸部の上に、
配線層が形成されたことを特徴とする。The alignment mark of the present invention is formed on a concave portion or a convex portion having a step consisting of at least a part of the first oxide film and the entire layer of the second oxide film.
A feature is that a wiring layer is formed.
第１図は、本発明の実施例におけるアライメント・マー
クの断面図である。基板１１上に、第１の酸化膜として
素子分離用酸化膜１２を形成し、更に、第２の酸化膜と
して層間絶縁酸化膜１３を形成する。次に、前記第２の
酸化膜１５に対して行なうフンタクトホール形成工程の
エラチンクラ前記第２の酸化膜１５の全層と、前記第１
の譲化膜１２の一部に及ぶまで行ない四部を形成する。FIG. 1 is a cross-sectional view of an alignment mark in an embodiment of the present invention. An element isolation oxide film 12 is formed as a first oxide film on the substrate 11, and an interlayer insulating oxide film 13 is further formed as a second oxide film. Next, the entire layer of the second oxide film 15 and the first
This process is performed until a portion of the transfer film 12 is covered to form four parts.
この時、前記第１の酸化膜１２の一部のエツチング量は
、前記第２の酸化膜１３に対するオーバー・エツチング
分に相当する。こうして形成された凹部の上に、配線層
１４が形成されて、本実施例のアライメント・マークが
得られる。At this time, the amount of etching of a portion of the first oxide film 12 corresponds to the amount of over-etching of the second oxide film 13. A wiring layer 14 is formed on the concave portion thus formed to obtain the alignment mark of this embodiment.
本実施例によれば、凹部の段差が、前記第２の敏化膜１
５のみならず、前記第１の酸化膜１２の一部にまで及び
、大きいために、第１図のようにその上に配線層１４を
形成しても、従来に比べ、段差は小さくならず、また、
段差のテーパー角も大きく、段差の上、下部エツジが鮮
明になる。According to this embodiment, the step of the concave portion is the second sensitized film 1.
5, it also extends to a part of the first oxide film 12 and is large, so even if the wiring layer 14 is formed thereon as shown in FIG. 1, the step difference will not become smaller than in the past. ,Also,
The taper angle of the step is also large, making the top and bottom edges of the step clear.
従って、このアライメント・マークから得られるアライ
メント信号は、より明確なものとなり、アライメント精
度は大きく向上する。Therefore, the alignment signal obtained from this alignment mark becomes clearer, and alignment accuracy is greatly improved.
以上、本実施例では、前記第１の酸化膜の一部にまで及
ぶ段差を有する凹部の上に配線層を形成する場合につい
て述べたが、段差が前記第１の酸化膜の全層にまで及ぶ
場合、また、形状が凸である場合についても、同様な効
果が得られる。更に、前記第１．及び第２の酸化膜とし
て、実施例以外の工程で生ずる酸化膜を用いるなど、本
発明の髪旨を逸しない範囲で種々応用が可能であること
は言うまでもない。As described above, in this embodiment, a case has been described in which a wiring layer is formed on a recess having a step extending to a part of the first oxide film. Similar effects can be obtained even when the shape is convex. Furthermore, the above-mentioned No. 1. It goes without saying that various applications are possible without departing from the spirit of the present invention, such as using an oxide film produced in steps other than those in the Examples as the second oxide film.
以上述べたように、本発明によれば、基板上に形成され
た第１の酸化膜の少なくとも一部と、第２の酸化膜の全
層とからなる段差を有する凹部、または、凸部の上に、
配線層を形成することＫより、アライメント・マークの
段差が、従来に比べ大きく、また段差のテーパー角も大
きく、段差の上、下部エツジが鮮明になる。従って、こ
のアライメント・マークから得られるアライメント信号
は、より明確なものとなり、アライメント精度が大きく
向上するという効果を有する。As described above, according to the present invention, a concave portion or a convex portion having a step consisting of at least a part of the first oxide film and the entire layer of the second oxide film formed on the substrate can be formed. above,
By forming the wiring layer, the step of the alignment mark is larger than that of the conventional method, and the taper angle of the step is also large, so that the upper and lower edges of the step are clear. Therefore, the alignment signal obtained from this alignment mark becomes clearer, which has the effect of greatly improving alignment accuracy.
更に、本発明の７ライメント・マークは、半導体装置の
製造工程中に作成され、このマーク形成用の工程を新た
に追加する必要がないため、製造工程を増やさずに、ア
ライメント精度を向上できるという優れた効果を有する
ものである。Furthermore, the 7 alignment marks of the present invention are created during the manufacturing process of semiconductor devices, and there is no need to add a new process for forming the marks, so alignment accuracy can be improved without increasing the number of manufacturing processes. It has excellent effects.
第１図は、本発明のアライメント・マークの一実施例を
示す主要断面図である。
第２図は、従来のアライメント・マークを示す主要断面
図である。
１１・・・・・・・・・基 板
１２・・・・・・・・・第１の酸化膜（素子分離用酸化
膜）１３・・・・・・・・・第２の酸化膜（層間絶縁酸
化膜）１４・・・・−・・・・配線層
２１・・・・・・・・・基 板
２２・・・・・・・・・層間絶縁酸化膜２３・・・・・
・・・・配線層
以上
出願人 セイコーエプソン株式会社FIG. 1 is a main sectional view showing an embodiment of the alignment mark of the present invention. FIG. 2 is a main cross-sectional view showing a conventional alignment mark. 11...Substrate 12...First oxide film (element isolation oxide film) 13...Second oxide film ( Interlayer insulating oxide film) 14... - Wiring layer 21... Substrate 22... Interlayer insulating oxide film 23...
...Applicant for wiring layer and above Seiko Epson Corporation
Claims (1)
と、第２の酸化膜の全層とからなる段差を有する凹部、
または、凸部の上に、配線層が形成されたことを特徴と
するアライメント・マーク。a recess formed on the substrate and having a step formed of at least a portion of the first oxide film and the entire second oxide film;
Alternatively, an alignment mark is characterized in that a wiring layer is formed on the convex portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068421A JPH01241117A (en) | 1988-03-23 | 1988-03-23 | Alignment-mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63068421A JPH01241117A (en) | 1988-03-23 | 1988-03-23 | Alignment-mark |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01241117A true JPH01241117A (en) | 1989-09-26 |
Family
ID=13373201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63068421A Pending JPH01241117A (en) | 1988-03-23 | 1988-03-23 | Alignment-mark |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01241117A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134808A (en) * | 1988-11-16 | 1990-05-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| US7265021B2 (en) | 2004-01-21 | 2007-09-04 | Seiko Epson Corporation | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| KR100771378B1 (en) * | 2006-12-22 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating the same |
| JP2011009647A (en) * | 2009-06-29 | 2011-01-13 | Oki Semiconductor Co Ltd | Semiconductor device, and method of manufacturing the same |
-
1988
- 1988-03-23 JP JP63068421A patent/JPH01241117A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02134808A (en) * | 1988-11-16 | 1990-05-23 | Fujitsu Ltd | Manufacture of semiconductor device |
| US7265021B2 (en) | 2004-01-21 | 2007-09-04 | Seiko Epson Corporation | Alignment method, method for manufacturing a semiconductor device, substrate for a semiconductor device, electronic equipment |
| KR100771378B1 (en) * | 2006-12-22 | 2007-10-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and method for fabricating the same |
| JP2011009647A (en) * | 2009-06-29 | 2011-01-13 | Oki Semiconductor Co Ltd | Semiconductor device, and method of manufacturing the same |
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