JPH0327527A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the size of a slit between wirings and relax difference in levels to enable highly accurate pattern formation by a method wherein dummy wiring is formed with insulation maintained with first layer wiring and an insulating material is filled between the first layer wiring and the dummy wiring. CONSTITUTION:First layer wiring 3 and dummy wiring 4 are formed on an insulation film 2A of a substrate 1 wherein a slit between the wirings 3,4 is made three times or less the thickness of the wiring 3. Then an insulation film 2B is formed on the wirings 3,4 and further the slit between the wirings 3, 4 is filled by silica 5 so that its upper face height is a half or higher of the wiring height. Second layer wiring 6 of a required pattern is formed over the wirings 3, 4 and the silica 5 with a contact hole provided on the film 23. Therefore difference in levels at the ends of the wiring 3 can be eliminated so that the wiring 6 is free from breakage as well as it is flattened. Thus highly accurate pattern formation is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a multilayer wiring structure.

[Conventional technology]

Conventionally, a semiconductor integrated circuit device having a multilayer wiring structure has an insulating film 2 on a semiconductor substrate 1, as shown in FIG.
The first layer wiring 3 of a required pattern is formed on A, and the second layer wiring 6 is further formed on this with an insulating film 2B interposed therebetween. In this case, silica 5 is coated on the insulating film 2B in order to reduce the level difference at the end of the first layer wiring 3.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit device described above, the level difference in the first layer wiring 3 is alleviated by applying silica 5, but if the silica 5 is not applied properly, the level difference is not sufficiently alleviated, and the level difference in the first layer wiring 3 is reduced. As shown in FIG. 3, there is a problem in that a break occurs in the second layer wiring 6.

Further, due to the step difference in the first layer wiring 3, the flatness of the second layer wiring 6 is poor, and the pattern image projected in the photolithography process is likely to be out of focus, making it difficult to form the second layer wiring 6 with high precision. There is also the problem of not being able to do so.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that prevents breakage of second layer wiring and enables highly accurate pattern formation.

[Means to solve the problem]

In the semiconductor integrated circuit device of the present invention, dummy wiring is formed between the first layer wiring provided on the substrate while maintaining insulation from the first layer wiring, and the dummy wiring is formed between the first layer wiring and the dummy wiring. Insulating material is filled in between.

[Effect]

In this structure, the gap between the first layer interconnects is made smaller by the dummy interconnects, and the filling of the insulating material into the gaps is improved to alleviate the level difference and suppress the breakage of the second layer interconnects.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

In the figure, a first layer wiring 3 is formed on an insulating film 2A of a semiconductor substrate 1 using a metal film such as argonium. At this time, a dummy ξ-wiring 4 is formed between the originally required wiring patterns. This dummy wiring 4 is formed at an interval within three times the wiring thickness from the original IM wiring 3.

For example, if the first layer wiring 3 is made of aluminum wiring with a thickness of 1 μm, the distance between the first layer wiring 3 and the dummy wiring 4 is 1 to 3 μm. Also, the wiring thickness is 21! m, the interval is 2 to 4 μm.

Then, an insulating film 2B is further formed on the first layer wiring 3 and the dummy wiring 4, and silica 5 is applied to the gap between the first layer wiring 3 and the dummy wiring 4. Fill the gap and increase the surface height of the silica 5 to the first layer wiring 3. The height of the upper surface of the dummy wiring 4 is set to be at least 1/2 or equal to the height.

In addition, these first layer wiring 3. A second layer wiring 6 of a desired pattern is formed over the dummy wiring 4 and the silica 5.

It goes without saying that a contact hole 1 is formed in the insulating film 2B at the connection portion between the first layer wiring 3 and the second layer wiring 6.

According to this structure, the dummy wiring 4 is arranged at the end of the first layer wiring 3 with a minute gap, and the gap is filled with silica 5. The difference in level at the end is almost eliminated. This completely prevents breakage of the second layer wiring 6, flattens the second wiring 6, prevents out-of-focus of the projected pattern in the photo-I lithography process, and enables highly accurate pattern formation. becomes.

FIG. 2 is a longitudinal sectional view of a second embodiment of the present invention, and the same parts as in FIG. 1 are designated by the same reference numerals.

This embodiment is applied to a semiconductor integrated circuit device in which electrodes are formed using a polycrystalline silicon film in addition to the first layer wiring 3. That is, if the thickness of this polycrystalline silicon film is 172 or more times the thickness of the first layer wiring 3, the polycrystalline silicon film 7 is disposed between the first layer wirings 3 as a dummy wiring. .

Then, an oxide film 8 is formed on the surface of the polycrystalline silicon film 7, and an insulating film 2B is formed thereon.

Note that, as in the first embodiment, silica 5 is filled between the first layer wiring 3 and the first layer wiring 3 to alleviate the step difference.

Note that the present invention can be similarly applied to a multilayer wiring structure of three or more layers. In this case, the first layer wiring may be used as the lower wiring, and the second layer wiring may be used as the upper wiring.

〔Effect of the invention〕

As explained above, in the present invention, dummy wiring is formed between the first layer wirings while maintaining insulation, and an insulator is filled between the first layer wirings and the dummy wirings. The wiring reduces the gap between the first layer wiring, improves the ability to fill the gap with insulation, alleviates the difference in level, prevents breakage of the second layer wiring, and enables high-precision pattern formation. It has the effect of making it possible.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of a first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a second embodiment of the present invention, and FIG. 3 is a vertical cross-sectional view of a conventional multilayer wiring structure. ■...Semiconductor substrate, 2A, 2B...Insulating film, 3...
・First layer wiring, 4... dummy wiring (aluminum film)
, 5... Silica, 6... Second layer wiring, 7... Dummy wiring (polycrystalline silicon film), 8... Oxide film.

Claims (1)

[Claims] 1. A second layer is placed on the first layer wiring provided on the substrate via an insulating film.
In a semiconductor integrated circuit device having a multilayer wiring structure in which layer wiring is formed, a dummy wiring is formed between the first layer wiring while maintaining insulation from the first layer wiring, and a dummy wiring is formed between the first layer wiring and the dummy wiring. A semiconductor integrated circuit device characterized in that an insulating material is filled between wirings.