JPH0199216A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0199216A JPH0199216A JP25761587A JP25761587A JPH0199216A JP H0199216 A JPH0199216 A JP H0199216A JP 25761587 A JP25761587 A JP 25761587A JP 25761587 A JP25761587 A JP 25761587A JP H0199216 A JPH0199216 A JP H0199216A
- Authority
- JP
- Japan
- Prior art keywords
- roller
- thin film
- substrate
- semiconductor substrate
- wiring layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 31
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- 239000010408 film Substances 0.000 abstract description 7
- 238000003825 pressing Methods 0.000 abstract description 6
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical class [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
配線形成用のアルミニウム系配線層を半導体基板上に形
成させるための方法に関し、
半導体基板に形成された凹部を埋めると共に、上面が平
坦な配線層の形成を目的とし、半導体基板上にアルミニ
ウムの薄膜を被着または搭載し、該半導体基板と薄膜お
よび加圧用ローラを150〜500℃に加熱し、該半導
体基板とローラとの少なくとも一方を移動させて、該加
熱ローラで該加熱薄膜を該半導体基板に押圧させて構成
する。[Detailed Description of the Invention] [Summary] A method for forming an aluminum-based wiring layer for forming wiring on a semiconductor substrate, which fills a recess formed in a semiconductor substrate and forms a wiring layer with a flat top surface. A thin film of aluminum is deposited or mounted on a semiconductor substrate, the semiconductor substrate, the thin film, and a pressure roller are heated to 150 to 500°C, and at least one of the semiconductor substrate and the roller is moved. The heating thin film is pressed against the semiconductor substrate using a heating roller.
本発明は半導体装置の製造におけるアルミニウム系配線
層の形成方法、特に、選択的にパターン形成された絶縁
層等による凹凸を有する半導体基板上に、該凹凸を埋め
て上面の平坦なアルミニウム系配線層を形成させる方法
に関する。The present invention relates to a method for forming an aluminum-based wiring layer in the manufacture of semiconductor devices, and in particular, to a semiconductor substrate having unevenness due to a selectively patterned insulating layer, etc., the unevenness is filled to form an aluminum-based wiring layer with a flat upper surface. The present invention relates to a method for forming.
IC,LSI等の半導体装置の配線は、一般にアルミニ
ウム(AI)系の導体が用いられ、厚さ1IIIll程
度の該配線を形成するためのAI系配線層は、一般にマ
グネトロンスパッタリング装置が利用されている。しか
し、既に絶縁層をパターン形成してなる等によって凹凸
を有する半導体基板に、マグネトロンスパッタリング装
置を使用し、単純に形成された該配線層は、コンタクト
ホールの底面および側面で薄くなり、許容電流値が低減
するおよび断線原因となる等の欠点があった。Aluminum (AI)-based conductors are generally used for wiring in semiconductor devices such as ICs and LSIs, and a magnetron sputtering device is generally used to form the AI-based wiring layer to form the wiring, which is about 1IIIll thick. . However, when the wiring layer is simply formed using a magnetron sputtering device on a semiconductor substrate that has unevenness due to patterning of an insulating layer, etc., the wiring layer becomes thinner at the bottom and side surfaces of the contact hole, and the allowable current value There were drawbacks such as a reduction in the number of wires and a cause of wire breakage.
第4図は絶縁層をパターン形成した半導体基板上にAA
の配線層を形成した断面図であり、所望のパターンに絶
’4kN2を形成した半導体基板1の上に、マグネトロ
ンスパッタリング装置等を使用しAβの配線層3を形成
してなる。Figure 4 shows an AA film on a semiconductor substrate on which an insulating layer has been patterned.
This is a cross-sectional view of a wiring layer 3 formed by forming an Aβ wiring layer 3 using a magnetron sputtering device or the like on a semiconductor substrate 1 on which 4kN2 is formed in a desired pattern.
絶縁層2は配線層3の形成に先立って凹所、例えばコン
タクトホール4が形成されており、バイアススパッタ法
等の平坦化が採用されない配線層3は、図示する如くコ
ンタクトホール4の上方でオーバハングが生成し、コン
タクトホール4の底面および側面で薄くなる。In the insulating layer 2, a recess, for example, a contact hole 4, is formed before forming the wiring layer 3, and the wiring layer 3, which is not flattened by bias sputtering, has an overhang above the contact hole 4 as shown in the figure. is generated and becomes thinner at the bottom and side surfaces of the contact hole 4.
そこで、従来はコンタクトホール4を開口部で広口の台
形状に形成したり、配線層3の形成に際しバイアススパ
ッタリング法を適用する等によって、オーバハングの生
成を抑制し、コンタクトホール4の底面および側面で薄
くならないように考慮し、配線層3を被着せしめていた
。Therefore, in the past, the generation of overhang was suppressed by forming the contact hole 4 into a wide trapezoidal opening or applying a bias sputtering method when forming the wiring layer 3. The wiring layer 3 was deposited in order not to become thin.
しかしながら、従来方法によるオーバハングの生成抑制
手段において、コンタクトホールを台形状にする方法は
、オーバハングの影響をなくす程度の台形状にすること
が困難であり、バイアススパッタリング法を利用する方
法は、配線層の形成に要する時間が長引くようになると
共に、半導体基板の温度上昇によって配線層の組織の微
細化および均一化が損なわれる、膜厚が不均一になるお
よび、コンタクトホール4の上方に凹部が生成されるよ
うになるため、配線パターンの微細化および精度が損な
われるという問題点があり、新規手段が要望されていた
。However, in the conventional method of suppressing the generation of overhang, it is difficult to make the contact hole trapezoidal enough to eliminate the effect of overhang. As the time required to form the contact hole 4 increases, the temperature of the semiconductor substrate increases, which impairs the fineness and uniformity of the structure of the wiring layer, makes the film thickness non-uniform, and creates a recess above the contact hole 4. As a result, there is a problem in that the miniaturization and precision of wiring patterns are impaired, and a new means has been desired.
上記問題点の除去を目的とした本発明方法は、第1図に
よれば、半導体基板11上にアルミニウム系導体の薄膜
12を被着(または搭載)し、半導体基板11と薄膜1
2および加圧用ローラ20とを150〜500℃に加熱
し、半導体基板11とローラ20との少なくとも一方を
移動させて、加熱ローラ20で加熱薄膜12を半導体基
板11に押圧させることを特徴とする半導体装置の製造
方法である。According to the method of the present invention aimed at eliminating the above-mentioned problems, as shown in FIG. 1, a thin film 12 of an aluminum conductor is deposited (or mounted) on a semiconductor substrate 11.
2 and the pressure roller 20 are heated to 150 to 500°C, at least one of the semiconductor substrate 11 and the roller 20 is moved, and the heating thin film 12 is pressed against the semiconductor substrate 11 by the heating roller 20. This is a method for manufacturing a semiconductor device.
上記手段によれば、加熱することで薄膜の流動(塑性変
形)を容易化し、加圧することで薄膜を塑性変形せしめ
、一般に1μm程度の深さに形成された半導体基板の凹
所は該薄膜の塑性変形によって確実に埋められるように
なると共に、該薄膜を塑性変形してなる配線層の上面は
平坦化されるようになる。従って、本発明は配線層の不
要部を除去するためのマスク合わせ等が高精度化し、微
細、高密度な配線の形成に寄与する。According to the above means, heating facilitates the flow (plastic deformation) of the thin film, and applying pressure causes the thin film to be plastically deformed, and the recesses in the semiconductor substrate, which are generally formed to a depth of about 1 μm, are formed in the thin film. Plastic deformation ensures that the wiring layer is filled in, and the upper surface of the wiring layer formed by plastic deformation of the thin film is flattened. Therefore, the present invention improves the accuracy of mask alignment for removing unnecessary portions of wiring layers, and contributes to the formation of fine, high-density wiring.
以下に、図面を用いて本発明方法の実施例を説明する。 Examples of the method of the present invention will be described below with reference to the drawings.
第1図は本発明方法の実施例による導体薄膜の平坦化押
圧装置を模式的に示す側面図、第2図は本発明方法の一
実施例による試料要部の側断面図、第3図は本発明方法
の他の実施例による試料要部の側断面図である。FIG. 1 is a side view schematically showing a flattening press device for a conductive thin film according to an embodiment of the method of the present invention, FIG. 2 is a side sectional view of the main part of a sample according to an embodiment of the method of the present invention, and FIG. FIG. 7 is a side cross-sectional view of a main part of a sample according to another embodiment of the method of the present invention.
第1図において、半導体装置基板11は上面にAl系の
薄膜12を形成(スパッタ)または搭載し、熱伝厚性を
有するホルダ13に固着し、ホルダ13は左右動自在な
ステージ14に固着させる。ステージ14は、ホルダ1
3の下面に対向するヒータ15を具え、例えばホルダ1
3に装着した温度センサによって通電が制御されるヒー
タ15は、基板11および薄膜12を150〜500℃
に加熱する。In FIG. 1, a semiconductor device substrate 11 has an Al-based thin film 12 formed (sputtered) or mounted on its upper surface, and is fixed to a holder 13 having thermal conductivity, and the holder 13 is fixed to a stage 14 that can move left and right. . Stage 14 is holder 1
For example, the holder 1 has a heater 15 facing the lower surface of the holder 1.
A heater 15 whose energization is controlled by a temperature sensor attached to
Heat to.
ステージ14の上方には、加圧用のコイルばね17を介
して固定部材16に支持金具18が垂下し、回転軸19
によって支持金具18に支持され回転自在でありヒータ
を内蔵するローラ20は、固定部材16を適宜量だけ降
下させるまたはステージ14を上昇させたとき、薄膜1
2を基板11に押圧することになり、その押圧力はコイ
ルばね17の反t8力によって発生する。Above the stage 14, a support fitting 18 hangs down from the fixed member 16 via a coil spring 17 for pressurization, and a rotating shaft 19
The roller 20, which is rotatable and has a built-in heater, is supported by the support fitting 18 by the roller 20, and when the fixing member 16 is lowered by an appropriate amount or the stage 14 is raised, the thin film 1
2 is pressed against the substrate 11, and the pressing force is generated by the anti-t8 force of the coil spring 17.
そこで、基板11と薄膜12およびローラ20を150
〜600°Cに加熱し、50〜200kg/cniの押
圧力でローラ20が薄膜12を押圧するようにしたのち
、ステージ14を左右方向に移動させるまたは、ローラ
20を左右方向に移動させると、該加熱によって軟化し
塑性変形し易くなった薄膜12は、該押圧力によって基
板11に形成された凹所を埋めると共に上面が平坦化さ
れ、その後の工程で不要部分を除去する配線層が得られ
ることになる。Therefore, the substrate 11, thin film 12, and roller 20 were
After heating to ~600°C and causing the roller 20 to press the thin film 12 with a pressing force of 50 to 200 kg/cni, the stage 14 is moved left and right, or the roller 20 is moved left and right. The thin film 12, which has been softened and easily plastically deformed by the heating, fills the recesses formed in the substrate 11 by the pressing force and has a flattened upper surface, thereby obtaining a wiring layer from which unnecessary portions are removed in subsequent steps. It turns out.
第2図において、上面に二酸化シリコン(SiO□)等
にてなる絶縁層23が選択的に形成された半導体基板1
1の上に、マクネトロンスパッタリング装置を使用した
Al系導体薄膜12を被着したのち、薄膜12の上を前
述のローラ20で押圧すると、薄膜12は絶縁層23の
被着しない凹所を隈無く埋め、上′ 面の平坦な配線層
21が得られる。ただし、配線層21の厚さを1.とし
たとき、薄膜12の厚さt2は該凹所を埋める平準化に
使用される量を見込んで適宜量だけ厚く、例えば厚さt
lが1μmであるとき1゜を1.6μmに形成する必要
がある。In FIG. 2, a semiconductor substrate 1 has an insulating layer 23 made of silicon dioxide (SiO□) selectively formed on its upper surface.
1, an Al-based conductive thin film 12 is deposited using a Macnetron sputtering device, and then the thin film 12 is pressed with the roller 20 described above, and the thin film 12 covers the recesses where the insulating layer 23 is not deposited. Thus, a wiring layer 21 with a flat top surface is obtained. However, the thickness of the wiring layer 21 is set to 1. In this case, the thickness t2 of the thin film 12 is thickened by an appropriate amount in consideration of the amount used for leveling to fill the recess, for example, the thickness t2.
When l is 1 μm, it is necessary to form 1° to 1.6 μm.
第3図において、絶縁Ji23が選択的に形成された半
導体基板11の上に、Aβ系導体シート (薄膜)22
を搭載したのち、シート22の上を前述のローラ20で
押圧すると、シート22は絶縁層23の被着しない凹所
を隈無く埋め、上面の平坦な配線層21になる。ただし
、配線層21の厚さをtlとしたとき、シート22の厚
さt、は該凹所を埋める平準化に使用される量を見込ん
で適宜量だけ厚く、例えば厚さtlが1μmであるとき
厚さt、を2〜4μmとする必要がある。In FIG. 3, an Aβ-based conductor sheet (thin film) 22 is placed on a semiconductor substrate 11 on which an insulating Ji 23 is selectively formed.
When the sheet 22 is pressed with the roller 20 described above, the sheet 22 completely fills the recesses where the insulating layer 23 is not adhered, and becomes a flat wiring layer 21 on the upper surface. However, when the thickness of the wiring layer 21 is tl, the thickness t of the sheet 22 is thickened by an appropriate amount in consideration of the amount used for leveling to fill the recess, for example, the thickness tl is 1 μm. The thickness t needs to be 2 to 4 μm.
以上説明したように本発明によれば、加熱することで薄
膜の流動(塑性変形)を容易化し、加圧することで薄膜
を塑性変形せしめ、一般に1μm程度の深さに形成され
た半導体基板の凹所は、該薄膜の塑性変形によって確実
に埋められるようになると共に、該薄膜を塑性変形して
なる配線層の上面は平坦化されるようになる。その結果
、配線層の不要部を除去するためのマスク合わせ等が高
精度化し、微細かつ高密度な配線の形成に寄与した効果
がある。As explained above, according to the present invention, the flow (plastic deformation) of the thin film is facilitated by heating, and the thin film is plastically deformed by applying pressure. The spots are reliably filled by plastic deformation of the thin film, and the upper surface of the wiring layer formed by plastic deformation of the thin film is flattened. As a result, mask alignment for removing unnecessary portions of the wiring layer becomes more accurate, which has the effect of contributing to the formation of fine and high-density wiring.
第1図は本発明方法の実施例による平坦化押圧装置を模
式的に示す側面図、
第2図は本発明方法の一実施例による試料要部の側断面
図、
第3図は本発明方法の他の実施例による試料要部の側断
面図、
第4図は絶縁層をパターン形成した半導体基板上に配線
層を形成した断面図、
である。
図中において、
11は半導体基板、
12はアルミニウム系導体の薄膜、
15はヒータ、
20は加圧用ローラ、
21はアルミニウム系導体の配線層、
22アルミニウム系導体のシート (薄膜)、23は絶
縁層、
を示す。
J4図FIG. 1 is a side view schematically showing a flattening press device according to an embodiment of the method of the present invention, FIG. 2 is a side sectional view of the main part of a sample according to an embodiment of the method of the present invention, and FIG. 3 is a method of the present invention FIG. 4 is a side cross-sectional view of a main part of a sample according to another embodiment. FIG. 4 is a cross-sectional view of a wiring layer formed on a semiconductor substrate on which an insulating layer is patterned. In the figure, 11 is a semiconductor substrate, 12 is a thin film of aluminum conductor, 15 is a heater, 20 is a pressure roller, 21 is a wiring layer of aluminum conductor, 22 is a sheet (thin film) of aluminum conductor, and 23 is an insulating layer. , indicates. J4 diagram
Claims (1)
12、22)を被着または搭載し、該半導体基板(11
)と薄膜(12、22)および加圧用ローラ(20)を
150〜500℃に加熱し、該半導体基板(11)とロ
ーラ(20)との少なくとも一方を移動させて、該加熱
ローラ(20)で該加熱薄膜(12、22)を該半導体
基板(11)に押圧させることを特徴とする半導体装置
の製造方法。A thin film of aluminum conductor (
12, 22) is adhered or mounted, and the semiconductor substrate (11
), the thin film (12, 22), and the pressure roller (20) are heated to 150 to 500°C, and at least one of the semiconductor substrate (11) and the roller (20) is moved to remove the heating roller (20). A method for manufacturing a semiconductor device, characterized in that the heating thin film (12, 22) is pressed against the semiconductor substrate (11).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25761587A JPH0199216A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25761587A JPH0199216A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0199216A true JPH0199216A (en) | 1989-04-18 |
Family
ID=17308723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25761587A Pending JPH0199216A (en) | 1987-10-13 | 1987-10-13 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0199216A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4228218A1 (en) * | 1992-08-25 | 1994-03-10 | Siemens Ag | Planarisation process for semiconductor substrate layer - applying pressure across entire surface of layer to remove unevenness prior to structuring |
US5547902A (en) * | 1995-01-18 | 1996-08-20 | Advanced Micro Devices, Inc. | Post hot working process for semiconductors |
JPH08227887A (en) * | 1995-02-21 | 1996-09-03 | Nec Corp | Manufacture of semiconductor device |
US6150252A (en) * | 1995-05-23 | 2000-11-21 | Texas Instruments Incorporated | Multi-stage semiconductor cavity filling process |
JP2007019535A (en) * | 2002-08-30 | 2007-01-25 | Nec Corp | Manufacturing apparatus for semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132281A (en) * | 1974-09-13 | 1976-03-18 | Fujitsu Ltd |
-
1987
- 1987-10-13 JP JP25761587A patent/JPH0199216A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5132281A (en) * | 1974-09-13 | 1976-03-18 | Fujitsu Ltd |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4228218A1 (en) * | 1992-08-25 | 1994-03-10 | Siemens Ag | Planarisation process for semiconductor substrate layer - applying pressure across entire surface of layer to remove unevenness prior to structuring |
DE4228218C2 (en) * | 1992-08-25 | 1998-12-10 | Siemens Ag | Method and device for planarizing a layer on a semiconductor substrate |
US5547902A (en) * | 1995-01-18 | 1996-08-20 | Advanced Micro Devices, Inc. | Post hot working process for semiconductors |
JPH08227887A (en) * | 1995-02-21 | 1996-09-03 | Nec Corp | Manufacture of semiconductor device |
US6150252A (en) * | 1995-05-23 | 2000-11-21 | Texas Instruments Incorporated | Multi-stage semiconductor cavity filling process |
JP2007019535A (en) * | 2002-08-30 | 2007-01-25 | Nec Corp | Manufacturing apparatus for semiconductor device |
JP4710768B2 (en) * | 2002-08-30 | 2011-06-29 | 日本電気株式会社 | Semiconductor device manufacturing apparatus and semiconductor device manufacturing method |
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