JPH01241825A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01241825A JPH01241825A JP6814288A JP6814288A JPH01241825A JP H01241825 A JPH01241825 A JP H01241825A JP 6814288 A JP6814288 A JP 6814288A JP 6814288 A JP6814288 A JP 6814288A JP H01241825 A JPH01241825 A JP H01241825A
- Authority
- JP
- Japan
- Prior art keywords
- grooves
- semiconductor substrate
- warpage
- film
- warped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 12
- 238000001459 lithography Methods 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract 1
- 230000008021 deposition Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分針)
本発明は、半導体装置の製造工程において特に高精度パ
ターンの形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Minute Hand) The present invention particularly relates to a method of forming a highly accurate pattern in the manufacturing process of a semiconductor device.
(従来の技術)
最近の半導体装置では高密度、高集積化を達成するため
−こ数1も0)嗅を積層したls造が採用されている。(Prior Art) In recent semiconductor devices, in order to achieve high density and high integration, an LS structure in which the number 1 is also 0) is used.
この様に数1−もの嗅を堆積した構造では、僕自身の応
力1こよって、半導体基板が反る現象が発生することが
しばしばあったっ
(発明が解決しようとする課@)
以上述べたように、従来の方法では堆積模り応力により
半導体基板が反ることがあり、例えばリソグラフィ工程
においてパターンが伸びてしまったりフォーカスぼけが
起こり、高fit f”l パターンを形成できない問
題があった。In a structure like this, in which several layers of metal are deposited, the semiconductor substrate often warps due to my own stress (a problem that the invention aims to solve).As stated above, In addition, in the conventional method, the semiconductor substrate may warp due to the stress caused by the deposition, and for example, the pattern may be elongated or out of focus may occur in the lithography process, making it impossible to form a high fit f''l pattern.
本発明は、上記のよう曇こ、半導体基板が反ってしまっ
た場合曇こ容易にそれを小さくすることができる半導体
装置の製造方法を提供することを目的とするものである
。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily reduce the cloudiness and warp of a semiconductor substrate as described above.
〔発明の111成〕
(課@を解決するための手段)
上記目的を達成するために1本宛明は、半導体主面に堆
積される嘆の任意の工程および任意の位置曇こ11i#
を設けること曇こより、模り応力憂こよる半導体基板の
反りを小さくすることを図るものである。[111th Form of the Invention] (Means for Solving Section @) In order to achieve the above-mentioned object, one purpose is to apply a cloud 11i# which is deposited on the main surface of a semiconductor in any process and at any position.
The purpose of this is to reduce the warping of the semiconductor substrate caused by mechanical stress.
(作用)
本発明昏こよる半導体装置の製造万去壷こまnば、半導
体極板主面上の堆積僕Gこ溝を形成すること昏こより、
そLJ)部分で堆積模り応力を緩和することができ、中
導体壜板の反りを小さくすることができるので、リソグ
ラフィー工程−こおいて高精度なパターンを形成するこ
とが可納になる。(Function) When manufacturing a semiconductor device according to the present invention, forming grooves on the main surface of a semiconductor electrode plate,
Since the stress caused by the deposition can be relaxed in the LJ) portion and the warpage of the medium conductor bottle plate can be reduced, it becomes possible to form a highly accurate pattern in the lithography process.
(実施例) 以下、本情明の実施例を図面?用いて説明する。(Example) The following is a drawing of an example of this information? I will explain using
半導体装置の製造工程において、半導体基数が反ってし
まった1易会、第1図に示すように、レーザ光を1打い
て、ウェハ上のダイシング94フ部の堆積嗅に溝1を形
成する。ここで第1図には、縦横、各1本ずつの111
1ヲ形成したが、本数は必要において増やせばよい。In the manufacturing process of a semiconductor device, when a semiconductor substrate is warped, as shown in FIG. 1, a laser beam is irradiated once to form a groove 1 in the deposited portion of the dicing 94 on the wafer. Here, in Figure 1, there are 111 lines, one each in the vertical and horizontal directions.
Although one was formed, the number can be increased if necessary.
また、溝の深さをこついては半導体基板の反りが高精度
のパターン形成に必要とされている±1〜2/1m以下
に小さくできれば第2図+a)のように堆積嗅厚より浅
くても、第21スfb) (4)よりに膜厚と同じであ
っても@2図(e)のように嗅厚より深くてもよい。In addition, if the depth of the groove can be reduced to within ±1 to 2/1 m, which is required for high-precision pattern formation, the warpage of the semiconductor substrate can be reduced even if it is shallower than the deposited thickness as shown in Figure 2+a). , 21st fb) According to (4), the thickness may be the same as the membrane thickness, or it may be deeper than the olfactory thickness as shown in Figure 2 (e).
また、溝の幅は、表面が凹昏こ反りた場合はほぼ0μm
でよく、凸に反った場合を数μmあれば十分である。In addition, the width of the groove is approximately 0 μm when the surface is concave or curved.
In the case of convex warping, a few micrometers is sufficient.
溝の酢置蚤こついては、溝がダイシングライ/lこ入っ
Cいればよく、高wI度は要求されない。さらに数チッ
プを犠牲奢こすれば、溝をチップ上に形成−してもよく
、この場合位置の精度は全く要求されないのに等しい。To prevent vinegar from forming in the grooves, it is only necessary that the grooves are dicing-lined, and a high degree of wiping is not required. By sacrificing a few more chips, grooves can be formed on the chips, in which case no positional accuracy is required.
溝を形成する時期昏こついてはリングラフィ工程前の半
導体基板の反りを小さくできる任意の工程ζこおいてで
よい。If the timing for forming the grooves is in doubt, any process ζ that can reduce the warpage of the semiconductor substrate before the phosphorography process may be performed.
溝を形成する他の実施例としては、刃物状のものを用い
る方法がある。Another example of forming the groove is a method using a blade-like tool.
以上述べTこようφこ、本発明によれは数1%、の嘆を
積1した半導体装(itの製造工程において、積層した
嘆Q)応力により半導体基板が反ってしまった場合Eこ
、反りを容易に小さくすることができるので、リソグラ
フィ工程において高精度カバターフが形成でき、高密1
更比、高集積度比が可能昏こなる。As stated above, according to the present invention, if the semiconductor substrate is warped due to stress of a semiconductor device (layered in the IT manufacturing process) of several 1%, Since warpage can be easily reduced, a high-precision cover tuff can be formed in the lithography process, and a high-density 1
Further ratios and higher integration ratios are possible.
第1図は本発明り製造万1去昏こよる平1■図、第2図
は断面図である。第1図、嘉2図において。
l・・・溝、2・・・チップ、3・・・堆積・漠3よび
累子領域、4・・・半導体基板(ウェハ) ぐ゛あ夕・
代理人 弁理士 則 近 憲 佑FIG. 1 is a diagram showing the state of the art according to the present invention, and FIG. 2 is a cross-sectional view. In Figures 1 and 2. l...groove, 2...chip, 3...deposition/deposition 3 and layer region, 4...semiconductor substrate (wafer)
Agent Patent Attorney Noriyuki Chika
Claims (1)
位置に溝を設けることを具備してなる半導体装置の製造
方法。1. A method of manufacturing a semiconductor device, comprising forming a groove at an arbitrary step and at an arbitrary position in a pattern deposited on a main surface of a semiconductor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6814288A JPH01241825A (en) | 1988-03-24 | 1988-03-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6814288A JPH01241825A (en) | 1988-03-24 | 1988-03-24 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01241825A true JPH01241825A (en) | 1989-09-26 |
Family
ID=13365198
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6814288A Pending JPH01241825A (en) | 1988-03-24 | 1988-03-24 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01241825A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219505A (en) * | 2009-02-23 | 2010-09-30 | Seiko Instruments Inc | Manufacturing method of glass-sealed package, and glass substrate |
CN105990308A (en) * | 2015-03-17 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
-
1988
- 1988-03-24 JP JP6814288A patent/JPH01241825A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219505A (en) * | 2009-02-23 | 2010-09-30 | Seiko Instruments Inc | Manufacturing method of glass-sealed package, and glass substrate |
CN105990308A (en) * | 2015-03-17 | 2016-10-05 | 株式会社东芝 | Semiconductor device and manufacturing method thereof |
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