JPH0424733B2 - - Google Patents

Info

Publication number
JPH0424733B2
JPH0424733B2 JP59168163A JP16816384A JPH0424733B2 JP H0424733 B2 JPH0424733 B2 JP H0424733B2 JP 59168163 A JP59168163 A JP 59168163A JP 16816384 A JP16816384 A JP 16816384A JP H0424733 B2 JPH0424733 B2 JP H0424733B2
Authority
JP
Japan
Prior art keywords
command
input
processing unit
central processing
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59168163A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6146545A (ja
Inventor
Katsumi Oonishi
Juji Oinaga
Nobuyuki Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16816384A priority Critical patent/JPS6146545A/ja
Publication of JPS6146545A publication Critical patent/JPS6146545A/ja
Publication of JPH0424733B2 publication Critical patent/JPH0424733B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP16816384A 1984-08-11 1984-08-11 入出力命令制御方法 Granted JPS6146545A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16816384A JPS6146545A (ja) 1984-08-11 1984-08-11 入出力命令制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16816384A JPS6146545A (ja) 1984-08-11 1984-08-11 入出力命令制御方法

Publications (2)

Publication Number Publication Date
JPS6146545A JPS6146545A (ja) 1986-03-06
JPH0424733B2 true JPH0424733B2 (lt) 1992-04-27

Family

ID=15862971

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16816384A Granted JPS6146545A (ja) 1984-08-11 1984-08-11 入出力命令制御方法

Country Status (1)

Country Link
JP (1) JPS6146545A (lt)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5217002B2 (ja) * 2004-07-05 2013-06-19 株式会社ナチュラレーザ・ワン 原稿圧着板開閉装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257743A (en) * 1975-11-07 1977-05-12 Hitachi Ltd Channel equipment
JPS52122066A (en) * 1976-04-06 1977-10-13 Kinsekisha Lab Ltd Device for judging frequency characteristics
JPS52144236A (en) * 1976-05-26 1977-12-01 Hitachi Ltd Information processing system
JPS58214930A (ja) * 1982-06-08 1983-12-14 Nec Corp デ−タ処理装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257743A (en) * 1975-11-07 1977-05-12 Hitachi Ltd Channel equipment
JPS52122066A (en) * 1976-04-06 1977-10-13 Kinsekisha Lab Ltd Device for judging frequency characteristics
JPS52144236A (en) * 1976-05-26 1977-12-01 Hitachi Ltd Information processing system
JPS58214930A (ja) * 1982-06-08 1983-12-14 Nec Corp デ−タ処理装置

Also Published As

Publication number Publication date
JPS6146545A (ja) 1986-03-06

Similar Documents

Publication Publication Date Title
EP0166272B1 (en) Processor bus access
EP0464615B1 (en) Microcomputer equipped with DMA controller
US5371857A (en) Input/output interruption control system for a virtual machine
US5107416A (en) Arrangement for simultaneously dealing with transfer requests produced by central, arithmetic and input-output processors of a super computer
US6134642A (en) Direct memory access (DMA) data transfer requiring no processor DMA support
JPH0424733B2 (lt)
US6085297A (en) Single-chip memory system including buffer
JP2522412B2 (ja) プログラマブルコントロ―ラと入出力装置の間の通信方法
JPH09218859A (ja) マルチプロセッサ制御システム
JPH0321941B2 (lt)
JPS63155254A (ja) 情報処理装置
JPH02183342A (ja) 割込み制御装置
JPS60136853A (ja) デ−タ転送方式
JPH01302448A (ja) 情報処理装置
JPH07111711B2 (ja) 処理終了割込制御システム
JPS6215903B2 (lt)
JPS61256421A (ja) 捕助記憶装置転送バツフアの初期化方式
JPH0425581B2 (lt)
JPS6267648A (ja) 排他制御命令処理方式
JPH01316851A (ja) チャネル制御方式
JPS6223342B2 (lt)
JPS63113658A (ja) インタロツク命令制御方式
JPS6175942A (ja) デイスクキヤツシユ制御方式
JPS6039265A (ja) デ−タ転送方式
JPH0690711B2 (ja) メモリアクセス制御方式

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees