JPH04245469A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH04245469A JPH04245469A JP1023391A JP1023391A JPH04245469A JP H04245469 A JPH04245469 A JP H04245469A JP 1023391 A JP1023391 A JP 1023391A JP 1023391 A JP1023391 A JP 1023391A JP H04245469 A JPH04245469 A JP H04245469A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- region
- element substrate
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000006185 dispersion Substances 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 5
- 229910052906 cristobalite Inorganic materials 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 229910052682 stishovite Inorganic materials 0.000 description 5
- 229910052905 tridymite Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明はＩＣ等の半導装置および
その製造方法に係り、特に半導体抵抗およびその製造方
法に関する。近年では、ＩＣの大規模集積化が要求され
ているため、各回路要素のレイアウト面積の縮少化が必
要となり、ＩＣ内の抵抗の高抵抗化とともに、歩留り向
上のために高精度化が要求される。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as an IC and a method of manufacturing the same, and more particularly to a semiconductor resistor and a method of manufacturing the same. In recent years, there has been a demand for large-scale integration of ICs, which necessitates a reduction in the layout area of each circuit element.In addition to increasing the resistance of ICs, higher precision is also required to improve yields. be done.
【０００２】0002
【従来の技術】図３に従来の半導体拡散抵抗の例を示す
。図３に示すように、従来の拡散抵抗は、シリコン基板
の一部にシリコン基板とは逆導電型のイオンを打ち込み
、その拡散領域５を抵抗として使用するものであった。
拡散領域５の両端には電圧供給用のアルミ酸線４が互い
に適当な間隔をおいて電気的にコンタクトがとられてい
る。コタンクトホール３はアルミ配線４と拡散領域５と
の電気的コンタクトをとるためのものであり、その下層
側には電極取出し用の高濃度拡散領域２が形成されてい
る。2. Description of the Related Art FIG. 3 shows an example of a conventional semiconductor diffused resistor. As shown in FIG. 3, in the conventional diffused resistor, ions of a conductivity type opposite to that of the silicon substrate are implanted into a part of a silicon substrate, and the diffused region 5 is used as a resistor. Aluminum oxide wires 4 for voltage supply are electrically contacted at both ends of the diffusion region 5 at appropriate intervals. The contact hole 3 is for making electrical contact between the aluminum wiring 4 and the diffusion region 5, and a high concentration diffusion region 2 for taking out an electrode is formed on the lower layer side thereof.
【０００３】0003
【発明が解決しようとする課題】ところが、イオン打ち
込み状態にはウェーハ上の位置やその他の条件によって
バラツキが生じ、結果としてウェーハ上の位置によって
抵抗値が相互に異なるという問題があった。また、従来
の拡散抵抗はＰＮ接合の存在により基板すなわちバック
ゲートの電位が抵抗値に影響する、いわゆるバックゲー
ト依存性があるため、抵抗値が異なってしまう問題もあ
った。However, there is a problem in that the state of ion implantation varies depending on the position on the wafer and other conditions, and as a result, the resistance value differs depending on the position on the wafer. In addition, conventional diffused resistors have a so-called backgate dependence in which the potential of the substrate, that is, the backgate, affects the resistance value due to the presence of the PN junction, so there is a problem that the resistance value varies.
【０００４】このようなことから拡散抵抗の特性は非線
型性となり、拡散抵抗を用いた電子回路、例えばフィル
タや増幅器等の歪み率が必ずしも良好なものとはならな
かった。また、イオン打ち込み法を用いると、シート当
りの抵抗値が下がるため、高抵抗を得るためには拡散領
域を長くとらなければならず、レイアウト面積の増大の
原因となっていた。[0004] For this reason, the characteristics of the diffused resistor become non-linear, and the distortion rate of electronic circuits using the diffused resistor, such as filters and amplifiers, is not always good. Furthermore, when the ion implantation method is used, the resistance value per sheet decreases, so in order to obtain high resistance, the diffusion region must be made long, which causes an increase in the layout area.
【０００５】本発明の目的は、バックゲートの影響を受
けず、抵抗値のバラツキの少ない小面積高抵抗化を図り
うる半導体装置およびその製造方法を提供することにあ
る。An object of the present invention is to provide a semiconductor device that is not affected by a back gate, has a small variation in resistance value, and is capable of achieving high resistance in a small area, and a method for manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の発明は、ＳＯＩ構造を有する素子基
板１２内に、トレンチアイソレーション領域１で囲まれ
た島状の抵抗領域９を形成して構成する。請求項２記載
の発明は、ＳＯＩ構造を有する素子基板１２内に、四方
連続するトレンチエッチング部１５を形成し、そのトレ
ンチエッチング部１５内にＣＶＤＳｉＯ２ 膜１６を充
填することにより素子基板１２の所定領域を取り囲むト
レンチアイソレーション領域１を形成し、このトレンチ
アイソレーション領域１によって形成された島状の抵抗
領域９に互いに所定間隔を置いてアルミ配線４、アルミ
配線８を形成する工程を含んで構成する。Means for Solving the Problems In order to solve the above problems, the invention according to claim 1 provides an island-shaped resistance region 9 surrounded by a trench isolation region 1 in an element substrate 12 having an SOI structure. form and compose. According to the second aspect of the invention, a trench etching section 15 continuous on all four sides is formed in an element substrate 12 having an SOI structure, and a predetermined region of the element substrate 12 is filled with a CVDSiO2 film 16 in the trench etching section 15. A trench isolation region 1 surrounding the trench isolation region 1 is formed, and an aluminum wiring 4 and an aluminum wiring 8 are formed at a predetermined distance from each other in an island-shaped resistance region 9 formed by the trench isolation region 1. .
【０００７】[0007]
【作用】請求項１および２記載の発明によれば、ＳＯＩ
構造基板上の素子基板１２内にトレンチアイソレーショ
ン領域１で囲まれた島状の孤立した抵抗領域９が形成さ
れているため、当該抵抗領域９は他の部分から絶縁物で
分離され、従来のようなバックゲートの影響を受けず、
また抵抗領域９は素子基板１２自身を用いており、従来
のようなイオン打込みによる拡散領域５を使用しないの
で、抵抗値のバラツキを抑制し、かつ高抵抗を得ること
が可能となる。[Operation] According to the invention described in claims 1 and 2, SOI
Since an island-shaped isolated resistance region 9 surrounded by a trench isolation region 1 is formed in the element substrate 12 on the structural substrate, the resistance region 9 is separated from other parts by an insulating material, unlike the conventional It is not affected by back gates such as
Further, since the resistance region 9 uses the element substrate 12 itself and does not use the diffusion region 5 formed by ion implantation as in the conventional case, it is possible to suppress variations in resistance value and obtain high resistance.
【０００８】[0008]
【実施例】次に、本発明の好適な実施例を図面に基づい
て説明する。図１に本発明の半導装置である半導体抵抗
の平面図を示す。この半導体装置はＳＯＩ（Ｓｉｌｉｃ
ｏｎ ｏｎ ｉｎｓｕｌａｔｏｒ）構造の基板を用いて
いる。ＳＯＩ構造の基板というのは、ウェーハの最下層
に支持基板（Ｓｉ）を置き、その上に酸化膜（ＳｉＯ２
）を介して素子基板１２が積層された構造を有する。
この酸化膜は支持基板と素子基板１２とを分離するため
のものである。素子基板は約３μｍで形成される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a plan view of a semiconductor resistor which is a semiconductor device of the present invention. This semiconductor device is an SOI (Silicon)
A substrate with an on-on insulator structure is used. A substrate with an SOI structure has a support substrate (Si) placed on the bottom layer of the wafer, and an oxide film (SiO2
) has a structure in which element substrates 12 are laminated via layers. This oxide film is for separating the support substrate and the element substrate 12. The element substrate is formed to have a thickness of about 3 μm.
【０００９】素子基板１２内にはウェーハの延在方向に
四方連続し、かつウェーハの厚さ方向において酸化膜に
到達する深さのトレンチアイソレーション領域１が形成
されている。したがって、素子基板１２内にはトレンチ
アイソレーション領域１と酸化膜とによって完全に包囲
されて分離された島状の抵抗領域が形成されている。抵
抗領域９の両端部には電極取出し用の高濃度拡散領域２
、６がそれぞれ埋込まれている。この高濃度拡散領域２
、６はコンタクトホール３、７と抵抗領域９との接触抵
抗を下げるためにイオン打ち込みされて形成される。
コンタクトホール３、７は高濃度拡散領域２、６とアル
ミ配線４、８間に形成され、このアルミ配線４と８との
間に必要な電圧を印加することにより、アルミ配線４と
８との間の長さに対応する抵抗値を示す作用をなす。Trench isolation regions 1 are formed in the element substrate 12, which are continuous on all sides in the extending direction of the wafer and have a depth that reaches the oxide film in the thickness direction of the wafer. Therefore, in the element substrate 12, island-shaped resistance regions are formed which are completely surrounded and isolated by the trench isolation region 1 and the oxide film. High concentration diffusion regions 2 for electrode extraction are provided at both ends of the resistance region 9.
, 6 are embedded respectively. This high concentration diffusion region 2
, 6 are formed by ion implantation in order to reduce the contact resistance between the contact holes 3 and 7 and the resistance region 9. The contact holes 3 and 7 are formed between the high concentration diffusion regions 2 and 6 and the aluminum wirings 4 and 8, and by applying a necessary voltage between the aluminum wirings 4 and 8, the contact holes 3 and 7 are formed between the aluminum wirings 4 and 8. The function is to indicate the resistance value corresponding to the length between the two.
【００１０】このように作成された抵抗領域９は、Ｓｉ
Ｏ２ のトレンチアイソレーション領域１で囲まれて電
気的に絶縁される。そのため、抵抗領域９の抵抗値は印
加電圧によって変化せず、バックゲート依存性を排除で
きる。また、抵抗領域９として素子基板１２自体を使用
しているので、高抵抗化が可能となる。因に、従来のよ
うな通常の拡散抵抗では、シート抵抗で１〜２ｋΩであ
るのに対し、本発明のように素子基板１２自身を使用し
た場合、３〜３０ｋΩのシート抵抗となる。このことは
、例えば１００ｋΩの抵抗領域９を作成した場合、レイ
アウト面積を約１／１０にも縮少化することができるこ
とを意味する。The resistance region 9 thus created is made of Si
It is surrounded and electrically insulated by an O2 trench isolation region 1. Therefore, the resistance value of the resistance region 9 does not change depending on the applied voltage, and back gate dependence can be eliminated. Furthermore, since the element substrate 12 itself is used as the resistance region 9, high resistance can be achieved. Incidentally, while a conventional conventional diffused resistor has a sheet resistance of 1 to 2 kΩ, when the element substrate 12 itself is used as in the present invention, the sheet resistance is 3 to 30 kΩ. This means that, for example, when creating a resistance region 9 of 100 kΩ, the layout area can be reduced to about 1/10.
【００１１】次に、図２に本発明の半導体装置の製造工
程を示し、製造方法について説明する。まず、図２（ａ
）に示すように、ＳＯＩ構造基板の素子基板１２上に選
択酸化法による素子分離法であるＬＯＣＯＳ（Ｌｏｃａ
ｌ ｏｘｉｄａｔｉｏｎ ｏｆ ｓｉｌｉｃｏｎ）の膜
１３（ＳｉＯ２ ）を形成する。ＳＯＩ構造基板はウェ
ーハの最下層の支持基板１０（Ｓｉ）、その上の酸化膜
１１（ＳｉＯ２ ）、さらにその上の素子基板１２（Ｓ
ｉ）からなる。Next, FIG. 2 shows the manufacturing process of the semiconductor device of the present invention, and the manufacturing method will be explained. First, Figure 2 (a
), LOCOS (Loca
A film 13 (SiO2) of oxidation of silicon is formed. The SOI structure substrate consists of a supporting substrate 10 (Si) at the bottom layer of the wafer, an oxide film 11 (SiO2) thereon, and an element substrate 12 (SiO2) above it.
i).
【００１２】次に、図２（ｂ）に示すように、ＬＯＣＯ
Ｓ膜１３および素子基板１２の表面全面にレジスト１４
を塗布したのち、ＬＯＣＯＳ膜１３を貫通する位置にエ
ッチングによりトレンチエッチング部１５を酸化膜１１
に達する深さで形成する。次いで、図２（ｃ）に示すよ
うに、表面にＣＶＤＳｉＯ２ 膜１６を全面成長させ、
トレンチエッチング部１５内にＳｉＯ２ を充填してト
レンチアイソレーション領域１を作成する。Next, as shown in FIG. 2(b), the LOCO
A resist 14 is applied to the entire surface of the S film 13 and the element substrate 12.
After coating the LOCOS film 13, a trench etched portion 15 is formed by etching the oxide film 11 at a position penetrating the LOCOS film 13.
Form at a depth that reaches . Next, as shown in FIG. 2(c), a CVDSiO2 film 16 is grown on the entire surface.
Trench isolation region 1 is created by filling SiO2 into trench etched portion 15.
【００１３】次いで、図２（ｄ）に示すように、ＬＯＣ
ＯＳ膜１３および抵抗領域９となる素子基板１２上のＣ
ＶＤＳｉＯ２ 膜１６をエッチングバックして表面を露
出する。このように、比較的簡単な工程で他の部分から
完全分離された抵抗領域９を形成することができる。Next, as shown in FIG. 2(d), the LOC
C on the element substrate 12 which becomes the OS film 13 and the resistance region 9
The VDSiO2 film 16 is etched back to expose the surface. In this way, the resistance region 9 completely isolated from other parts can be formed through a relatively simple process.
【００１４】[0014]
【発明の効果】以上の通り、本発明によれば、トレンチ
アイソレーション領域１によって囲まれた抵抗領域を形
成したので、抵抗領域は完全に他の部分から絶縁分離さ
れ、バックゲートの影響を受けることなく抵抗値のバラ
ツキの少ない小面積高抵抗の半導体抵抗を提供すること
ができる。As described above, according to the present invention, the resistance region surrounded by the trench isolation region 1 is formed, so that the resistance region is completely insulated and isolated from other parts and is not affected by the back gate. Therefore, it is possible to provide a small-area, high-resistance semiconductor resistor with little variation in resistance value.
【図１】本発明の半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device of the present invention.
【図２】本発明の半導体装置の製造工程図である。FIG. 2 is a manufacturing process diagram of a semiconductor device of the present invention.
【図３】従来の半導体装置の平面図である。FIG. 3 is a plan view of a conventional semiconductor device.
１…トレンチアイソレーション領域 ２…高濃度拡散領域 ３…コンタクトホール ４…アルミ配線 ５…拡散領域 ６…高濃度拡散領域 ７…コンタクトホール ８…アルミ配線 ９…抵抗領域 １０…支持基板 １１…酸化膜 １２…素子基板 １３…ＬＯＣＯＳ膜 １４…レジスト １５…トレンチエッチング部 １６…ＣＶＤＳｉＯ２ 膜 1...Trench isolation area 2...High concentration diffusion region 3...Contact hole 4...Aluminum wiring 5...Diffusion area 6...High concentration diffusion region 7...Contact hole 8...Aluminum wiring 9...Resistance area 10...Support substrate 11...Oxide film 12...Element board 13...LOCOS film 14...Resist 15...Trench etching part 16...CVDSiO2 film
Claims (2)
内にトレンチアイソレーション領域（１）で囲まれた島
状の抵抗領域（９）が形成されていることを特徴とする
半導体装置。[Claim 1] Element substrate (12) of SOI structure substrate
A semiconductor device characterized in that an island-shaped resistance region (9) surrounded by a trench isolation region (1) is formed therein.
）内に四方連続するトレンチ（１５）を形成する工程と
、前記トレンチ（１５）内に絶縁物（１６）を形成する
工程と、前記トレンチアイソレーション領域（１）によ
って形成された島状の領域（９）に電気的に接触する電
極（４）を互いに間隔をおいて少なくとも２ヶ所設ける
工程と、を含むことを特徴とする半導体装置の製造方法
。[Claim 2] An element substrate (12
) a step of forming a trench (15) continuous on all sides in the trench (15), a step of forming an insulator (16) in the trench (15), and an island-like region formed by the trench isolation region (1). (9) A method for manufacturing a semiconductor device, comprising the step of providing at least two electrodes (4) in electrical contact with each other at intervals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01023391A JP3417482B2 (en) | 1991-01-30 | 1991-01-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01023391A JP3417482B2 (en) | 1991-01-30 | 1991-01-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04245469A true JPH04245469A (en) | 1992-09-02 |
| JP3417482B2 JP3417482B2 (en) | 2003-06-16 |
Family
ID=11744579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01023391A Expired - Fee Related JP3417482B2 (en) | 1991-01-30 | 1991-01-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3417482B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020017385A1 (en) * | 2018-07-18 | 2020-01-23 | 株式会社東海理化電機製作所 | Semiconductor device and method for manufacturing same |
-
1991
- 1991-01-30 JP JP01023391A patent/JP3417482B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020017385A1 (en) * | 2018-07-18 | 2020-01-23 | 株式会社東海理化電機製作所 | Semiconductor device and method for manufacturing same |
| JP2020013903A (en) * | 2018-07-18 | 2020-01-23 | 株式会社東海理化電機製作所 | Semiconductor device and manufacturing method thereof |
| US11444074B2 (en) | 2018-07-18 | 2022-09-13 | Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho | Semiconductor device and method for manufacturing same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3417482B2 (en) | 2003-06-16 |
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