JPH06204408A - Diffused resistor for semiconductor device - Google Patents

Abstract

PURPOSE:To improve the accuracy of a resistance value of a diffused resistor layer which is formed by diffusing impurities into a semiconductor device even when an impurity concentration of the diffused resistor layer is lowered. CONSTITUTION:A p-type resistor layer 2 is diffused using a resistor pattern from the surface side of an n-type semiconductor region 1. A p-type resistor surface layer 3 is very shallowly diffused on the surface of the resistor layer 2, using substantially the same resistor pattern, as that of the resistor layer, at a high impurity concentration. An insulation film 11 covers the surfaces of the semiconductor region 1, the resistor layer 2 and the resistor surface layer 3. Then, terminals 12 are led out of both ends of the resistor surface layer 3, whereby a diffused resistor 20 is obtained. The influence of accumulated electric charges caused by mobile ions in the insulation film 11 on a carrier distribution within the resistor layer 2 is interrupted by the resistor surface layer 3, whereby variations in resistance value of the diffused resistor 20 is reduced to less than + or -0.1%, about one order of magnitude lower than with a conventional diffused resistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance which is formed in a semiconductor device by diffusing impurities and is suitable for a case where a particularly accurate resistance value such as a piezo resistance for a pressure sensor or an acceleration sensor is required. .

[0002]

2. Description of the Related Art It is advantageous to use a resistance for an electronic circuit as a built-in resistance in a semiconductor device rather than a so-called external resistance, and it is well known that a field effect transistor is used for this in a digital circuit. However, when a more accurate resistance value is required for analog circuits and sensors, it is customary to use a diffusion resistance created by diffusing impurities of the opposite conductivity type into the semiconductor.

As is well known, a conventional representative example of this diffused resistor is shown in FIG. FIG. 7 (a) is a sectional view and FIG. 7 (b) is a top view. The n-type semiconductor region 1 is, for example, an epitaxial layer grown on a semiconductor substrate of an integrated circuit device, and a p-type resistance layer 2 is diffused from its surface in an elongated pattern to form bulges 2a at both ends thereof. The connection layer 6 is diffused with the same p-type high impurity concentration, and then the connection layer is formed in the window of the insulating film 11 by the aluminum electrode film provided on the insulating film 11 of silicon oxide or phosphosilicate glass covering the surface. It is customary to lead out the terminal 12 connected to 6 to form the diffusion resistance 20, and to cover the upper side thereof with a protective film 13 such as silicon nitride. The resistance layer 2 can be formed with various surface resistances depending on the impurity concentration and the diffusion depth.
Can have various resistance values by appropriately setting the ratio of the sheet resistance and the effective length and width of the pattern of the resistance layer 2. The diffused resistor 20 is used in the state in which a reverse bias voltage is applied to the pn junction between the diffused resistor 20 and the semiconductor region 1.

[0004]

By the way, generally, the diffusion resistance is suitable for low resistance of about several hundred Ω or less, but it is 1 kΩ.
It is not suitable for the above high resistance, and in particular, in order to build a high resistance in a small area of the chip, if the impurity concentration of the resistance layer 2 is reduced to about 10 ¹⁸ atoms / cm ³ or less, the resistance value accuracy decreases. Therefore, there is a problem that variations easily occur. Of course, the amount of impurities introduced into the resistance layer is accurately controlled by the ion implantation method, and the thermal diffusion condition is strictly controlled to improve the accuracy of the resistance value, but the variation is still ± 1%.
The reality is that it is very difficult to reduce below.

The requirement for the accuracy of the resistance value is strict when the diffusion resistance is used for the sensor. Especially, when the diffusion resistance is used as a piezo resistance or a strain gauge, a bridge circuit is composed of four diffusion resistances, so that the resistance value is ± 0.5% or more. It becomes difficult to achieve bridge balance if there is a variation in the resistance value.
It is desirable to keep it below 0.1%. Of course, if the impurity concentration of the resistance layer 2 is increased, this difficulty can be remedied considerably,
The chip area required to make a diffused resistor having the same resistance value increases significantly.

An object of the present invention is to solve the above problems and improve the accuracy of the resistance value of the diffusion resistance even when the impurity concentration of the resistance layer is lowered.

[0007]

In the diffused resistor of the first invention of the present application, the resistance layer of the other conductivity type is diffused from the surface of the semiconductor region of one conductivity type in a resistance pattern to form a surface portion of the resistance layer. Then, diffuse the resistance surface layer of the other conductivity type with the same pattern and a high impurity concentration, and cover the surface of the semiconductor area including the resistance layer and the resistance surface layer with an insulating film. The above-mentioned object is achieved by deriving each of these. The impurity concentration of the resistance surface layer in the above is higher than that of the resistance layer by one digit or more, and usually 10 ¹⁹ atoms /
The diffusion depth is preferably 0.1 to 0.5 μm with a cm ³ or more. Further, it is advantageous that the mask pattern for diffusion of the resistance surface layer is the same as that for the resistance layer and that the resistance surface layer is diffused after the resistance layer is diffused.

In the diffused resistor of the second aspect of the present invention, the resistive layer is diffused similarly to the first aspect of the invention, and the surface layer of one conductivity type is shallowly diffused in the surface portion of the semiconductor region including at least most of the resistive layer. The above-mentioned object is achieved by covering the surface of the semiconductor region including the resistance layer and the surface layer with an insulating film, and deriving the terminals from both ends of the resistance layer. The surface layer in the above is diffused over the entire surface of the semiconductor region including the resistance layer, and the connection layer is diffused in the other conductivity type so as to reach each end of the resistance layer through the surface layer. It is advantageous to derive each terminal from the surface. The diffusion depth of the surface layer is very shallow, and usually 0.5 to 1 μm.

In the diffused resistor of the third aspect of the present invention, the resistance layer of the other conductivity type is buried under the surface portion of the semiconductor region of one conductivity type with a resistance pattern and diffused so that the other surface of the semiconductor region is diffused. The conductive type connection layer is diffused with a high impurity concentration so as to reach both ends of the resistance layer, the surface of the semiconductor region is covered with an insulating film, and the terminals are respectively led out from the connection layer to achieve the above-mentioned object. In order to embed the resistance layer as described above, it is possible to introduce impurities for the purpose deeply by ion implantation and then perform thermal diffusion, but the semiconductor region is made up of upper and lower two-layered structure and the resistance is applied from the surface of the lower semiconductor region. It is advantageous to first diffuse the layer and then grow an epitaxial layer of one conductivity type thereon as the upper semiconductor region. The ion acceleration voltage when burying the resistance layer by ion implantation is preferably 1 MeV or more, preferably several MeV, and the epitaxial layer grown as the upper semiconductor region may be as thin as 1 to 2 μm.

[0010]

According to the present invention, in order to further improve the accuracy of the resistance value of the diffused resistor, it is necessary to prevent the vertical distribution of carriers in the resistance layer from being influenced by the accumulated charges in the insulating film covering the upper side thereof. Focusing on a certain point, the problem is solved by interposing a semiconductor layer for blocking this influence between the resistance layer and the insulating film. That is, although a small amount of mobile ions are present in the insulating film and the electric charge is always accumulated, the distribution of majority carriers on the surface portion of the resistance layer in contact with the insulating film is affected by the electrostatic induction, or is not reversed. The conductivity value of the diffused resistor is likely to vary, and the accumulated amount and distribution of electric charges in the insulating film also tend to vary, and the resistance value of the diffused resistor tends to vary. The lower the impurity concentration, the more remarkable.

Therefore, in the above-described first invention, the resistance surface layer having the same conductivity type as that of the resistance layer, but having a high impurity concentration,
According to the second aspect of the invention, the surface layer having a conductivity type opposite to that of the resistance layer is used.
According to the invention, the semiconductor region of the opposite conductivity type to that of the upper side of the embedded resistance layer blocks the influence of the charge accumulation amount and the distribution state in the insulating film on the vertical distribution of carriers in the resistance layer, thereby reducing the diffusion resistance. Improve resistance accuracy. As a result, in any case, the variation in the resistance value of the diffused resistance can be reduced to ± 0.1%, which is one digit smaller than that of the conventional one, or less.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, second and third in FIGS. 1, 3 and 5, respectively.
A sectional view of a diffused resistor 20 according to the invention is shown in FIG. 2, FIG. 4, and FIG. 6 which are sectional views showing the steps of manufacturing the diffused resistor. The same reference numerals are given to the portions corresponding to those in FIG. 7, and the resistance layer 2 is assumed to be diffused in a planar pattern as shown in FIG. 7 (b).

In the first invention of FIG. 1, an n-type semiconductor region 1 is provided.
Diffusing the p-type resistance layer 2 with a predetermined impurity concentration from the surface of
The p-type resistance surface layer 3 is diffused very shallowly with the same pattern as that, but with an impurity concentration higher by about one digit or more, and the surface of the semiconductor region 1 including the resistance layer 2 and the upper side of the resistance surface layer 3 is oxidized. The terminals 12 are respectively covered with an insulating film 11 made of silicon or the like and made of aluminum electrode films from both ends of the resistance surface layer 3 and are covered with a protective film 13 made of silicon nitride or the like to form a diffusion resistor 20.

FIG. 2 (a) shows a diffusion process of the resistance layer 2. A mask film M1 of silicon oxide is formed on the surface of the semiconductor region 1 by a photo process, and using this as a mask, boron is commonly used as a p-type impurity for ion implantation. By injecting and then thermally diffusing, the resistance layer 2 is usually formed to a depth of 2 to 3 μm. The impurity concentration of the resistance layer 2 is set according to the resistance value required for the diffusion resistance 20, and for example, when the resistance value is about 1 kΩ or more, it is set to 10 ¹⁶ to 10 ¹⁸ atoms / cm ³ . In addition,
In the process of FIG. 2 (a), the resistance layer 2 is set to a predetermined value from the target value,
For example, try to make it with a resistance value as high as 5 to 10%.

Next, FIG. 2 (b) shows a diffusion process of the resistance surface layer 3, in which p-type impurities are ion-implanted into the surface of the resistance layer 2 at a high dose using the same mask film M1 as the previous one, and then short. The resistance surface layer 3 is usually formed to a depth of 0.2 to 0.5 μm by thermal diffusion for a time. The impurity concentration of the resistance surface layer 3 is higher than that of the resistance layer 2 by at least one digit, for example, 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ or more. After that, insulating film 11 and terminal 12
And the protective film 13 are sequentially arranged to complete the state shown in FIG. The resistance value of the diffusion resistor 20 becomes a predetermined value lower than the resistance value of the resistance layer 2 by 5 to 10% by the resistance surface layer 3.

In the first aspect of the invention, since the resistance surface layer 3 having a high impurity concentration is interposed between the resistance layer 2 and the insulating film 11,
Due to the blocking effect, the resistance layer 2 which is the main body of the diffused resistor 20
The carrier distribution inside is not affected by the accumulated charge in the insulating film 11, and the dispersion of the resistance value of the diffusion resistor 20 is ± 0.1
It can be reduced to about%. Further, the first invention can share the same mask film M1 for diffusion of the resistance layer 2 and the resistance surface layer 3, so that there is an advantage that the photoprocess for mask formation can be completed only once.

In the second invention of FIG. 3, the n-type semiconductor region 1 is used.
Of the semiconductor layer 1 including the surface layer 4 and the p-type resistance layer 2 described above is diffused, and the n-type surface layer 4 is shallowly diffused to the surface portion of the semiconductor region 1 including most of the resistance layer 2. The surface of the is covered with an insulating film 11
12 is derived to form the diffusion resistance 20. Although the terminal 12 may be exposed from the resistance layer 2 when the surface layer 4 is diffused, the surface layer 4 may be diffused over the entire surface of the resistance layer 2 and the semiconductor region 1 in the illustrated example. , The p-type connecting layer 6 is diffused from the surface of the surface layer 4 at a high impurity concentration so as to reach each end of the resistance layer 2, and the terminal 12 is led out therefrom. As in FIG. 1, the protective film 13 is provided so as to cover the terminals 12.

FIGS. 4 (a) to 4 (c) show the diffusion resistance 20 of the structure of FIG.
The main manufacturing steps of are shown below. In the process of FIG. 4A, the mask film M1
The resistance layer 2 is formed from the surface of the semiconductor region 1 by diffusion using, and the n-type surface layer 4 is diffused over the entire surface of the semiconductor region 1 and the resistance layer 2 in the next step of FIG. 4 (b). In the step 4 (c), p is formed by diffusion using another mask film M2.
The connecting layer 6 in the form of a diffusion is diffused from the surface of the surface layer 4 to reach the resistance layer 2. After that, the insulating film 11, the terminal 12, and the protective film 13 are sequentially arranged to complete the state shown in FIG. The impurity concentration of the surface layer 4 may be set higher than the impurity concentration of the resistance layer 2 so that the surface of the p-type resistance layer 2 can be changed to the n-type. Good. The connection layer 6 has a high impurity concentration of 10 ¹⁸ to 10 ¹⁹ atoms / cm ³ or more. The steps of FIGS. 4 (b) and 4 (c) may be replaced with each other as appropriate.

In the embodiment of the third invention shown in FIG. 5, the semiconductor region is embedded in the lower semiconductor region 1 and the upper semiconductor region 5 in order to embed the p-type resistance layer under the surface of the n-type semiconductor region. It is a two-layer structure. Therefore, as shown in FIG.
First, the p-type resistance layer 2 is diffused on the surface of the p-type semiconductor region 1 using the mask film M1, and then an n-type epitaxial layer is formed as the upper semiconductor region 5 as shown in FIG. 6B. Is grown so as to cover the film, for example, to a thickness of 1 to 2 μm. Further, in the step of FIG. 6C, the p-type connection layer 6 is diffused from the surface of the semiconductor region 5 with a high impurity concentration so as to reach each end of the resistance layer 2 using the mask film M2, and then the semiconductor region is formed. 5, the insulating film 11 covering the surfaces of the connection layers 6, the terminals 12 connected to each connection layer 6 and the protective film 13 covering the terminals 12 are sequentially arranged to complete the diffusion resistance 20 of FIG.

In both the diffusion resistance 20 according to the second invention and the third invention described above, the p-type resistance layer 2 is isolated from the insulating film 11 by the n-type surface layer 4 or the upper semiconductor region 5. Therefore, the carrier distribution in the resistance layer 2 is not affected by the accumulated charge in the insulating film 11,
It is possible to reduce the variation in the resistance value of the diffused resistor 20 to about ± 0.1% or less. In either case, the photo process is required twice for the mask films M1 and M2, which is the same as the conventional one. In the third aspect of the invention, instead of forming the semiconductor region in a two-layer structure in order to embed the resistance layer 2, the resistance value accuracy is slightly lowered, but the resistance layer 2 is formed from the surface of the single-layer semiconductor region.
The impurities for use may be implanted at a depth of 2 to several μm by ion implantation with a high acceleration voltage of 1 to several MeV.

In order to block the influence of the charges accumulated in the insulating film 11 on the carrier distribution of the resistance layer 2, the resistance surface layer 3 has the same conductivity type as that of the resistance layer 2 in the first invention, and the second and third resistance layers are used.
In the invention, the surface layer 4 and the upper semiconductor region 5 have the conductivity type opposite to that of the resistance layer 2, but in any case, the blocking effect is not so different. In terms of this blocking effect, it is preferable to set the impurity concentration of the resistance surface layer 3 of the same conductivity type as high as possible than that of the resistance layer 2.
The impurity concentration of the surface layer 4 of the opposite conductivity type and the semiconductor region 5 on the upper side need not be particularly low. Diffusion resistance according to the present invention
No. 20 has a surface resistance of the resistance layer 2 of 0.5 to 5 kΩ / □, a diffusion pattern length to width ratio of several to 10 and even a resistance value of several kΩ, the variation is one digit lower than the conventional ±. It can be easily controlled to 0.1% or less, and the area required for making it can be reduced by setting the sheet resistance higher.

[0022]

As described above, according to the present invention, the accuracy of the resistance value of the diffused resistor is likely to be lowered because the carrier distribution in the resistance layer is affected by the accumulated charge in the insulating film above the resistance layer. Focusing on the cause, in the first invention, the resistance surface layer is diffused to the surface portion with the same conductivity type as the resistance layer with a high impurity concentration, and in the second invention, the surface layer is formed on the resistance layer and the surface portion of the semiconductor region. In the third invention, diffusion is performed with the conductivity type opposite to that of the resistance layer, and in the third invention, the resistance layer is embedded and diffused under the surface of the semiconductor region with the conductivity type opposite to that. The influence of the accumulated charge in the insulating film is cut off, and the variation in the resistance value of the diffusion resistance is reduced to 1
It can be reduced by more than an order of magnitude.

The first invention has the advantage that the photoprocess for forming the mask film for impurity diffusion can be completed only once, while the second and third inventions require two photoprocesses as in the conventional case. The first is the control of the resistance value of the diffusion resistance.
It has the advantage of being easier than the invention. Also, the first to the third
In any of the inventions, even if the impurity concentration of the resistance layer is reduced to 10 ¹⁸ atoms / cm ³ or less, the effect of improving the accuracy of the resistance value of the diffusion resistance is high as described above, and the diffusion resistance of 1 kΩ or more is high. In particular, it is particularly advantageous for application to sensor diffusion resistors such as piezoresistors that require high resistance value accuracy.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a diffused resistor according to the first invention.

2A and 2B show the states of the main steps of manufacturing the diffusion resistance of FIG. 1, where FIG. 2A is a sectional view showing a diffusion step of a resistance layer and FIG. 2B is a sectional view showing a diffusion step of a resistance surface layer. It is a figure.

FIG. 3 is a sectional view showing an embodiment of a diffused resistor according to the second invention.

4A and 4B show a state of each main process when the diffusion resistance of FIG. 3 is formed, wherein FIG. 4A is a diffusion process of a resistance layer, FIG. 4B is a diffusion process of a surface layer, and FIG. 3C is a cross-sectional view showing a diffusion process of the connection layer.

FIG. 5 is a sectional view showing an embodiment of a diffused resistor according to the third invention.

6A and 6B show a state of each main step when the diffusion resistance of FIG. 5 is formed, wherein FIG. 6A shows a diffusion step of a resistance layer, and FIG. 6B shows growth of an epitaxial layer as an upper semiconductor region. Process,
FIG. 3C is a cross-sectional view showing the diffusion process of the connection layer.

FIG. 7 is a sectional view of the conventional diffused resistor, and FIG. 7B is a top view thereof.

[Explanation of symbols]

 1 Semiconductor region or lower semiconductor region 2 Resistive layer 3 Resistive surface layer 4 Surface layer 5 Upper semiconductor region or epitaxial layer 6 Connection layer 11 Insulating film 12 Terminal 13 Protective film 20 Diffusion resistance

Claims (3)

[Claims] 1. A resistance layer of the other conductivity type diffused from a surface of a semiconductor region of one conductivity type in a resistance pattern, and a surface of the resistance layer diffused shallowly with a pattern substantially the same as that of the resistance layer and a high impurity concentration. And a resistance surface layer of the other conductivity type and an insulating film covering the surface of the resistance layer and the semiconductor region including the resistance surface layer, wherein terminals are respectively derived from both ends of the resistance surface layer. Diffusion resistance for semiconductor devices. 2. A surface of a semiconductor region including at least most of the resistance layer of the other conductivity type and a resistance layer of the other conductivity type diffused from the surface of the semiconductor region of one conductivity type in a resistance pattern, and shallowly diffused to the surface portion. A diffused resistor for a semiconductor device, comprising a surface layer of one conductivity type and an insulating film covering the surface of the semiconductor region including the surface layer, wherein terminals are led out from both ends of the resistance layer. 3. A resistance layer of the other conductivity type embedded and diffused in a resistance pattern under the surface of the semiconductor region of one conductivity type, and a surface of the semiconductor region so as to reach both ends of the resistance layer, respectively. A connection layer of the other conductivity type diffused at a high impurity concentration, and an insulating film covering the surface of the semiconductor region,
A diffused resistor for a semiconductor device, characterized in that a terminal is derived from each connection layer.