JPH05343397A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance a degree of freedom of wiring without increasing the area occupied by elements by also providing N type buried layers just under the separated oxide films and respectively connecting N type epitaxial layers which will become lands of resistance with the N type buried layers. CONSTITUTION:N type buried layers 2 are selectively formed within a semiconductor substrate 1 and the N type epitaxial layers 3 are grown. Thereafter, the N type epitaxial layers 3 in the region which will become the isolated region is etched to form isolated oxide films 10. In this case, the bottom part of the isolated oxide films 10 is set in contact with the N type buried layers 2. Thereafter, after the P type diffused layers 5 are formed as the resistance elements within the N type epitaxial layers 3 which will become lands of resistance, an oxide film 6 is formed on the surface and aperture windows 11 are provided on the one land of the N type epitaxial layer 3 to form metal wirings 12, 13. Thereby, connection of metal wirings at the surface are no longer necessary and the other metal wirings formed simultaneously between lands of resistance can also be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device incorporating a resistance element.

[0002]

2. Description of the Related Art In recent years, miniaturization of semiconductor integrated circuit devices has progressed, and there has been a demand for reduction of the area occupied by elements. Along with this, from the viewpoint of miniaturization of the resistance element, there is a demand for a technology capable of reducing the occupied area and increasing the degree of freedom of arrangement.
In general, when using a diffusion resistance element, the diffusion layer to be the resistance, it is necessary to form on the diffusion layer of the opposite conductivity type, to set the potential of the lower diffusion layer higher than the potential of the resistance,
Usually, it is set to the same potential as the power supply voltage.

A conventional semiconductor integrated circuit device will be described below. FIG. 3 is a sectional structural view of a conventional semiconductor integrated circuit device, and FIG. 4 is a plan view. 3 and 4, the N-type buried layer 2 is selectively formed in the semiconductor substrate 1, and the N-type epitaxial layer 3 is formed on the semiconductor substrate 1 and the N-type buried layer 2. After that, the P-type isolation diffusion layer 4 is selectively
Then, the P-type diffusion layer 5 is selectively formed in the island of the N-type epitaxial layer surrounded by the P-type isolation diffusion layer 4 and used as a resistance element. After that, an oxide film 6 is formed on the N-type epitaxial layer 3, openings 7 and 8 are selectively provided in the oxide film 6 on the island of the N-type epitaxial layer 3, and electrically connected by a metal wiring 9. ..

In the semiconductor integrated circuit device configured as described above, the N-type epitaxial layer 3 serving as the island of resistance is electrically connected by the metal wiring 9 through the openings 7 and 8 of the oxide film 6, respectively. To be done.

[0005]

However, in the above-mentioned conventional structure, the metal wiring is used to electrically connect the N-type epitaxial layers, which are the islands of the resistance, and to maintain the potential higher than that of the resistance element. .. Therefore, it is impossible to dispose another metal wiring formed at the same time on the surface between the resistor islands. Further, when the N-type epitaxial layers serving as the islands of resistance are separated from each other in distance, it is necessary to dispose the metal wiring particularly long, which greatly restricts the degree of freedom of wiring.
The element occupying area increases. There was an inconvenience.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above conventional problems and to provide a semiconductor integrated circuit device capable of increasing the degree of freedom of wiring without increasing the element occupying area.

[0007]

To achieve this object, in a semiconductor integrated circuit device of the present invention, an N-type buried layer formed in a semiconductor substrate is provided directly below an isolation oxide film to form a resistance island. The N-type epitaxial layers are electrically connected to each other by N-type buried layers.

[0008]

With this structure, all the N-type epitaxial layers serving as the islands of resistance can be electrically connected by the N-type buried layer buried immediately below the isolation oxide film. Therefore, the metal wiring can be electrically connected to one resistance island,
No metal wiring is required for the remaining islands of resistance,
It is possible to increase the degree of freedom in arranging the metal wiring, such as arranging another metal wiring in which the islands of the resistance are formed at the same time, and to reduce the area occupied by the element. Further, in terms of circuit operation, no current flows through the buried diffusion layer and the island of the resistance, and only the function of holding the potential is sufficient, so that there is no problem in increasing the diffusion resistance due to the use of the buried layer. Further, by using a thick isolation oxide film immediately below the metal wiring for crossover, it can be expected to reduce the wiring capacitance which becomes a problem in high frequency characteristics.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a plan view.

First, an N type buried layer 2 is selectively formed in a semiconductor substrate 1 made of P type silicon or the like. As this method, for example, Sb ions are formed by an ion implantation method using a thermal oxide film as a mask, and a diffusion process at about 1200 degrees is performed.
It is formed to a depth of about 2 μm. After that, the N-type epitaxial layer 3 is grown to a thickness of about 1 μm by the CVD method. afterwards,
The N-type epitaxial layer 3 in the region to be the isolation region is selectively etched by about 600 nm, and the isolation oxide film 10 is formed by about 1.5 μm by the selective oxidation method using the nitride film by the CVD method. At this time, the bottom of the isolation oxide film 10 is kept in contact with the N-type buried layer 2. After that, a P-type diffusion layer 5 is formed as a resistance element in the N-type epitaxial layer 3 serving as a resistance island by a boron ion implantation method or the like, and then an oxide film 6 is formed on the surface thereof to form the N-type epitaxial layer 3 An opening window 11 is provided on one of the islands to form metal wirings 12 and 13.

The metal wiring 12 is for taking the potential of the N-type epitaxial layer, and the metal wiring 13 is
The wiring is connected to other active elements formed at the same time.

As described above, according to this embodiment, by using the buried diffusion layer, the surface between the resistor islands is
Other metal wiring formed at the same time can be crossed over.

Although two resistance islands are shown here, it is needless to say that even if there are a plurality of resistance islands or they are separated from each other, they may be connected by a buried layer.

[0015]

As described above, according to the present invention, by electrically connecting the islands of the resistance with the buried layer below the isolation oxide film,
No metal wiring connection is required on the surface, another metal wiring formed at the same time between islands of the resistor can be arranged, the degree of freedom of wiring can be improved, and the area occupied by the element can be reduced. In addition, since a thick isolation oxide film is applied directly under the metal wiring, wiring capacitance with the substrate can be reduced, and a significant reduction in wiring delay, which is a problem with high-frequency characteristics, can be expected, which is an excellent feature for high integration. The semiconductor integrated circuit device can be realized.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a sectional structural view of a conventional semiconductor integrated circuit device.

FIG. 4 is a plan view of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 2 N-type buried layer 3 N-type epitaxial layer 4 P-type isolation diffusion layer 5 P-type diffusion layer 7, 8 Contact window 9, 12, 13 Metal wiring

Claims (1)

[Claims] 1. A second conductivity type impurity diffusion layer selectively formed in a first conductivity type semiconductor substrate and a surface of the first conductivity type semiconductor substrate and second conductivity type impurity diffusion layer. A second conductive type epitaxial layer, a first insulating film selectively formed in the second conductive type epitaxial layer so as to contact the second conductive type impurity layer, and the first insulating film. On a second conductivity type impurity layer formed in the enclosed second conductivity type epitaxial layer, and on a second insulation film formed to cover the second conductivity type epitaxial layer and the first insulation film. A metal wiring selectively disposed, the first
A plurality of islands of the second conductivity type epitaxial layer surrounded by an insulating film are electrically connected to each other by the second conductivity type impurity diffusion layer buried immediately below the first insulating film, and the first island of the second conductivity type epitaxial layer is electrically connected. 1 of the second conductivity type epitaxial layer surrounded by an insulating film
A semiconductor integrated circuit device in which the metal wiring is electrically connected to two islands through an opening of the second insulating film.