JPH01225349A - Material for electronic element formation - Google Patents
Material for electronic element formationInfo
- Publication number
- JPH01225349A JPH01225349A JP5234888A JP5234888A JPH01225349A JP H01225349 A JPH01225349 A JP H01225349A JP 5234888 A JP5234888 A JP 5234888A JP 5234888 A JP5234888 A JP 5234888A JP H01225349 A JPH01225349 A JP H01225349A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- island
- conductive layer
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 title claims description 15
- 230000015572 biosynthetic process Effects 0.000 title abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 15
- 229920005591 polysilicon Polymers 0.000 abstract description 15
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 6
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000003321 amplification Effects 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電子素子製造用の半導体材料に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor materials for manufacturing electronic devices.
支持体層の上に絶縁層を介して設けられた半導体島状領
域を有し、同領域を使って電子素子が作られるようにな
っている電子素子製造用の半導体材料に、例えば、絶縁
層分離基板CDI基板)がある。DI基板は、例えば、
ポリシリコン層からなる支持体層の上に5ift層で電
気的に分離されたシリコン半導体単結晶島状領域を有す
る基板である。各島状領域は、絶縁が完全で、分離容量
が小さく、島状領域内で発生したキャリヤが他の領域に
浸入しないといった利点がある。D1基板の半導体単結
晶島状領域を使って作られる電子素子のひとつに、MO
S)ランジスタがある。MOSトランジスタの場合、増
幅率がL/Wで決まる。Lはチャンネル長であり、Wは
チャンネル幅である、チャンネル幅Wが大きいほど増幅
率が高い。さらにチャンネル長し、チャンネル幅Wが大
きいほど製造プロセスのぶれによる増幅率のバラツキが
押さえられる。MOS)ランジスタを用いた演算増幅器
の場合、チャンネル幅Wやチャンネル長りが大きいほど
増幅度の精度が向上する。For example, a semiconductor material for manufacturing electronic devices, which has a semiconductor island-like region provided on a support layer with an insulating layer interposed therebetween, and is used to manufacture electronic devices, has an insulating layer. There is a separation board (CDI board). The DI board is, for example,
This substrate has a silicon semiconductor single crystal island region electrically separated by a 5ift layer on a support layer made of a polysilicon layer. Each island region has the advantage that the insulation is perfect, the isolation capacitance is small, and carriers generated within the island region do not invade other regions. MO is one of the electronic devices made using the semiconductor single crystal island region of the D1 substrate.
S) There is a transistor. In the case of a MOS transistor, the amplification factor is determined by L/W. L is the channel length, and W is the channel width. The larger the channel width W, the higher the amplification factor. Furthermore, the longer the channel and the wider the channel width W, the more variation in amplification factor due to fluctuations in the manufacturing process can be suppressed. In the case of an operational amplifier using a MOS (MOS) transistor, the accuracy of the amplification degree improves as the channel width W and channel length increase.
しかしながら、ひとつひとつの半導体単結晶島状領域の
面積は余り広くない。そのため、MOSトランジスタの
チャンネル長りやチャンネル@Wを大きくすることは難
しい。また、ひとつの半導体重結晶島状領域にMOS)
ランジスタを多数個形成することも容易ではない。However, the area of each semiconductor single crystal island region is not very large. Therefore, it is difficult to increase the channel length and channel @W of the MOS transistor. In addition, in one semiconductor heavy crystal island region, MOS)
It is also not easy to form a large number of transistors.
半導体単結晶島状領域の面積を大きくすれば、素子形成
面積は増加するが、それでは、基板面積が大きくなって
しまい、素子全体形状の大型化や基板コストの上昇を招
来するという不都合があるこの発明は上記事情に鑑み、
半導体島状領域の面積を増やすことなく、素子形成面積
を大きくできる構造を有する電子素子製造用の半導体材
料を提供することを課題とする。Increasing the area of the semiconductor single-crystal island region increases the device formation area, but this increases the substrate area, resulting in an increase in the overall size of the device and an increase in substrate cost. The invention was made in view of the above circumstances,
It is an object of the present invention to provide a semiconductor material for manufacturing electronic devices, which has a structure that allows the device formation area to be increased without increasing the area of semiconductor island regions.
前記課題を解決するため、この発明の半導体島状領域(
以下、単に「島状領域」という)を有する電子素子製造
用の半導体材料は、絶縁層の外側に導電層が配設されて
いる。In order to solve the above problems, a semiconductor island-like region (
In a semiconductor material for manufacturing electronic devices having a structure (hereinafter simply referred to as an "island region"), a conductive layer is disposed outside an insulating layer.
この発明にかかる電子素子製造用の半導体材料(以下、
単に「半導体材料」と記す)は、島状領域の表面だけで
なく、絶縁層の外側にある導電層を利用して島状領域の
底面も素子形成領域として使うことができる。そのため
、島状領域の大きさは変わらなくとも、素子形成領域が
飛曜的に増加する。Semiconductor material for manufacturing electronic devices according to this invention (hereinafter referred to as
(simply referred to as a "semiconductor material"), not only the surface of the island-like region but also the bottom surface of the island-like region can be used as an element formation region by utilizing the conductive layer outside the insulating layer. Therefore, even if the size of the island region does not change, the element formation region increases dramatically.
以下、この発明にかかる半導体材料について、その−例
をあられす図面を参照しながら詳しく説明する。Hereinafter, examples of the semiconductor material according to the present invention will be explained in detail with reference to the accompanying drawings.
第1図は、この発明の半導体材料の一例であるDI基板
をあられす。FIG. 1 shows a DI substrate which is an example of the semiconductor material of the present invention.
第1図にみるように、DI基板1は、ポリシリコン層(
支持体層)2の上に絶縁層(Si0g層)3で電気的に
分離された島状領域4を有しており、同領域4を使って
電子素子が作られる。As shown in FIG. 1, the DI substrate 1 has a polysilicon layer (
It has an island-like region 4 electrically separated by an insulating layer (SiOg layer) 3 on the support layer) 2, and the electronic device is made using the region 4.
このDI基板lでは、絶縁層3の外側に導電層(ポリシ
リコン層)5が配設され、この導電rii5とポリシリ
コン層2の間には両者の電気的絶縁のための絶縁層(S
ift層)6が形成されていて、絶縁層3、島状領域分
離4および導電層5全体をポリシリコン層2から分離す
るようにしている。導電層5は、島状領域4に形成され
る素子に応じた形状・面積で予め形成されている。In this DI substrate l, a conductive layer (polysilicon layer) 5 is disposed outside the insulating layer 3, and an insulating layer (S
Ift layer) 6 is formed to separate the entire insulating layer 3, island isolation 4 and conductive layer 5 from the polysilicon layer 2. The conductive layer 5 is formed in advance to have a shape and area depending on the elements to be formed in the island region 4 .
DI基板lはつぎのようにして作られている。The DI board l is made as follows.
N−シリコン半導体ウェハ(図示省略)の表面に異方性
エツチングでV溝を形成し、その表面を熱酸化して絶縁
N3用の5i(h層を形成し、その上に導電層5用のポ
リシリコン層を薄く堆積させ(必要ならばパターン化す
る)、その後、さらに絶縁層6用の5ins層を形成す
る。続いて、ポリシリコンN2を厚く堆積させる。しか
るのち、■溝の底があられれるまでウェハの外側から研
磨すると島状領域4が完成する。A V-groove is formed on the surface of an N-silicon semiconductor wafer (not shown) by anisotropic etching, the surface is thermally oxidized to form a 5i (h layer) for the insulating N3, and a 5i (h) layer for the conductive layer 5 is formed on it. A thin layer of polysilicon is deposited (patterned if necessary), followed by another 5ins layer for insulation layer 6. Next, a thick layer of polysilicon N2 is deposited. When the wafer is polished from the outside until it is completely removed, the island-like regions 4 are completed.
第2図は、上記DI基板1のひとつの島状領域4にフォ
トダイオードDとMOS)ランジスタTが形成されてい
る半導体装置をあられす。第3図は、この半導体装置の
回路図である。FIG. 2 shows a semiconductor device in which a photodiode D and a MOS transistor T are formed in one island region 4 of the DI substrate 1. FIG. 3 is a circuit diagram of this semiconductor device.
フォトダイオードDは、島状領域4の表面に形成され、
MOS)ランジスタTは島状領域4の底面に形成されて
いる。フォトダイオードDは、P領域11、N−領域1
2およびN゛領域13からなるPiN構造を有する。1
1’、13’は取り出し電極である。一方、MOSトラ
ンジスタTは、島状領域4の底面に形成され、P領域1
5をソースとし、P領域16をドレインとしている。こ
のMOS)ランジスタTのゲート電極は、絶縁層3の外
側の導電層(ポリシリコン層)5である。A photodiode D is formed on the surface of the island region 4,
A MOS transistor T is formed on the bottom surface of the island region 4. The photodiode D has a P region 11 and an N- region 1.
It has a PiN structure consisting of 2 and N' regions 13. 1
1' and 13' are extraction electrodes. On the other hand, the MOS transistor T is formed on the bottom surface of the island region 4, and the P region 1
5 serves as a source, and P region 16 serves as a drain. The gate electrode of this MOS transistor T is a conductive layer (polysilicon layer) 5 outside the insulating layer 3.
15′、16′、5′は取り出し電極である。このよう
な導電層5があるから島状領域4の底面も素子形成領域
として使うことができるのである。15', 16', and 5' are extraction electrodes. Because of the presence of such a conductive layer 5, the bottom surface of the island region 4 can also be used as an element formation region.
このMOS)ランジスタTは、島状領域4の底面全面を
使って形成されており、利得が大きく、かつ、製造プロ
セスのぶれによる増幅率のバラツキが押さえられるよう
に、チャンネル長しとチャンネル幅Wが大きくなってい
る。This MOS) transistor T is formed using the entire bottom surface of the island region 4, and is designed to have a large gain and suppress variations in amplification factor due to fluctuations in the manufacturing process. is getting bigger.
それだけでなく、通常、フォトダイオードDは相当に大
きな面積(例えば100ミクロン平方)を必要とするが
、このような素子とMOS)ランジスタTがひとつの島
状領域4に共に形成できるのである。Moreover, although the photodiode D normally requires a fairly large area (for example, 100 microns square), such a device and the MOS transistor T can be formed together in one island region 4.
つぎに、第3図の回路を簡単に説明しておく。Next, the circuit shown in FIG. 3 will be briefly explained.
フォトダイオードDに光が入射すると、遮断状態にあっ
たフォトダイオードDが導通し、MOSトランジスタT
のゲートに電圧が加わり、そのため、遮断状態にあった
MOSトランジスタTが導通し、ソースにつながる抵抗
R8の両端に電圧があられれる。光の入射がなくなると
、フォトダイオードDは遮断状態となり、ゲートがゼロ
電位となり、同時にMOS)ランジスタTも遮断状態と
なり、ソースにつながる抵抗R8の両端の電圧はゼロと
なる。When light enters the photodiode D, the photodiode D which was in the cut-off state becomes conductive, and the MOS transistor T
As a result, the MOS transistor T, which has been in a cut-off state, becomes conductive, and a voltage is applied across the resistor R8 connected to the source. When light is no longer incident, the photodiode D is in a cut-off state, and its gate becomes zero potential.At the same time, the MOS transistor T is also cut-off, and the voltage across the resistor R8 connected to the source becomes zero.
なお、この回路の抵抗素子R,、Rsも外付けにせずに
、島状領域4、あるいは、他の島状領域に設けておいて
もよい。Note that the resistive elements R, , Rs of this circuit may also be provided in the island-like region 4 or another island-like region without being provided externally.
i−1’、:、MOS)ランジスタTのソース領域とド
レイン領域となるP領域15.16は、DI基板lの製
造後に形成するのではなく、D1基板1の製造工程で作
るようにしてもよい。P regions 15 and 16, which become the source and drain regions of transistor T (i-1', :, MOS), may be formed during the manufacturing process of D1 substrate 1 instead of being formed after manufacturing DI substrate 1. good.
この発明は上記実施例に限らない。電子素子として、能
動素子だけでなく、第4図にみるように、島状領域4に
受動素子であるコンデンサを形成してもよい。このコン
デンサは、絶縁層3がBP、電体となり、N層19と導
電層3が電極である。広い電極面積(素子形成領域)が
あり、容量を大きくできる。導電層がポリシリコンでな
く、例えば、タングステン等であってもよい。導電層を
バクーンニングすることにより底面に複雑な回路を作る
ようにしてもよい。半導体基板の構造も、第1図に示さ
れた構造に限らない。This invention is not limited to the above embodiments. As the electronic element, not only an active element but also a capacitor, which is a passive element, may be formed in the island region 4 as shown in FIG. In this capacitor, the insulating layer 3 is BP and serves as an electric body, and the N layer 19 and the conductive layer 3 are electrodes. It has a large electrode area (element formation area) and can increase capacitance. The conductive layer may be made of tungsten or the like instead of polysilicon. Complex circuitry may be created on the bottom surface by baking the conductive layer. The structure of the semiconductor substrate is also not limited to the structure shown in FIG.
以上に述べたように、この発明の半導体材料は、絶縁層
の外側に導電層がある。そのため、島状領域の底面も素
子形成領域となるので、島状領域の大きさを増やさなく
とも素子形成面積が大幅に増加する。As described above, the semiconductor material of the present invention has a conductive layer outside the insulating layer. Therefore, since the bottom surface of the island region also serves as an element formation region, the element formation area can be significantly increased without increasing the size of the island region.
第1図は、この発明にかかる半導体材料の一例のDI基
板をあられす断面図、第2図は、上記DI基板1のひと
つの島状領域にフォトダイオードDとMOS)ランジス
タTが形成されている半導体装置をあられす断面図、第
3図は、第2図の半導体装置の回路図、第4図は、前記
半導体材料の島状領域に形成されたコンデンサをあられ
す断面図である。
1・・・DI基板(半導体材料) 2・・・支持体層3
・・・絶縁層 4・・・島状領域 5・・・導電M
(ポリシリコン層)
代理人 弁理士 松 本 武 彦
第3図
第4図FIG. 1 is a cross-sectional view of a DI substrate as an example of the semiconductor material according to the present invention, and FIG. 2 shows a photodiode D and a MOS transistor T formed in one island-like region of the DI substrate 1. FIG. 3 is a circuit diagram of the semiconductor device of FIG. 2, and FIG. 4 is a cross-sectional view of a capacitor formed in the island-like region of the semiconductor material. 1... DI substrate (semiconductor material) 2... Support layer 3
... Insulating layer 4 ... Island region 5 ... Conductive M
(Polysilicon layer) Agent: Patent attorney Takehiko Matsumoto Figure 3 Figure 4
Claims (1)
状領域を有し、同領域を使って電子素子が作られるよう
になっている電子素子製造用の半導体材料において、前
記絶縁層の外側に導電層が配設されていることを特徴と
する電子素子製造用の半導体材料。1. In a semiconductor material for manufacturing an electronic device, which has a semiconductor island-like region provided on a support layer with an insulating layer interposed therebetween, and the semiconductor island-like region is used to manufacture an electronic device, the insulating A semiconductor material for manufacturing electronic devices, characterized in that a conductive layer is provided on the outside of the layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5234888A JPH01225349A (en) | 1988-03-04 | 1988-03-04 | Material for electronic element formation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5234888A JPH01225349A (en) | 1988-03-04 | 1988-03-04 | Material for electronic element formation |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01225349A true JPH01225349A (en) | 1989-09-08 |
Family
ID=12912306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5234888A Pending JPH01225349A (en) | 1988-03-04 | 1988-03-04 | Material for electronic element formation |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01225349A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
US5442223A (en) * | 1990-10-17 | 1995-08-15 | Nippondenso Co., Ltd. | Semiconductor device with stress relief |
-
1988
- 1988-03-04 JP JP5234888A patent/JPH01225349A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5306942A (en) * | 1989-10-11 | 1994-04-26 | Nippondenso Co., Ltd. | Semiconductor device having a shield which is maintained at a reference potential |
US5403769A (en) * | 1989-10-11 | 1995-04-04 | Nippondenso Co., Ltd. | Process for producing a semiconductor device |
US5474952A (en) * | 1989-10-11 | 1995-12-12 | Nippondenso Co., Ltd. | Process for producing a semiconductor device |
US5627399A (en) * | 1989-10-11 | 1997-05-06 | Nippondenso Co., Ltd. | Semiconductor device |
US5442223A (en) * | 1990-10-17 | 1995-08-15 | Nippondenso Co., Ltd. | Semiconductor device with stress relief |
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