JPH0421355B2 - - Google Patents

Info

Publication number
JPH0421355B2
JPH0421355B2 JP59216350A JP21635084A JPH0421355B2 JP H0421355 B2 JPH0421355 B2 JP H0421355B2 JP 59216350 A JP59216350 A JP 59216350A JP 21635084 A JP21635084 A JP 21635084A JP H0421355 B2 JPH0421355 B2 JP H0421355B2
Authority
JP
Japan
Prior art keywords
light
insulating base
led chip
led chips
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59216350A
Other languages
English (en)
Other versions
JPS6196777A (ja
Inventor
Shotaro Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hakuyo Denkyu KK
Original Assignee
Hakuyo Denkyu KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hakuyo Denkyu KK filed Critical Hakuyo Denkyu KK
Priority to JP59216350A priority Critical patent/JPS6196777A/ja
Publication of JPS6196777A publication Critical patent/JPS6196777A/ja
Publication of JPH0421355B2 publication Critical patent/JPH0421355B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15162—Top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Led Device Packages (AREA)

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はLEDチツプ（発光ダイオードチツプ）
を用いた全周囲発光体に関する。
（従来の技術） LEDチツプを用いた発光体として、基台の一
面に該LEDチツプを接着したものが知られてい
る。
（発明が解決しようとする問題点） 従来の発光体は、基板が遮光体であるため
LEDチツプによる配光は限られた立体角内に制
限されてしまい全周囲に亘る配光が得られない不
都合があつた。
本発明はかかる不都合を解消すると共に各方向
の光度を増加することをその目的としたものであ
る。
（問題点を解決するための手段） 本願の第１発明は、多面体から成る絶縁基台の
面にLEDチツプを配設したことを特徴するとし、
第２発明は、多面体から成り稜に突出する板状体
を設けた絶縁基台の面にLEDチツプを配設した
ことを特徴とする。
（実施例） 第１図及び第２図は本発明の一実施例を示す。
図面において、１はセラミツク、ガラス繊維入り
エポキシ樹脂等により例えば各稜の長さが15mm程
度の４面体すなわち３角錐に形成された絶縁基台
で、該基台１の各面には図示のようなパターンで
銀又は銀―パラジウムからなる導電性インクを用
いてシルク印刷等の方法で電極２ａ，２ｂ及び回
路３がプリントされている。この電極２ａにはそ
れぞれLEDチツプ４が導電性接着剤で接着され、
その上面は超音波圧接等の方法により溶接される
金又はアルミニウム等の延性に富んだ金属の微細
線５により他の電極２ｂと接続されている。
図において６はリードピン７の植設部で、リー
ドピン７は絶縁基台１の成形時にインサート成形
により植立させるかあるいは孔に嵌入し接着剤で
固定する。
図面には示さないが、電極２ａ，２ｂにLED
チツプ４を接続した後透光性樹脂を絶縁基台１の
各面のポツテイング等の方法かあるいはリードピ
ン７には触れないようにして基台１全体を透光性
樹脂液にデイツプする等の方法により被覆し、
LEDチツプ４、微細線５等を保護する。かくて、
リードピン７にLEDチツプ４に順方向電流が流
れるように直流電圧を加えると、互に並列に接続
されたLEDチツプ４は一斉に発光し、全周囲に
亘つて配光される。
この実施例では４面体の絶縁基台１を使用した
が、立方体、直方体等の６面体あるいはそれ以上
の多面体にすれば更に配光の均一性が向上する。
また絶縁基台１の前面にLEDチツプ４を配設
したが、用途によつては必ずしも全面でなくても
よい。
更にまた絶縁基台１の各面には１個のLEDチ
ツプ４を配設したが、複数個を配設してもよい。
第３図及び第４図は本発明の他の発光体を示
す。絶縁基台１は、各稜に適宜の高さの板状体８
が基台１の中から放射方向に突出されて例えば接
着により設けられた４面体から成り、その上部の
平坦部には前記板状体８を補強するための３角柱
部９が接着され、その頂部にリードピン７が孔に
挿入して植設されている。
この絶縁基台１の各面に形成する電極２ａ，２
ｂ及び回路３並びに電極２ａに接着するLEDチ
ツプ４はいずれも第１図及び第２図に図示のもの
と同様に作成されている。
尚、電極２ａ，２ｂ及び回路３の作成は３角柱
部９及び板状体８が４面体に取付けられる前に行
なわれる。
かくてリードピン７に直流電圧を加えると、各
面のLEDチツプ４は発光し、各光は板状体８に
よつて反射されるので各面の発光体の光度は増大
する。
各面に配設されたLEDチツプ４の光が異色で
ある場合等において、各面の光を板状体８で互に
遮光すれば各面の光が混合することが防止でき
る。
（発明の効果） 本発明は、多面体から成る絶縁基台の面に
LEDチツプを配設したので、LEDチツプによる
配光が全周囲に亘つて得られる効果を有し、ま
た、多面体から成り稜に突出する板状体を設けた
絶縁基台の面にLEDチツプを配設したので各方
面のLEDチツプによる配光の光度を増加させる
ことができると共に各方面に異なる色を配光する
場合等に互に混合しない効果を有する。
【図面の簡単な説明】
第１図は本発明の全周囲発光体の正面図、第２
図はその表面の展開図、第３図は本発明の他の全
周囲発光体の斜視図、第４図は平面図を示す。 １…絶縁基台、２ａ，２ｂ…電極、３…回路、
４…LEDチツプ、５…微細線、６…リードピン
の植設部、７…リードピン、８…板状体。

Claims (1)

  1. 【特許請求の範囲】 １ 多面体から成る絶縁基台の面にLEDチツプ
    を配設したことを特徴とする全周囲発光体。 ２ 多面体から成り稜に突出する板状体を設けた
    絶縁基台の面にLEDチツプを配設したことを特
    徴とする全周囲発光体。
JP59216350A 1984-10-17 1984-10-17 全周囲発光体 Granted JPS6196777A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59216350A JPS6196777A (ja) 1984-10-17 1984-10-17 全周囲発光体

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59216350A JPS6196777A (ja) 1984-10-17 1984-10-17 全周囲発光体

Publications (2)

Publication Number Publication Date
JPS6196777A JPS6196777A (ja) 1986-05-15
JPH0421355B2 true JPH0421355B2 (ja) 1992-04-09

Family

ID=16687171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59216350A Granted JPS6196777A (ja) 1984-10-17 1984-10-17 全周囲発光体

Country Status (1)

Country Link
JP (1) JPS6196777A (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6418042B2 (ja) * 2015-04-08 2018-11-07 日亜化学工業株式会社 発光装置及び光源装置

Also Published As

Publication number Publication date
JPS6196777A (ja) 1986-05-15

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