JPH04206780A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04206780A
JPH04206780A JP33653190A JP33653190A JPH04206780A JP H04206780 A JPH04206780 A JP H04206780A JP 33653190 A JP33653190 A JP 33653190A JP 33653190 A JP33653190 A JP 33653190A JP H04206780 A JPH04206780 A JP H04206780A
Authority
JP
Japan
Prior art keywords
region
window
type
type semiconductor
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33653190A
Other languages
Japanese (ja)
Inventor
Takao Arai
新井 高雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33653190A priority Critical patent/JPH04206780A/en
Publication of JPH04206780A publication Critical patent/JPH04206780A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce an operating resistance by a method wherein a reverse conductive type first region is formed in one conductive type semiconductor layer and a reverse conductive type second region having high impurity density is formed in this first region. CONSTITUTION:A window is selectively opened in an oxidation film 2 on an N type semiconductor substrate 1, P type impurities are introduced from the surface of the N type semiconductor substrate 1 through this window, and a first P region 3 comprising a PN connection is formed. Thereafter, the oxidation film 2 is again formed, a window is opened in a central portion of the first P region 3, the P type impurities having high density are introduced into the first P region 3 through this window, and a second P region comprising a P<+>-connection, namely a P<+> region 4, is formed. At this time, the P<+> region 4 is formed so as to penetrate into the first P region 3 and reach an N type semiconductor, and the depth is made about slightly deeper than the first P region 3.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はプレーナ型PN接合ダイオードを含む半導体装
置に関し、特に動作抵抗の低い定電圧ダイオードに関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a planar PN junction diode, and particularly to a constant voltage diode with low operating resistance.

〔従来の技術〕[Conventional technology]

従来のこの種の半導体装置の一例を第5図(a)の断面
図に示す。同図のように、N型半導体基板1の表面に設
けた酸化膜2に選択的に窓をあけ、この窓を通してP型
不純物を導入してガードリングとしてP型頭域3Bを形
成する。また、N型半導体基板1に改めて酸化膜を形成
した後、前記P型頭域3Bで囲まれる領域に高濃度のP
型不純物を導入して所要の降伏電圧のP″領域4Bを形
成する。そして、酸化膜2の窓を通してアノード電極5
を形成し、また半導体基板1の裏面にカソード電極6を
形成している。
An example of a conventional semiconductor device of this type is shown in the cross-sectional view of FIG. 5(a). As shown in the figure, a window is selectively formed in the oxide film 2 provided on the surface of the N-type semiconductor substrate 1, and a P-type impurity is introduced through the window to form a P-type head region 3B as a guard ring. Further, after forming an oxide film on the N-type semiconductor substrate 1 again, a high concentration of P is applied to the region surrounded by the P-type head region 3B.
A type impurity is introduced to form a P″ region 4B having a required breakdown voltage.Then, an anode electrode 5 is formed through a window of the oxide film 2.
A cathode electrode 6 is formed on the back surface of the semiconductor substrate 1.

このように構成される半導体装置は、アノード電極5と
カソード電極6をリード等を介して外部回路に接続し、
かつ所定の封止が行われる。
The semiconductor device configured in this manner connects the anode electrode 5 and the cathode electrode 6 to an external circuit via a lead or the like,
And a predetermined sealing is performed.

また、従来の双方向定電圧ダイオードは第6図に示す構
成であり、第5図(a)に相当する部分には同一符号を
付しである。なお、5は表面電極、6は裏面電極である
Further, a conventional bidirectional voltage regulator diode has a configuration shown in FIG. 6, and parts corresponding to those in FIG. 5(a) are given the same reference numerals. Note that 5 is a front electrode, and 6 is a back electrode.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このような構成の半導体装置では、アノード電極5とカ
ソード電極6との間に逆方向に電圧を印加していくと、
第5図(b)のようにPN接合面に空乏層7Bが広がり
、A部分で降伏がおき、電流が流れる。この場合、N型
半導体基板1に比べて空乏層7Bの抵抗率が大きいため
、B部分に電流が集中する。そのため、!区間の抵抗骨
が大きくなり、動作抵抗が大きくなるといった特性上の
問題があった。特に低ノイズタイプの定電圧ダイオード
は、図中のSが非常に小さいので、影響が大きくなる。
In a semiconductor device having such a configuration, when a voltage is applied in the opposite direction between the anode electrode 5 and the cathode electrode 6,
As shown in FIG. 5(b), a depletion layer 7B spreads on the PN junction surface, breakdown occurs at the portion A, and current flows. In this case, since the resistivity of the depletion layer 7B is higher than that of the N-type semiconductor substrate 1, the current is concentrated in the B portion. Therefore,! There was a problem with the characteristics that the resistance bones in the section became large and the movement resistance became large. In particular, in the case of a low-noise type voltage regulator diode, S in the figure is very small, so the influence is large.

このことは、第6図の双方向定電圧ダイオードについて
も同様である。
This also applies to the bidirectional voltage regulator diode shown in FIG.

本発明の目的は、動作抵抗を低減した半導体装置を提供
することにある。
An object of the present invention is to provide a semiconductor device with reduced operating resistance.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、一導電型の半導体層の表面に、
逆導電型の第1の領域を形成してPN接合を構成すると
ともに、この第1の領域内にこれよりも不純物濃度の高
い逆導電型の第2の領域を形成している。
In the semiconductor device of the present invention, on the surface of a semiconductor layer of one conductivity type,
A first region of an opposite conductivity type is formed to constitute a PN junction, and a second region of an opposite conductivity type having a higher impurity concentration is formed within this first region.

この場合、第2の領域は、第1の領域を貫通して一導電
型の半導体層にまで到達させる。
In this case, the second region penetrates the first region and reaches the semiconductor layer of one conductivity type.

〔作用〕[Effect]

本発明によれば、第1の領域および第2の領域と半導体
基板との間に形成される空乏層の区間が狭くなり、かつ
電流の集中領域が狭くなって、動作抵抗を低減する。
According to the present invention, the section of the depletion layer formed between the first region and the second region and the semiconductor substrate becomes narrower, and the current concentration region becomes narrower, thereby reducing the operating resistance.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)は本発明の第1実施例の断面図である。図
において、N型半導体基板1上の酸化膜2に選択的に窓
を開け、この窓を通してN型半導体基板1の表面からP
型不純物を導入し、目的とする降伏電圧より高い降伏電
圧になるようなPN接合を構成する第1のP Si域3
を形成する。
FIG. 1(a) is a sectional view of a first embodiment of the present invention. In the figure, a window is selectively opened in an oxide film 2 on an N-type semiconductor substrate 1, and P from the surface of the N-type semiconductor substrate 1 through this window.
A first P Si region 3 in which type impurities are introduced to form a PN junction that has a breakdown voltage higher than the target breakdown voltage.
form.

その後、改めて酸化膜2を形成し、前記第1のP 91
域3の中央部分に窓をあけ、この窓を通して第1のP領
域3に高濃度のP型不純物を導入し、主接合として目的
とする降伏電圧のP” −N接合を構成する第2のP 
Si域、すなわちP゛領域4を形成する。このとき、P
″領域4は第1のP領域3を貫通してN型半導体の領域
に達するように形成するが、その深さは第1のP領域3
よりも僅かに深い程度に構成している。
After that, an oxide film 2 is formed again, and the first P 91
A window is formed in the center of the region 3, and a high concentration of P-type impurity is introduced into the first P region 3 through this window to form a second P”-N junction with the desired breakdown voltage as the main junction. P
A Si region, that is, a P′ region 4 is formed. At this time, P
``region 4 is formed so as to penetrate through the first P region 3 and reach the N-type semiconductor region, but its depth is smaller than that of the first P region 3.
The structure is slightly deeper than the previous one.

その上で、前記窓を通してP″領域4に接触されるアノ
ード電極5を形成し、またN型半導体基板1の裏面にカ
ソード電極6を形成し、ダイオードを完成している。
Then, an anode electrode 5 is formed to be in contact with the P'' region 4 through the window, and a cathode electrode 6 is formed on the back surface of the N-type semiconductor substrate 1 to complete the diode.

この構成のダイオードによれば、逆方向に電圧を印加し
ていくと、第1図(b)のように空乏層7が広がり、A
部分で降伏がおき、電流が流れる。
According to the diode with this configuration, when a voltage is applied in the reverse direction, the depletion layer 7 expands as shown in FIG.
Breakdown occurs in some parts and current flows.

このとき、空乏層7の抵抗率が大きいため、B部分に電
流が集中する。しかしながら、この構成では、P′″領
域4の深さを第1のP領域3の深さよりも僅かに深(形
成しているため、従来の構成に比較して!区間を短くす
ることができ、この!区間が短くなった分だけ、動作抵
抗を小さくすることが可能となる。
At this time, since the resistivity of the depletion layer 7 is high, the current is concentrated in the B portion. However, in this configuration, the depth of the P'' region 4 is slightly deeper than the depth of the first P region 3, so the section can be shortened compared to the conventional configuration. , it becomes possible to reduce the operating resistance by the amount that this ! section is shortened.

第2図(a)は本発明の第2実施例の断面図であり、前
記実施例に対応する部分には同一符号を付しである。こ
の実施例では、P+領域4Aの深さをP領域3の深さよ
りも僅かに浅く形成し、P゛−P−N接合を構成してい
る。
FIG. 2(a) is a cross-sectional view of a second embodiment of the present invention, and parts corresponding to the previous embodiment are given the same reference numerals. In this embodiment, the depth of the P+ region 4A is formed to be slightly shallower than the depth of the P region 3, forming a P-P-N junction.

この構成によれば、アノード電極5とカソード電極6間
に逆方向の電圧を印加していくと、第2図(b)のよう
に空乏層7Aが広がり、C部分で降伏がおき、電流が流
れる。この場合においても、従来のペレットと比べて!
区間が短くなり、動作抵抗が小さくなる。ただし、P″
領域4Aの深さは、P″領域4Aの空乏層がP ?TI
域3の空乏層の区間(Lの区間)内に存在するように設
定することが肝要である。
According to this configuration, when a voltage in the opposite direction is applied between the anode electrode 5 and the cathode electrode 6, the depletion layer 7A expands as shown in FIG. flows. Even in this case compared to traditional pellets!
The section becomes shorter and the operating resistance becomes smaller. However, P″
The depth of the region 4A is P'', the depletion layer of the region 4A is P?TI
It is important to set it so that it exists within the depletion layer section (L section) of region 3.

なお、このように形成された半導体装置のペレットは、
例えば、第3図のようにガラス管11の中に入れ、両側
からスラグリード12a、12bを当て、加熱によって
ガラス管を溶融して気密封止を行うことでDHD型のダ
イオードが構成される。
Note that the pellet of the semiconductor device formed in this way is
For example, as shown in FIG. 3, a DHD type diode is constructed by placing the diode in a glass tube 11, applying slug leads 12a and 12b from both sides, and melting the glass tube by heating to airtightly seal it.

本発明のダイオードを、主接合サイズが40枚φ程度の
ペレットに適用すれば、動作抵抗を2〜3割低減するこ
とができる。
If the diode of the present invention is applied to a pellet with a main junction size of about 40 pieces φ, the operating resistance can be reduced by 20 to 30%.

第4図は本発明を双方向定電圧ダイオードに適用した第
3実施例の断面図である。
FIG. 4 is a sectional view of a third embodiment in which the present invention is applied to a bidirectional voltage regulator diode.

この実施例では、N型半導体基板1の表裏両面に設けた
酸化膜2a、2bに窓をあけ、この窓を利用して目的と
する降伏電圧より高い降伏電圧になるようなp 85域
3a、3bを形成する。同様にして、酸化膜に窓をあけ
た後、前記P領域3a。
In this embodiment, a window is formed in the oxide films 2a and 2b provided on both the front and back surfaces of the N-type semiconductor substrate 1, and the p85 region 3a, which uses this window to achieve a breakdown voltage higher than the target breakdown voltage, 3b is formed. Similarly, after opening a window in the oxide film, the P region 3a is formed.

3b内に主接合のP″領域4a、4bを形成する。Main junction P'' regions 4a and 4b are formed within 3b.

その上で各面に電極5.6を形成して半導体装置のベレ
ットを形成する。
Then, electrodes 5 and 6 are formed on each surface to form a pellet of a semiconductor device.

この構成によれば、前記各実施例と同様の効果が得られ
るとともに、第6図に示した従来の双方向定電圧ダイオ
ードに比較して、(,1,+12)“ 分だけベレット
サイズを小さくできるという効果も得られる。因に、ベ
レットサイズ0.40mm11程度のベレットに本実施
例を適用すると、ベレットサイズを20%程度縮小する
ことができる。
According to this configuration, the same effects as in each of the embodiments described above can be obtained, and the pellet size is reduced by (,1,+12)" compared to the conventional bidirectional voltage regulator diode shown in FIG. Incidentally, if this embodiment is applied to a pellet with a pellet size of about 0.40 mm11, the pellet size can be reduced by about 20%.

本発明はP型半導体基板にN型の第1および第2の領域
を形成するダイオードにおいても同様に適用することが
できる。
The present invention can be similarly applied to a diode in which N-type first and second regions are formed on a P-type semiconductor substrate.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、一導電型の半導体層に逆
導電型の第1の領域を形成し、この第1の領域内に不純
物濃度の高い逆導電型の第2の領域を形成しているので
、これら第1および第2の領域と半導体基板との間に形
成される空乏層の区間が狭くなり、かつ電流集中範囲が
狭くなり、動作抵抗を低減することができる効果がある
As explained above, the present invention forms a first region of an opposite conductivity type in a semiconductor layer of one conductivity type, and forms a second region of an opposite conductivity type with a high impurity concentration within this first region. Therefore, the section of the depletion layer formed between the first and second regions and the semiconductor substrate becomes narrower, and the range of current concentration becomes narrower, resulting in an effect that the operating resistance can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)は本発明の第1実施例の断面図、同図(b
)はその逆バイアス時の空乏層状態を示す図、第2図(
a)は本発明の第2実施例の断面図、同図(b)はその
逆バイアス時の空乏層状態を示す図、第3図は第1実施
例のパッケージ構造を示す断面図、第4図は本発明の第
3実施例の断面図、第5図(a)は従来のダイオードの
断面図、同図(b)は逆バイアス時の空乏層状態を示す
図、第6図は従来の双方向定電圧ダイオードの断面図で
ある。 1・・・N型半導体基板、2.2a、2b・・・酸化膜
、3.3A、3B・・・P領域(第1の領域)、4.4
A、4B・・・P+頭域(第2の領域)、5・・・アノ
ード電極(表面電極)、6・・・カソード電極(裏面電
極)。 第3図 第4図 第6図
FIG. 1(a) is a sectional view of the first embodiment of the present invention, and FIG. 1(b)
) is a diagram showing the state of the depletion layer at the time of reverse bias, and Figure 2 (
FIG. 3A is a cross-sectional view of the second embodiment of the present invention, FIG. The figure shows a sectional view of the third embodiment of the present invention, FIG. 5(a) is a sectional view of a conventional diode, FIG. FIG. 2 is a cross-sectional view of a bidirectional voltage regulator diode. 1... N-type semiconductor substrate, 2.2a, 2b... Oxide film, 3.3A, 3B... P region (first region), 4.4
A, 4B...P+ head region (second region), 5... Anode electrode (front electrode), 6... Cathode electrode (back electrode). Figure 3 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】 1、一導電型の半導体層の表面に、逆導電型の第1の領
域を形成してPN接合を構成するとともに、この第1の
領域内にこれよりも不純物濃度の高い逆導電型の第2の
領域を形成したことを特徴とする半導体装置。 2、第2の領域は、第1の領域を貫通して一導電型の半
導体層にまで達してなる特許請求の範囲第1項記載の半
導体装置。
[Claims] 1. A first region of an opposite conductivity type is formed on the surface of a semiconductor layer of one conductivity type to constitute a PN junction, and an impurity concentration higher than that of the first region is formed in the first region. A semiconductor device characterized in that a second region of a highly opposite conductivity type is formed. 2. The semiconductor device according to claim 1, wherein the second region extends through the first region to reach the semiconductor layer of one conductivity type.
JP33653190A 1990-11-30 1990-11-30 Semiconductor device Pending JPH04206780A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33653190A JPH04206780A (en) 1990-11-30 1990-11-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33653190A JPH04206780A (en) 1990-11-30 1990-11-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04206780A true JPH04206780A (en) 1992-07-28

Family

ID=18300099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33653190A Pending JPH04206780A (en) 1990-11-30 1990-11-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04206780A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184562B1 (en) * 1996-05-20 2001-02-06 Max-Planck-Gesellschaft Zur Strip detector
WO2019198614A1 (en) * 2018-04-13 2019-10-17 株式会社デンソー Semiconductor device and production method for same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184562B1 (en) * 1996-05-20 2001-02-06 Max-Planck-Gesellschaft Zur Strip detector
WO2019198614A1 (en) * 2018-04-13 2019-10-17 株式会社デンソー Semiconductor device and production method for same
US11322584B2 (en) 2018-04-13 2022-05-03 Denso Corporation Semiconductor device and manufacturing method for same

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