JPH0277136A - Mis field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent a current from flowing through a PN junction when a current is made to flow by applying a positive potential and a negative potential to the source and the drain, respectively, and reduce the recovery time so much that neglection is permitted by connecting a Schottky barrier junction between a source electrode and a channel region, which junction is in parallel to a PN junction between the channel region and the source region, has the same polarity as said PN junction, and has a diffusion potential lower than said PN junction. CONSTITUTION:In an MIS field effect transistor, a Schottky barrier junction 20 is formed in a channel region 4 and from the main surface 2 side. The transistor is constituted of a Schottky barrier type region 21 having a P-type impurity density lower than the channel region 4, and a Schottky barrier electrode 22 formed on a P-type semiconductor region 21, which electrode forms a Schottky junction in combination with the above P-type semiconductor region. Since the source electrode 10 is connected with the channel region 4 via the Schottky barrier junction 20, the high speed operation together with the recovery time reduction are facilitated without decreasing the breakdown strength between the source and the drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improvements in MIS field effect transistors.

[Conventional technology]

FIG. 10 shows a schematic diagram for explaining the operating principle of a conventional MIS field effect transistor. In Figure 10,
5 is an n-type source region, 4 is a p-type channel region, 3 is an n-type drain region, 10 is a source electrode, 242 is a back gate electrode, 7 is a gate electrode, 9 is a drain electrode, 2
7 is a source terminal, 28 is a gate terminal, 29 is a drain terminal, 30 is a channel current component, and 31 is a pn junction current component. Since the p-type channel forming region 4 and the n-type source region 5 are short-circuited by the source electrode 10 and the pack gate electrode 242, the structure is made up of the n-type drain region 3, the p-type channel region 4, and the n-type source region 5. The p-type channel region 4 corresponding to the base of the npn-type parasitic bipolar transistor and the source region 5 corresponding to the emitter are short-circuited, and this parasitic bipolar transistor does not operate, so that the drain-source breakdown voltage of the MIS field effect transistor increases. No decline occurs.゛Figure 10 is a schematic diagram of a conventional MIS field effect transistor, but here we will explain the first structural example of the conventional example.
This will be explained with reference to FIG.

As a conventional example, MIS whose cross-sectional structure is illustrated in FIG.
A field effect transistor is provided.

That is, for example, it has an n° type semiconductor substrate Fi1, and an n type semiconductor layer is formed as a drain region 3 having a flat main surface 2 on the semiconductor substrate 1.

Further, a p-type channel region 4 is formed in the drain region 3 from the main surface 2 side.

Further, a source region 5 having p-type to n-type is formed in channel region 4 from the main surface 2 side without being connected to drain region 3 .

Further, a gate electrode 7 is formed on a region of the channel region 4 facing the main surface 2 with a gate insulator N6 interposed therebetween. In this case, the gate insulating layer 6 extends over the drain region 3 and the channel region 4, the gate electrode 7 extends over the drain region 3, and the insulating layer 8 extends the gate electrode 7 together with the gate insulating layer 6. Surrounded and covered.

Further, a drain electrode 9 is ohmically formed on the semiconductor substrate l on the main surface side opposite to the drain region 3 side.

Further, a source electrode 10 is ohmically formed in the source region 5 . In this case, the source electrode 10 extends onto the insulating layer 8 covering the gate electrode 7, and
P between the channel region 4 facing the main surface 2 and the source region 5 up to the region facing the main surface 2 of the channel region 4
extending across the n-junction 11 and extending its extension 10
a is ohmically connected to the channel region 4.

The above is one structural example of a conventionally proposed MIS field effect transistor.

According to the conventional MIS field effect transistor, if a power supply is connected between the drain electrode 9 and the source electrode 10 through a load, and a control voltage is applied between the source electrode 10 and the gate electrode 7 in this state, the channel Since a channel extending between the y-rain region 3 and the source region 5 is formed in the region 4 according to the control voltage, it can function as a MIS field effect transistor, supplying a current according to the control voltage to the load. That's why.

Further, in the case of the conventional MIS field effect transistor shown in FIG. 11, an npn type parasitic bipolar transistor is formed by a drain region 3, a channel region 4, and a source region 5, which serve as a collector region, a base region, and an emitter region, respectively. has been done. Here, the source electrode 10 connected to the source region 5 extends to above the channel region 4. Therefore, the base region and emitter region of the parasitic bipolar transistor are short-circuited by the source electrode 1o. Therefore, in terms of its function as a MIS field effect transistor, the parasitic bipolar transistor does not substantially operate as a transistor. Therefore, a high drain-source breakdown voltage characteristic can be obtained as a breakdown voltage of the MIS field effect transistor.

[Problem to be solved by the invention]

In the case of the conventional MIS field effect transistor shown in FIG. 11, the source electrode 10 connected to the source region 5 extends above the channel region 4, and the channel region 4 and the drain region 3 form a pn junction. Therefore, when using the polarity of the power supply connected through the load between the drain electrode 9 and the source electrode 10 with the source electrode 10 side being positive, the drain electrode 9
In addition to the channel current component flowing through the source region 5, the channel formed in the channel region 4, and the drain region 3 in that order, there is also an unnecessary component flowing through the pn junction between the channel region 4 and the drain region 3. Nap
An n-junction current component flows. Charges are accumulated in the pn junction due to this pn junction current component, which adversely affects the characteristics of the MrS field effect transistor, such as limiting its operating speed.

Further, it will be explained in detail.

The n-type substrate 1 and the n-type epitaxial layer 3 in FIG. 11 are collectively expressed as an n-type drain region 3 in FIG. Further, the source electrode 10 in FIG. 11 is n in FIG.

A portion connected to type source region 5 and a portion connected to p type channel region 4 are shown separately.

In this structure, the p-type channel region 4 and the n'-type source region 5 are short-circuited because of the npn type formed by the drain region 3, the p-type channel region 4, and the n'-type source region 5, as described above. The base (p-type channel region 4) and emitter (n+
By short-circuiting the type source region 5), this parasitic bipolar transistor is not operated, and the drain-source breakdown voltage of the MIS field effect transistor is ensured. However, the source electrode 10 is connected to the p-type channel region 4.
, a pn junction formed by the rectangular channel region 2 and the n-type drain region 3 exists between the source electrode and the drain electrode of the MIS field effect transistor. Therefore, when the drain-source voltage of the MIS field effect transistor is applied in both positive and negative directions (for example, when used as a MIS rectifier), the current is adjusted to match the direction of the rectifying characteristics of the pn junction. It must flow from the source to the drain. At this time, forward current may flow not only through the inversion layer channel portion (30) but also through this pn junction (31). However, unless special processing is added to the device (for example, doping with a heavy metal as a lifetime killer), the recovery time of this pn junction is long, which may impede circuit operation or increase device loss.

Alternatively, the p-type channel region 4 may not be connected to the source electrode 10, and the pn channel region 4 between the source electrode and the drain electrode may be
If the junction is eliminated, no current will flow through the pn junction and the recovery time will be negligibly small, but since the base of the parasitic bipolar transistor is now open, its collector-emitter breakdown voltage will be significantly reduced. This will result in a decline. This results in a decrease in the drain-source breakdown voltage of the MIS field effect transistor.

In this way, when using a MIS field effect transistor, it is necessary to reduce the recovery time without lowering the drain-source breakdown voltage.

[Means to solve the problem]

The MIS field effect transistor according to the present invention, like the conventional MrS field effect transistor explained in FIG. a channel region having an opposite second conductivity type; a source region connected to the channel region and having a first conductivity type; a gate electrode layer formed on the channel region with a gate insulating layer interposed therebetween; A drain electrode is connected to the region, and a source electrode is connected to the source region.

However, in the MIS field effect transistor having such a configuration, a Schottky barrier junction that is parallel to and has the same polarity as the pn junction formed by the channel region and source region is connected between the source region and the channel region.

More specifically, in the MIS field effect transistor of the present invention, the junction surface between the channel region and the back gate electrode has a rectifying characteristic of the same polarity as the pn junction between the channel region and the source region, and the pn junction A Schottky barrier junction having a diffusion potential smaller than The device further includes the Schottky barrier junction formed at a junction surface between the channel region and the Schottky barrier electrode, and further includes a silicided Schottky barrier electrode.

An object of the present invention is to provide a method for using MIS field effect transistors in which voltages in both positive and negative directions are applied between the source electrode and the drain electrode of the MTS field effect transistor.
An object of the present invention is to provide a MIS field effect transistor with reduced recovery time without lowering the breakdown voltage between the drain and the source.

[For production]

FIG. 1 shows the improved MI of the present invention corresponding to FIG.
A model of an S field effect transistor structure is shown. The operating principle of the improved Mrs field effect transistor according to the present invention will be explained using this figure.

In the present invention, the p-type channel region 4 is not directly connected to the source electrode, and in the meantime, as shown in FIG. The second feature is that a Schottky barrier junction is formed in which the diffusion potential is lower than that of the previous pn junction.

Therefore, except for the above features, the MTS field effect transistor according to the present invention has a similar configuration to the conventional MIS field effect transistor described above in FIG. 11. Although detailed explanation will be omitted, the same function as that of the conventional MIS field effect transistor described above in FIG. 11 is obtained.

Also, in the MIS field effect transistor according to the present invention, a parasitic bipolar transistor consisting of a drain region, a channel region, and a source region is configured similarly to the conventional MIS field effect transistor shown in FIG.

However, in the MIS field effect transistor according to the present invention, the source and channel are connected through a Schottky no-ria junction that is parallel to the pn junction formed from the channel region and the source region, has the same polarity, and has a low diffusion potential. Therefore, there is no pn junction current component flowing through the pn junction between the channel region and the drain region. Further, the Schottky barrier junction is formed from a channel region and a source region.
Since the parasitic bipolar transistor has a lower diffusion potential than the n-junction, the diffusion potential of the pn junction due to the channel region and the source region is suppressed by the diffusion potential of the Schottky barrier junction added according to the present invention, so that the parasitic bipolar transistor operates as a transistor. Do not do this. , therefore,
A MIS field effect transistor having a high drain-source breakdown voltage can be obtained.

As mentioned above, FIG. 1 is a schematic diagram for explaining the operating principle of the MIS field effect transistor of the present invention. In FIG. 1, 32 is a Schottky barrier junction;
Other symbols used are those mentioned above. The back gate electrode 242 of the p-type channel region 4 is directly connected to the source electrode 10.
A Schottky barrier junction 32 having the same polarity and lower diffusion potential is formed in parallel with the pn junction between the p-type channel region 4 and the n'-type source region 5, without being connected to the p-type channel region 4 and the n'-type source region 5. Therefore, when current flows from the source to the drain, p
Since the newly provided Schottky barrier junction 32 prevents the pn junction current component 31 of the type channel region 4-n type drain region 3 from flowing, only the channel current component 30 flows, and the current is caused by the pn junction current component. The long recovery time can be reduced to a negligible amount.

Furthermore, when a positive potential is applied to the drain and a negative potential is applied to the source, the pn junction voltage between the p-type channel region 4 and the n°-type source region 5 is suppressed by the forward voltage drop (diffusion potential) of the Schottky barrier junction 32. Since the parasitic bipolar transistor does not operate, the drain-source breakdown voltage does not become lower than that of the conventional structure.

What has been described above is not limited to n-channel type MIS field effect transistors, but is similarly possible with p-channel type MIs field effect transistors.

〔Example〕

Next, as shown in FIGS. 2, 3, and 4, M
The first aspect of the S field effect transistor. Let us describe the second and third embodiments.

In FIGS. 2 to 4, FIGS. 1 and 10.

Portions corresponding to those in FIG. 11 are given the same reference numerals and detailed explanations will be omitted.

The MIS field effect transistor according to the present invention shown in FIGS. 2 to 4 has the same structure as the conventional MIS field effect transistor described above in FIG. 11, except for the following points.

That is, between the source electrode 10 and the channel region 4,
It is connected in parallel to the pn junction formed by the channel region 4 and source region 5 via a Schottky barrier junction having the same polarity and a lower diffusion potential than the pn junction.

In the case of the first embodiment of the present invention shown in FIG. 2, this Schottky barrier junction 20 is formed in the channel region 4 from the main surface 2 side, and has a lower p-type impurity density than the channel region 4. and a Schottky barrier electrode 22 formed on the p-type semiconductor region 21 to form a Schottky junction therebetween.

Further, in the case of the second embodiment according to the present invention shown in FIG. There is.

That is, the p-type semiconductor region 21 has the same impurity density as in the first embodiment of the present invention shown in FIG. 2, and a Schottky barrier junction 20 is formed between it and the electrode 10. be.

Further, in the case of the third embodiment according to the present invention shown in FIG. 4, the Schottky barrier junction 20 is formed on the channel region 4 and forms a heterojunction with the channel region 4. The semiconductor region 23 is made of a material (for example, GaP when the channel region 4 is Si) and has n-type, and a metal recombination center is introduced to ohmically connect the semiconductor region 23 and the source electrode 10. Ohmic forming layer 24 made of semiconductor etc.
It is made up of.

First and second MIS field effect transistors according to the present invention
According to the third embodiment, since the source electrode 10 is connected to the channel region 4 via the Schottky barrier junction 20, the recovery time can be reduced and the speed increased without lowering the breakdown voltage between the drain and the source. As mentioned above, this makes it easier.

Next, FIG. 5, FIG. 6, and FIG. 7 show that the MI according to the present invention is
Fourth, fifth and sixth embodiments of the S field effect transistor will be described.

4th. In the fifth and sixth embodiments, in the first, second and third embodiments, the Schottky barrier junction 20 and the pn junction 11 formed by the channel region 4 and source region 5 formed on the main surface 2 are absolutely It is characterized in that it is formed locally on the channel region 4 while being covered by the layer 26, and the other configurations are the same as those of the first, second, and third embodiments, respectively. has.

That is, FIG. 5 (fourth embodiment) corresponds to FIG. 2 (first embodiment), and FIG. 6 (fifth embodiment) corresponds to FIG. 3 (second embodiment). 7 (sixth embodiment) is the fourth embodiment.
This corresponds to the figure (third embodiment).

FIG. 8 shows a cross-sectional view of a vertical MIS field effect transistor as a seventh embodiment of the present invention. In the figure, 22 is an electrode for forming a Schottky barrier, 21 is a region for forming a p-type Schottky barrier, and the other symbols used are as described above. In the conventional structure, the p-type Schottky barrier forming region 21 has a high doping concentration because it makes ohmic contact with the source electrode, but in this example, it exhibits rectifying characteristics as a Schottky barrier. It is formed as a region with low acceptor concentration (
For example, the effective fourth degree is lowered by doping with impurities that serve as donors.) The forward voltage drop (diffusion potential) between this region 12 and the Schottky barrier forming electrode 22 is smaller than that of the pn junction between the p-type channel region 4 and the n-type source region 5, and the semiconductor A Schottky barrier junction is formed with the anode on the side and the cathode on the electrode side. The Schottky barrier forming electrode 2 is connected to the n''' type source region 4 so as to be in ohmic contact with the n''' type source region 4.
2 metal types (e.g. Cr, Pt, 'rt, M
o, W, etc.) and the doping concentration of the p-type Schottky barrier forming region 21.

In this case, the Schottky barrier forming electrode 2
Since the Schottky barrier junction 20 between the p-type Schottky barrier forming region 21 of No. 2 and the p-n junction between the p-type channel region 4 and the n-type epitaxial layer 3 are formed in series in opposite directions, When the channel is turned on and a positive potential is applied to the source and a negative potential is applied to the drain, current flows only through the channel portion and does not flow through the pn junction. Therefore, the recovery time becomes negligibly small.

In addition, when the channel is turned off and a reverse voltage is applied, that is, a positive potential to the drain and a negative potential to the source, the voltage between the p-type channel region 4 and the n-type source region 5 increases due to the diffusion of the Schottky barrier junction. Since the npn structure of the n-type epitaxial layer 3, p-type channel forming region 4, and n-type source region 5 does not operate as a transistor, the withstand voltage between the drain and source is lower than that of the conventional structure. will not decrease.

The manufacturing advantage is that the source electrode has a two-layer structure consisting of the source electrode 10 and the Schottky barrier forming electrode 22, so in the manufacturing process, the Schottky barrier forming process can be performed at the same time as the source electrode 10. It is possible. That is, when forming the source electrode, the Schottky barrier electrode 22 is deposited first, and then the source electrode IO can be deposited and processed using the same mask.

As described above, according to the structure of the present invention, when used as a rectifying element, a MIS field effect transistor that has a reverse breakdown voltage equivalent to that of a conventional structure and whose recovery time is negligible can be used as a Schottky It can be manufactured without creating a new mask for the barrier forming electrode.

The above explanation can be applied not only to vertical MIS field effect transistors, but also to horizontal MIS field effect transistors, MIS field effect transistors of other structures, or p-channel type MIS field effect transistors, and the effect can be obtained. can be given.

In addition, the present invention can be applied to various types of MIS field effect transistors, and various modifications and changes are also possible.

FIG. 9 is a sectional view of a vertical MIs field effect transistor as an eighth embodiment of the present invention. In the figure, 23 is a silicide electrode, and other symbols are the same as those described above. The silicide electrode 23 for forming the Schottky barrier is formed by performing the step of forming a source electrode in the manufacturing process of a normal MIS field effect transistor as described below.

A metal to be silicided (for example, Pt, Ni, Ti, W, etc.) is deposited on the entire surface where the source electrode 10 is to be formed.

Silicide and p-type shot 1 - key barrier formation region 21
A Schottky barrier 20 is formed between the metal 2 and the metal 2 to make ohmic contact with the n-type source region 5.
3 and the doping concentration of the p-type Schottky barrier forming region 21. Next, the contact portion between the metal and silicon is silicided by heat treatment.

Next, the metal that has not been turned into silicide is removed by chemical etching. Finally, a source electrode 10 is formed.

〔Effect of the invention〕

In the MIS field effect transistor according to the present invention,
In order to incorporate a new Schottky barrier junction, when current is passed with the source at a positive potential and the drain at a negative potential, the p
No current flows through the n-junction, the device operates only as a majority carrier device in the channel portion, and the recovery time can be reduced to a negligible level. As a result, there is an advantage that loss due to reverse current during the recovery period can be reduced.

Moreover, in one embodiment of the MIS field effect transistor according to the present invention, there is no need to create a special mask for the Schottky barrier forming metal, and the process steps are minimal compared to the production of a normal MIS field effect transistor. It can be manufactured at an additional cost.

Furthermore, compared to the conventional structure, by introducing the Schottky barrier junction according to the gist of the present invention, the recovery time can be reduced without reducing the withstand voltage between the drain and the source, and the speed can be increased. .

[Brief explanation of the drawing]

FIG. 1 shows a schematic diagram for explaining the operating principle of the MIS field effect transistor of the present invention. FIGS. 2, 3 and 4 each show an M according to the present invention.
First of all, IS field effect transistors. FIG. 7 is a schematic cross-sectional view showing second and third embodiments. FIGS. 5, 6 and 7 respectively show the M according to the present invention.
4th TS field effect transistor. FIG. 7 is a schematic cross-sectional view showing fifth and sixth embodiments. FIG. 8 is a cross-sectional view of a vertical MrS field effect transistor as a seventh embodiment of the present invention. FIG. 9 is a sectional view of a vertical MIS field effect transistor as an eighth embodiment of the present invention. FIG. 10 is a schematic diagram illustrating the operating principle of a conventional MIS field effect transistor. FIG. 11 shows a cross-sectional view of a conventional MIS field effect transistor. 1...n゛Semiconductor substrate 2...Main surface 3...Drain region 4...Channel forming region 5...Source region 6...Gate insulating layer 7...Gate electrode 8.26. ...Insulating layer 9...Drain electrode 10...Source electrode 10a...Source electrode extension 11...PN junction 20.32...Schottky barrier junction 21...p
Type Schottky barrier formation ml Area 22... Schottky barrier forming electrode 23... Silicide electrode 24... Ohmic formation layer 27... Source terminal 28... Gate terminal 29... Drain terminal 30... ...Channel current component 31...PN junction current component 242...Back gate electrode patent applicant Nippon Telegraph and Telephone Co., Ltd. agent Patent attorney Tama Mushi Kugobeha Kaname, Ni

Claims (1)

[Claims] 1. A drain region having a first conductivity type, a channel region having a second conductivity type in contact with the drain region, and a source having the first conductivity type in contact with the channel region. a gate electrode layer formed on the channel region via a gate insulating layer, a drain electrode connected to the drain region, and a source electrode connected to the source region.
In the S field effect transistor, the pn junction is provided between the source electrode and the channel region in parallel with and of the same polarity as the pn junction formed by the channel region and the source region.
A MIS field effect transistor characterized in that a Schottky barrier junction having a lower diffusion potential than the junction is connected. 2. A drain region, a channel region, a source region, and a gate electrode on the surface of the channel region via an insulating film;
a back gate electrode connected to the channel region, a source electrode connected to the source region, a drain electrode connected to the drain region, and the source electrode and the back gate electrode connected to each other by a short circuit or the same metal layer. In the MIS field effect transistor formed as a
A MIS field effect transistor comprising a Schottky barrier junction that has a rectifying characteristic of the same polarity as a pn junction between a channel region and a source region, and has a diffusion potential lower than that of the pn junction. 3. A Schottky barrier electrode containing a metal impurity is provided on the channel region, and the source electrode is formed on the Schottky barrier electrode. The MIS field effect transistor according to claim 1, further comprising the Schottky barrier junction formed on a junction surface. 4. The MIS field effect transistor according to claim 3, comprising a silicided Schottky barrier electrode.