JPH0494572A - Lateral type thyristor - Google Patents
Lateral type thyristorInfo
- Publication number
- JPH0494572A JPH0494572A JP21272790A JP21272790A JPH0494572A JP H0494572 A JPH0494572 A JP H0494572A JP 21272790 A JP21272790 A JP 21272790A JP 21272790 A JP21272790 A JP 21272790A JP H0494572 A JPH0494572 A JP H0494572A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- anode
- layer
- substrate
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 238000009792 diffusion process Methods 0.000 claims description 63
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000000903 blocking effect Effects 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】 [産業上の利用分野] 本発明は、ラテラル型サイリスタに関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a lateral thyristor.
[従来の技術]
第2図は従来のラテラル型サイリスクを示すもので、図
において、lはN型基板、2はアノードを構成するP型
拡散層、3はゲートを構成するP型拡散層、4はカソー
ドを構成するN型拡散層、5は前記カソードN型拡散層
4にオーミック接続されたカソード電極、6は前記アノ
ードP型拡散層2にオーミック接続されたアノード電極
、7は絶縁膜、8は空乏層をそれぞれ示す。なお、同図
(a世順方向阻止状態、すなわちカソード電極5の電位
に対してアノード電極6の電位が高い状態で発生する空
乏層8を示し、同図(ロ)は逆方向阻止状態、すなわち
カソード電極5の電位に対してアノード電極6の電位が
低い状態で発生する空乏層8を示す、また、図中寸法り
は、アノードP型拡散層2とゲー)P型拡散層3との距
離を示す。[Prior Art] Fig. 2 shows a conventional lateral type silicon risk. In the figure, l denotes an N-type substrate, 2 denotes a P-type diffusion layer constituting an anode, 3 denotes a P-type diffusion layer constituting a gate, 4 is an N-type diffusion layer constituting a cathode; 5 is a cathode electrode ohmically connected to the cathode N-type diffusion layer 4; 6 is an anode electrode ohmically connected to the anode P-type diffusion layer 2; 7 is an insulating film; 8 indicates a depletion layer, respectively. In addition, the same figure (a) shows the depletion layer 8 generated in the forward direction blocking state, that is, the state where the potential of the anode electrode 6 is higher than the potential of the cathode electrode 5, and the same figure (b) shows the reverse direction blocking state, that is, The figure shows a depletion layer 8 that occurs when the potential of the anode electrode 6 is lower than the potential of the cathode electrode 5. The dimension in the figure is the distance between the anode P-type diffusion layer 2 and the anode P-type diffusion layer 3. shows.
かかる従来のラテラル型サイリスタにおいて、第2図(
萄に示すように順方向阻止状態の場合、耐圧(順方向阻
止電圧)は、空乏層8がゲートP型拡散層3からN型基
板1の方向へ拡がり、アノードP型拡散層2へ到達して
アノード・カソード間に急激に電流が流れ始めた時の印
加電圧である。In such a conventional lateral type thyristor, as shown in FIG.
As shown in the figure, in the forward blocking state, the breakdown voltage (forward blocking voltage) is determined by the fact that the depletion layer 8 spreads from the gate P-type diffusion layer 3 toward the N-type substrate 1 and reaches the anode P-type diffusion layer 2. This is the applied voltage when current suddenly begins to flow between the anode and cathode.
また、第2図(b)に示すように逆方向阻止状態の場合
、耐圧(逆方向阻止電圧)は、空乏層8がアノードP型
拡散層2からN型基板1の方向へ拡がり、ゲー)P型拡
散層3へ到達してアノード・カソード間に急激に電流が
流れ始めた時の印加電圧である。In addition, as shown in FIG. 2(b), in the reverse blocking state, the withstand voltage (reverse blocking voltage) is increased by the depletion layer 8 expanding from the anode P-type diffusion layer 2 toward the N-type substrate 1, This is the applied voltage when the current reaches the P-type diffusion layer 3 and suddenly begins to flow between the anode and cathode.
[発明が解決しようとする課B]
ところで、上記のようにサイリスタの耐圧は、順方向、
逆方向共に、アノードP型拡散層2とゲートP型拡散層
3との距離りに依存しているため、より高い耐圧のサイ
リスクを得るには、距離りを大きくする必要がある。そ
のため、チップ面積の増大を招き、歩留り低下、コスト
上昇につながるという問題があった。[Problem B to be solved by the invention] By the way, as mentioned above, the withstand voltage of the thyristor is
Both in the reverse direction depend on the distance between the anode P-type diffusion layer 2 and the gate P-type diffusion layer 3, so it is necessary to increase the distance in order to obtain a higher voltage resistance. Therefore, there was a problem in that the chip area increased, leading to a decrease in yield and an increase in cost.
本発明は、上記問題点に鑑みなされたもので、その目的
とするところは、チップ面積を増大せずに高耐圧が得ら
れるラテラル型サイリスクを提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a lateral type silicon risk that can obtain a high withstand voltage without increasing the chip area.
[1!!を解決するための手段]
本発明は上記課題を解決するために、半導体基板表面に
、該基板と反対の導電型のアノード拡散層とゲート拡散
層を離間して形成するとともに、該ゲート拡散層表面に
前記基板と同じ導電型のカソード拡散層を形成してなる
ラテラル型サイリスタにおいて、前記アノード拡散層と
ゲート拡散層の間であって前記基板表面に、前記アノー
ド及びゲート拡散層からそれぞれ離間して、前記アノー
ド及びゲート拡散層より低く、かつ、前記基板と同程度
以上の不純物濃度を有する基板と反対の導電型の拡散層
を形成したことを特徴とする。[1! ! Means for Solving the Problems] In order to solve the above problems, the present invention forms an anode diffusion layer and a gate diffusion layer of the opposite conductivity type on the surface of a semiconductor substrate, separated from each other, and also separates the gate diffusion layer from the semiconductor substrate. In a lateral type thyristor in which a cathode diffusion layer of the same conductivity type as the substrate is formed on a surface thereof, a cathode diffusion layer is formed on the substrate surface between the anode diffusion layer and the gate diffusion layer, and spaced apart from the anode and gate diffusion layers, respectively. The method is characterized in that a diffusion layer of a conductivity type opposite to that of the substrate is formed, which has an impurity concentration lower than that of the anode and gate diffusion layers and approximately equal to or higher than that of the substrate.
[実施例] 本発明の実施例を図面を参照して説明する。[Example] Embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例を示すもので、前記従来例と
異なる点は、アノードP型拡散層2とゲ−)P型拡散層
3の間であってN型基板1の表面に、アノード及びゲー
ト拡散層2.3からそれぞれ離間してP型拡散層9を形
成したことで、そのP型拡散層9の不純物濃度は、アノ
ードP型拡散層2及びゲー)P型拡散層より低く、N型
基板1と同程度以上である。従って、このP型拡散層9
は高抵抗層となる。なお、他の構成は前記従来例と同様
であるので、同等構成に同一符号を付すことにより説明
を省略する。FIG. 1 shows an embodiment of the present invention, which differs from the conventional example described above in that it is between the anode P-type diffusion layer 2 and the gate electrode P-type diffusion layer 3 and is located on the surface of the N-type substrate 1. By forming the P-type diffusion layer 9 apart from the anode and gate diffusion layers 2.3, the impurity concentration of the P-type diffusion layer 9 is lower than that of the anode P-type diffusion layer 2 and the gate diffusion layer 2.3. It is low, and is comparable to or higher than that of the N-type substrate 1. Therefore, this P type diffusion layer 9
becomes a high resistance layer. Note that the other configurations are the same as those of the conventional example, so the description will be omitted by assigning the same reference numerals to the equivalent configurations.
このように構成されたラテラル型サイリスタにおいて、
第1図(a)に示すように順方向阻止状態の場合、すな
わちカソード電極5の電位に対してアノード電極6の電
位が高い場合、アノード・カソード間印加電圧の増加に
従って、空乏層8はゲートP型拡散層3からN型基板1
の方向へ拡がり、P型拡散層9に到達する。さらに印加
電圧を増加、すると、空乏層8はP型拡散層9のアノー
ド側端からさらに拡がり、アノードP型拡散層2に到達
する。In the lateral type thyristor configured in this way,
As shown in FIG. 1(a), in the forward blocking state, that is, when the potential of the anode electrode 6 is higher than the potential of the cathode electrode 5, as the voltage applied between the anode and cathode increases, the depletion layer 8 From P type diffusion layer 3 to N type substrate 1
It spreads in the direction of and reaches the P-type diffusion layer 9. When the applied voltage is further increased, the depletion layer 8 further expands from the anode side end of the P-type diffusion layer 9 and reaches the anode P-type diffusion layer 2.
P型拡散層9がない場合、すなわち従来例の場合、空乏
層8がアノードP型拡散層2に到達した時、急激に電流
が流れるた、め、その時の印加電圧がサイリスタの耐圧
となったが、本発明では、不純物濃度の低い、すなわち
高抵抗のP型拡散層9が存在するため、空乏層8がアノ
ードP型拡散層2に到達した時、僅かに1t21iLが
流れ始める。In the case where there is no P-type diffusion layer 9, that is, in the case of the conventional example, when the depletion layer 8 reaches the anode P-type diffusion layer 2, a current flows rapidly, so the applied voltage at that time becomes the withstand voltage of the thyristor. However, in the present invention, since the P-type diffusion layer 9 with low impurity concentration, that is, high resistance, exists, when the depletion layer 8 reaches the anode P-type diffusion layer 2, a slight amount of 1t21iL starts to flow.
この時の印加電圧は、アノードP型拡散層2とゲートP
型拡散層3との距11Lが、前記従来例と等しい場合、
従来例の印加電圧よりも僅かに低い。The applied voltage at this time is between the anode P type diffusion layer 2 and the gate P.
When the distance 11L to the type diffusion layer 3 is equal to that of the conventional example,
This is slightly lower than the applied voltage in the conventional example.
しかし、従来例の場合、この印加電圧で2.激に電流が
流れ、これ以上の電圧では使用できないが、本発明の場
合、高抵抗P型拡散層9が存在するため流れる電流は微
小であり、実使用上問題はなく、さらに印加電圧を加え
ることができる。従って、本発明の場合、従来例の印加
電圧以上でも使用可能となる。本発明に係るサイリスタ
の耐圧(この場合、順方向阻止電圧)は、アノード・カ
ソード間に流れる電圧が規定電流(実使用上問題となる
電流量)を鰯えた時の印加電圧である。However, in the case of the conventional example, 2. A strong current flows and it cannot be used at a higher voltage, but in the case of the present invention, the current flowing is minute because of the presence of the high resistance P-type diffusion layer 9, and there is no problem in actual use, and further applied voltage is applied. be able to. Therefore, in the case of the present invention, it is possible to use the applied voltage higher than that of the conventional example. The withstand voltage (in this case, forward blocking voltage) of the thyristor according to the present invention is the voltage applied when the voltage flowing between the anode and cathode reaches a specified current (current amount that is a problem in practical use).
また、第1図Φ)に示すように逆方向阻止状態の場合は
、アノード・カソード間の電位は順方向の場合と逆にな
り、空乏層8の拡がりも逆にアノードP型拡散層2側か
ら拡がるが、順方向の場合と同様に、高抵抗P型拡散層
9の存在により、従来例より高耐圧が得られる。In addition, as shown in FIG. 1 Φ), in the case of the reverse blocking state, the potential between the anode and the cathode is opposite to that in the forward direction, and the spread of the depletion layer 8 is also opposite to the anode P-type diffusion layer 2 side. However, as in the case of the forward direction, due to the presence of the high-resistance P-type diffusion layer 9, a higher withstand voltage can be obtained than in the conventional example.
[発明の効果1
本発明は上記のように、アノード拡散層とゲート拡散層
の間の基板表面に、アノード及びゲート拡散層より低く
、基板と同程度以上の不純物濃度を有する高抵抗拡散層
を設けたことにより、アノード拡散層とゲート拡散層と
の間の距離を大きくすることなく高耐圧を実現すること
ができる。すなわち、チップ面積を増大する必要がない
ので、歩留り低下、コスト上昇を招くことなく高耐圧の
ラテラル型サイリスタを得ることができる。[Effect of the Invention 1] As described above, the present invention provides a high resistance diffusion layer on the substrate surface between the anode diffusion layer and the gate diffusion layer, which has an impurity concentration lower than that of the anode and gate diffusion layers and approximately equal to or higher than that of the substrate. By providing this, a high breakdown voltage can be achieved without increasing the distance between the anode diffusion layer and the gate diffusion layer. That is, since there is no need to increase the chip area, a lateral type thyristor with high breakdown voltage can be obtained without reducing yield or increasing cost.
また、言い換えれば、所望耐圧を実現するには、本発明
によれば、アノード・カソード間の距離を小さくするこ
とができるので、チップ面積を小さくすることができ、
歩留りの向上、コストの低減を図ることができる。In other words, in order to achieve the desired breakdown voltage, according to the present invention, the distance between the anode and cathode can be reduced, so the chip area can be reduced.
It is possible to improve yield and reduce costs.
第1図は本発明の一実施例を示す断面図で、(a)は順
方向阻止状態を示し、〜)は逆方向阻止状態を示すもの
である。第2図は従来例を示す断面図で、(a)は順方
向阻止状態を示し、(b)は逆方向阻止状態を示すもの
である。
1・・・半導体基板、2・・・アノード拡散層、3・・
・ゲート拡散層、4・・・カソード拡散層、訃・・カソ
ード電極、6・・・アノード電極、7・・・絶縁膜、8
・・・空乏層、9・・・高抵抗拡散層。FIG. 1 is a sectional view showing an embodiment of the present invention, in which (a) shows a forward direction blocking state, and (-) shows a reverse direction blocking state. FIG. 2 is a sectional view showing a conventional example, in which (a) shows a forward direction blocking state and (b) shows a reverse direction blocking state. 1... Semiconductor substrate, 2... Anode diffusion layer, 3...
・Gate diffusion layer, 4... Cathode diffusion layer, 2... Cathode electrode, 6... Anode electrode, 7... Insulating film, 8
... Depletion layer, 9... High resistance diffusion layer.
Claims (1)
ード拡散層とゲート拡散層を離間して形成するとともに
、該ゲート拡散層表面に前記基板と同じ導電型のカソー
ド拡散層を形成してなるラテラル型サイリスタにおいて
、前記アノード拡散層とゲート拡散層の間であって前記
基板表面に、前記アノード及びゲート拡散層からそれぞ
れ離間して、前記アノード及びゲート拡散層より低く、
かつ、前記基板と同程度以上の不純物濃度を有する基板
と反対の導電型の拡散層を形成したことを特徴とするラ
テラル型サイリスタ。(1) On the surface of a semiconductor substrate, an anode diffusion layer and a gate diffusion layer of the conductivity type opposite to that of the substrate are formed at a distance, and a cathode diffusion layer of the same conductivity type as the substrate is formed on the surface of the gate diffusion layer. In the lateral type thyristor, between the anode diffusion layer and the gate diffusion layer, on the substrate surface, spaced apart from the anode and gate diffusion layer, respectively, and lower than the anode and gate diffusion layer;
A lateral type thyristor further comprising a diffusion layer of a conductivity type opposite to that of the substrate and having an impurity concentration comparable to or higher than that of the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21272790A JPH0494572A (en) | 1990-08-10 | 1990-08-10 | Lateral type thyristor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21272790A JPH0494572A (en) | 1990-08-10 | 1990-08-10 | Lateral type thyristor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0494572A true JPH0494572A (en) | 1992-03-26 |
Family
ID=16627436
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21272790A Pending JPH0494572A (en) | 1990-08-10 | 1990-08-10 | Lateral type thyristor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0494572A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999056320A1 (en) * | 1998-04-28 | 1999-11-04 | North Carolina State University | Bidirectional silicon carbide power devices having voltage supporting regions therein for providing improved blocking voltage capability |
-
1990
- 1990-08-10 JP JP21272790A patent/JPH0494572A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999056320A1 (en) * | 1998-04-28 | 1999-11-04 | North Carolina State University | Bidirectional silicon carbide power devices having voltage supporting regions therein for providing improved blocking voltage capability |
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