JPH0316257A - Semiconductor device - Google Patents

Abstract

PURPOSE:To smoothen the fluctuation of an ON-voltage at the time of turning-ON with a very small current by a method wherein a MOS-FET which is connected in parallel with a bipolar transistor is compounded in addition to a MOS-FET for driving the base of the bipolar transistor. CONSTITUTION:An n-p-n bipolar transistor 41 is composed of an n<+>-type substrate 1, an n<->-type layer 2, a p<+>-type layer 3 and an n<+>-type layer 4. An n-type channel MOS-FET 51 is composed of the n<->-type layer 2, a first channel region 7 and an n<+>-type layer 5. Further, a p-type channel MOS-FET 52 is composed of the p<+>-type layer 3, a second channel region 8 and a p<+>-type layer 6 and an n-type channel MOS-FET 53 is composed of the n-type layer 2, a third channel region 15 and the n<+>-type layer 4. If a positive voltage is applied to the gates of the MOS-FET 51 and the MOS-FET 53 through a gate terminal G while a positive voltage is applied to the collector terminal C of such a semiconductor device, a current is made to flow between the collector terminal C and an emitter terminal E through the channel of the MOS-FET 53. Therefore, an ON-voltage is gradually increased. With this constitution, the fluctuation of the ON-voltage at the time of turning-ON can be smoothened.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is used in horizontal deflection circuits for televisions and displays, and is a semiconductor VT device that is a composite of a bibolar transistor and a MOSFET for driving its base. Regarding. (Prior art) In recent years, as televisions and displays have become higher in quality, higher in definition, and larger in area, switching devices used in horizontal deflection circuits have become faster, lower in loss, larger in current, and higher in voltage resistance. I'm here. However, since conventional bipolar transistors are current-driven, a major drawback is that the base drive circuit cannot be simplified. In order to make this possible, a bipolar transistor has been proposed in which a base driving MOSFET is combined. Figure 2 shows its structure. In the figure, a high resistance n° layer 2 (second region) is formed on the n1 base layer 1 (first region),
A p° layer 3 (third region) and a p9 layer 6 (sixth region) adjacent to the p0 layer 3 with an interval are selectively formed on the surface of the n′ layer 2, and further p′layer 3 (third region) is formed. selectively sandwich the n layer 4 (fourth region) and the n layer 4 (fourth region) on the surface of the
form layer 5 (fifth region), layer 2 of layer 3
The surface region sandwiched between the base drive MO
The channel region 7 (first channel region) of the SFET is defined as a second channel region 8, and the part sandwiched between the p' layer 3 and the p0 layer 6 on the surface of the n'' layer 2 is defined as a second channel region 8. A gate electrode 1O is formed to be connected to the gate terminal G via the gate insulating film 9 so as to cover the channel region 7 and the second channel region 8 at the same time.
t8ill is in contact with the n'' layer 5, a factory electric wire l2 is in contact with the n9 layer 4, and a collector electrode 13 is placed in contact with the surface of the n'' substrate 1 and connected to the collector terminal C.
Further, an electric wire 14 is placed in contact with the p layer 6 and is electrically connected to the metal electrode 12 and the metal ivy terminal.

The p'' layer L 6+ n '' layer 4.5 and the electrodes 10, 1112.14 of this semiconductor device are shaped like strips as shown in the figure.The semiconductor device shown in FIG. When a positive voltage is applied to the gate electrode lO when a voltage of n″a! is applied, n″a! It,n layer 2
, first channel region 7. n° layer 5. A current flows through the carrier diversion electrode 1l to the p3 layer 3, which is the base region of the npn bipolar transistor with the n' layer 4 as the collector, the n' layer 2, and the n medium board l as the collector. The bipolar transistor turns on. Also, the gate voltage 110
When a negative voltage is applied to the second channel region 8, the p layer 6
, the potential of the p′″ layer 3 via the electrode l4 is
2, so the bipolar transistor turns off, [Ll! which the invention attempts to solve! ! ) In the above semiconductor device, current begins to flow when the potential of the collector becomes higher than the diffusion potential of the junction between the p0 layer 3 and the n' layer 4. Therefore, as shown in the output characteristics of FIG. 3, almost no current flows at a collector voltage below the diffusion potential (approximately 0.5 V).

When this semiconductor device is used in a horizontal deflection circuit for a television, etc., fluctuations in the on-voltage during turn-on with a minute current cause undesirable phenomena such as severe distortion. It is an object of the present invention to eliminate the above-mentioned drawbacks and to make it possible to operate ξ even when the collector voltage of the composite bipolar transistor is low.
The object of the present invention is to provide a semiconductor device in which a current flows between the collector and the collector, and the on-voltage changes slowly during turn-on. (Means for solving the problem) In order to achieve the above object, the semiconductor device of the present invention has the following features:
A first region of the first conductivity type with high impurity concentration, f on the first region
a second head region of the first conductivity type with a low impurity concentration;
The third and sixth regions of the second conductivity type are selectively formed on the surface of the second region with a gap between them, and the third and sixth regions are selectively formed on the surface of the third region with a high impurity concentration and a gap between them. a fourth region and a fifth region of the first conductivity type having The portion sandwiched between the third region and the sixth region is the second channel region, the portion sandwiched between the second head region and the fourth region on the surface of the third region is the third channel region, and on each channel region. Each wA
Gate electrodes are formed with each other through the edge film, an electrode that contacts the surfaces of the third and fifth regions at the same time, an ivy electrode that contacts the surface of the fourth region, and a lid electrode that contacts the surface of the sixth region. It is equipped with electrodes to be connected and a collector electrode that contacts the surface of the first region. (Function) In addition to the first MOSFET formed between the fourth region and the surface of the second region via the fifth region, a third MOSFET whose channel formation region is directly formed between the second region and the second region is formed. The gate of the first MOSFET and the third MOSFET are simultaneously connected.
By applying a voltage to the gate of the OSFET, even if the collector voltage is small, the collector 1 is applied through the third MOSFET.
T-stream flows.

As a result, fluctuations in collector voltage can be suppressed even when turn-on is caused by a small collector current. [Embodiment] FIG. 1 shows the structure of an embodiment of the present invention. What differs from the conventional structure in FIG. The electrode l1 is partially omitted, and the part sandwiched between the n° layer 4 (fourth region) and the n- layer 2 (second region) of the p° layer 3 is used as the third channel region l5 and is placed thereon. The gate electrode 17 is provided through the gate insulation film WA16, and this is connected to the gate terminal G together with the gate electrode 10.The gate wA edge 11116 and the gate electrode l7 are connected to the gate insulation &I film 9 and the gate electrode IO at the same time. Figure 4 is an equivalent circuit diagram of this semiconductor device.
The npn bipolar transistor 41 is formed on an n9 substrate x. n-
! 12+p◆layer 3. It is formed of n layer 4. Further, the n-channel MOSFET 51 has an n-channel MOSFET 28 first channel region 7. Due to the n0 layer 5, the p-channel MOSFET 52 has a second channel region 8. By the p′″ layer 6,
The n-channel MOSFET 53 is formed by the n layer 2l and the third channel region i5+n'' layer 4.The diode 42 is formed by the p0 layer 6, the n layer 2 and the n'' substrate l. When a positive voltage is applied to the collector terminal C of such a semiconductor device, the MOsFE
751, when a positive voltage is applied to the gate of MOSFET 53, the collector potential becomes ξ
Even if it is not higher than the diffusion potential of the vine-base junction, M
Since a current flows between the collector terminal C and the emitter terminal E through the channel of the OSFET 53, the output characteristics become as shown in FIG. 5, and the on-voltage gradually increases from 0. 6th
The figure shows another embodiment of the present invention, in which the positions of the band-shaped n' layer 4 and the 00 layer 5, which are also band-shaped, are alternately exchanged in the band-shaped p' layer 3. Therefore, the positions of the bipolar transistor 41 and the MOSFET 53 are alternately exchanged, and the current density within the plane of the semiconductor substrate becomes uniform. Therefore, bibolar transistor 41 and MO3FET 53
The area ratio can be freely selected, which has the effect of making it possible to manufacture a semiconductor device with any current capacity. Furthermore, since the MOSFET 9L is sandwiched between the bibolar transistor sections, the conductivity modulation effect of the bibolar 1 transistor section also extends to the MOSFET section, which also has the effect of lowering the on-resistance of the MOSFET T53 connected in parallel.

It is clear that the above explanation holds true even if the n-type and p-type in each region are replaced. [Effects of the Invention] According to the present invention, the semiconductor base of a bipolar transistor {
On the other hand, MO for bibolar transistor base operation
By combining a bipolar transistor and a parallel-connected MOSFET in addition to SFET, it is possible to flow a minute collector current even when the collector potential is low, so the fluctuation of the on-voltage at turn-on with a minute current is gentle. This prevents undesirable phenomena such as screen distortion when used in horizontal deflection circuits such as televisions.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
The figure shows a conventional MOSFF. A perspective cross-sectional view of a T compound bibolar transistor, FIG. 3 is a diagram of the output characteristic vA of the semiconductor device in FIG. 2, FIG. 4 is an equivalent circuit diagram of the semiconductor *I in FIG. FIG. 6 is a perspective sectional view of a semiconductor device according to another embodiment of the present invention. 1: n'' substrate (first region) 2: n single layer (second region) 3: p'ii (third region) 4: n'' layer (
(fourth region), 5: n'' layer (fifth region), 6: p''
11 (sixth region) 7: first channel region, 8: second channel region, 9, 16: gate insulating film, 10. 17
Gate electrode, 11, 14; electrode, 12j Ivy electrode, t3: collector electrode, l5: third channel region. Dai! People (H + f. 1 Mountain Ro Iwao Figure 1 C Figure 4 ■ Figure 5 Figure 3 V Figure 6

Claims (1)

[Claims] 1) A first region of the first conductivity type with a high impurity concentration, a second region of the first conductivity type with a low impurity concentration laminated on the first region, and a layer formed selectively on the surface of the second region and between them. A third region and a sixth region of the second conductivity type having a gap, and a fourth region and a fifth region of the first conductivity type selectively formed on the surface of the third region and having a high impurity concentration and a gap therebetween. The part of the surface of the third region sandwiched between the second region and the fifth region is called the first channel region, and the part of the surface of the second region sandwiched between the third region and the sixth region is called the channel region. The portion sandwiched between the second and fourth regions on the surface of the second channel region and the third region is defined as a third channel region, and gate electrodes are formed on each channel region with an insulating film interposed therebetween. An electrode that simultaneously contacts the surfaces of the third region and the fifth region, an emitter electrode that contacts the surface of the fourth region, an electrode that contacts the surface of the sixth region and is connected to the emitter electrode, and a collector electrode that contacts the surface of the first region. A semiconductor device characterized by: