JP2611429B2 - Conductivity modulation type MOSFET - Google Patents
Conductivity modulation type MOSFETInfo
- Publication number
- JP2611429B2 JP2611429B2 JP1134409A JP13440989A JP2611429B2 JP 2611429 B2 JP2611429 B2 JP 2611429B2 JP 1134409 A JP1134409 A JP 1134409A JP 13440989 A JP13440989 A JP 13440989A JP 2611429 B2 JP2611429 B2 JP 2611429B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- layer
- conductivity modulation
- mosfet
- conductivity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 description 52
- 230000000694 effects Effects 0.000 description 11
- 108091006146 Channels Proteins 0.000 description 10
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はMOSFETのソース領域とドレイン領域の間のベ
ース領域に伝導度変調を起こさせる伝導度変調型MOSFET
に関する。Description: BACKGROUND OF THE INVENTION The present invention relates to a conductivity-modulated MOSFET that causes conductivity modulation in a base region between a source region and a drain region of a MOSFET.
About.
伝導度変調型MOSFETは、通常の電力用縦型MOSFETのド
レインイン領域をソース領域とは逆の導電型にしたもの
である。第２図は従来の伝導度変調型MOSFETの断面構造
を示す。ドレイン層となるP+層１の上にN+バッファ層２
を介して積層されたN-ベース層３には、表面の酸化膜５
の上に設けられた多結晶シリコンゲート６をマスクとし
て不純物を導入する、いわゆるセルフアラインメント方
式によりチャネルとなるべきＰ層４が形成されている。
Ｐ層４ゲート６の下方の外側にはN+ソース層７が形成さ
れている。この素子のゲート６に電圧印加することによ
りチャネル層４の、ゲート酸化膜５の直下の表面層は反
転層となり、Ｎチャネルが形成される。このため、ソー
ス層７から電子がチャネルを通りベース層３に注入され
る。これにより伝導度変調が生じ、ベース層３の内部で
は電子と正孔が過剰に存在することとなり、低抵抗素子
となる。In the conductivity modulation type MOSFET, the drain-in region of a normal power vertical MOSFET has a conductivity type opposite to that of the source region. FIG. 2 shows a sectional structure of a conventional conductivity modulation type MOSFET. N + buffer layer 2 on P + layer 1 serving as a drain layer
The oxide film 5 on the surface of the N − base layer 3 laminated via
P layer 4 to be a channel is formed by a so-called self-alignment method in which impurities are introduced using polycrystalline silicon gate 6 provided as a mask as a mask.
An N + source layer 7 is formed outside the P layer 4 below the gate 6. By applying a voltage to the gate 6 of this element, the surface layer of the channel layer 4 immediately below the gate oxide film 5 becomes an inversion layer, and an N channel is formed. Therefore, electrons are injected from the source layer 7 into the base layer 3 through the channel. As a result, conductivity modulation occurs, and electrons and holes are excessively present inside the base layer 3, and a low-resistance element is obtained.
このように、伝導度変調型MOSFETは、絶縁ゲート型の
バイポーラ素子として最近注目を集めている素子であ
る。As described above, the conductivity modulation type MOSFET is an element that has recently attracted attention as an insulated gate bipolar element.
第２図に示すような構造をもつ伝導度変調型MOSFETで
は接合型FET（JFET）効果を免れない。このFFET効果と
は、N-ベース層とＰ層４との接合により形成されるピル
トインポテンシアルにより図に点線で領界を示した空乏
層81が生ずることである。JFET効果により電子ｅの通り
道82は大幅に狭められる。このため電子ｅの注入は制限
され、これはまた正孔の注入の制限ともなる。ひとたび
大きな伝導度変調が生じてしまえば、空乏層81には多量
の正孔が落ち込むため、その空乏層は電圧を維持するこ
とができず消滅してしまい、JFET効果はなくなってしま
う。このように伝導度変調型MOSFETでは、ひとたび伝導
度変調が生じてしまえばJFET効果は問題ないため、オン
・オフのみを問題とするスイッチング素子ではほとんど
問題とはならない。しかしながら、電流・電圧（Ｉ−
Ｖ）特性が第３図のようになり、立ち上がりに遅れが生
ずるため、Ｉ−Ｖ特性における立ち上がりに左右される
場合、極めて重要な問題になってくる。例えば、伝導度
変調型MOSFETをテレビの水平偏向に用いる場合、このＩ
−Ｖ特性における上ち上がり特性は画面そのものにノイ
ズが生ずるため問題である。In the conductivity modulation type MOSFET having the structure as shown in FIG. 2, the junction type FET (JFET) effect cannot be avoided. The FFET effect means that a depletion layer 81 indicated by a dotted line in the figure is generated by a pyrt impotential formed by a junction between the N − base layer and the P layer 4. The passage 82 of the electron e is greatly narrowed by the JFET effect. This limits the injection of electrons e, which also limits the injection of holes. Once a large conductivity modulation occurs, a large amount of holes fall into the depletion layer 81, so that the depletion layer cannot maintain the voltage and disappears, and the JFET effect disappears. As described above, in the conductivity modulation type MOSFET, once the conductivity modulation occurs, the JFET effect is not a problem, and therefore, there is almost no problem in a switching element that only involves ON / OFF. However, the current / voltage (I−
V) The characteristics are as shown in FIG. 3 and the rise is delayed, which is a very important problem when the characteristics are influenced by the rise in the IV characteristics. For example, when a conductivity modulation type MOSFET is used for horizontal deflection of a television,
The rising characteristic in the -V characteristic is a problem because noise occurs on the screen itself.
JFET効果を低減する方法としては、ゲート６の横幅を
拡げＰ層４の間隔を大きくすればよいが、このようにす
ると一定面積下では逆に総チャネル長が減ってしまい、
電子の注入が減少するので、総合的に見ては余り良い方
法とは言えない。As a method of reducing the JFET effect, the lateral width of the gate 6 may be increased and the interval between the P layers 4 may be increased. However, in this case, the total channel length is reduced under a certain area.
Since the injection of electrons is reduced, it is not a very good method overall.
本発明の目的は、上述の問題を解決し、Ｉ−Ｖ特性の
立ち上がりの遅れのない伝導度変調型MOSFETを提供する
ことにある。An object of the present invention is to solve the above-mentioned problem and to provide a conductivity modulation type MOSFET having no delay in rising of the IV characteristic.
上記の目的を達成するために、本発明は、第一導電形
の第一層と第二導電形の第二層とが積層され、その第二
層の表面部に選択的に第一導電形の第一領域が、さらに
その第一領域の表面部に選択的に第二導電形の第二領域
が形成され、第二層と第二領域にはさまれた第一領域の
表面上に絶縁膜を介してゲートが設けられ、第二領域表
面および第二領域の第二層より遠い側にある第一領域表
面に一方の主電極が接触する伝導度変調型MOSFETにおい
て、第一領域の表面部に選択的に第二導電形の第三領域
が形成され、第一領域の表面から第三領域に隣接して第
二層に達するＵ字状の溝が形成され、第二層と第三領域
にはさまれた第一領域の露出するＵ字状溝内側面上に絶
縁膜を介して補助ゲートが設けられ、第三領域および第
三領域の反Ｕ字状溝側にある第一領域表面に前記一方の
主電極が接触するものとする。In order to achieve the above object, the present invention provides a first conductive type first layer and a second conductive type second layer are laminated, the first conductive type selectively on the surface of the second layer. A second region of the second conductivity type is selectively formed on the surface of the first region, and an insulating layer is formed on the surface of the first region sandwiched between the second layer and the second region. In a conductivity-modulated MOSFET in which a gate is provided via a film and one main electrode is in contact with the surface of the second region and the surface of the first region farther from the second layer of the second region, the surface of the first region A third region of the second conductivity type is selectively formed in the portion, a U-shaped groove extending from the surface of the first region to the second region adjacent to the third region is formed, and the second layer and the third layer are formed. An auxiliary gate is provided on the exposed inner surface of the U-shaped groove of the first region sandwiched between the regions, with an insulating film interposed therebetween, and the third region and the third region on the side opposite to the U-shaped groove. Wherein the one main electrode shall be in contact with a certain first region surface.
第一領域の表面から第二層に達するＵ字状の溝の側壁
上に補助ゲートを有するMOS構造を備えた伝導度変調MOS
FETにおいては、JFET効果が存在せず、印加電圧に応じ
て主電極から第三領域を経てチャネルを通じてキャリア
が注入され、第二層に伝導度変調を起こすため、第４図
に示すように一様に立上るＩ−Ｖ特性を示す。この特性
が第３図に示した従来の平面型の伝導濃度長型MOSFETの
特性と組合わせるため、第３図のようなＩ−Ｖ特性の立
上りの遅れば解消される。しかし素子のすべてをＵ字状
溝内側面上のMOS構造を備えた伝導度変調型MOSFETにし
ないのは、JFET効果は無くても、負荷短絡時などに流れ
る大電流により素子の温度が上昇し、温度が上昇した部
分の少量キャリアの注入が増加しその部分に電流が集中
しさらに温度が上昇するというポジティブフィ−ドバッ
クにより素子破壊が発生し易く耐量の点で劣るためで、
耐量は表面上にMOS構造を備えた平板型の伝導度変調型M
OSFETで負わせるようにする。A conductivity-modulated MOS having a MOS structure with an auxiliary gate on the side wall of a U-shaped groove reaching the second layer from the surface of the first region
In the FET, since the JFET effect does not exist, carriers are injected from the main electrode through the channel through the third region in accordance with the applied voltage, and conductivity modulation occurs in the second layer. It shows the IV characteristic which rises as follows. Since this characteristic is combined with the characteristic of the conventional planar conduction-concentration long-type MOSFET shown in FIG. 3, it is eliminated if the rise of the IV characteristic as shown in FIG. 3 is delayed. However, the reason that not all of the elements are the conductivity modulation type MOSFETs having the MOS structure on the inner surface of the U-shaped groove is that even if there is no JFET effect, the temperature of the element rises due to a large current flowing when a load is short-circuited. This is because the injection of a small amount of carriers in the portion where the temperature rises increases, current concentrates in that portion, and the temperature is further increased.
The withstand capability is a conductivity type M of a flat plate type with a MOS structure on the surface.
OSFET will be charged.
第１図は本発明の一実施例を断面で示し、第２図と共
通の部物には同一の符号が付されている。第２図に示し
たようにP+ドレイン層（第一層）1,N+バッファ層（第二
層）2,N-ベース層（第二層）３が積層され、第二層の表
面部にＰ形のチャネル（第１領域）４を形成し、チャネ
ル層４の表面部にN+ソース層（第二領域）７を形成した
基板上にMOS構造を有する従来の平面型の伝導度変調型M
OSETの基板の縁部のN+ソース層（第三領域）71に接して
Ｕ字状の溝11が形成されている。溝11は基板表面からの
選択的なウエットエッチングあるいはドライエッチング
で形成できる。この溝の内面にゲート酸化膜５を形成し
たのち、減圧CVD法で多結晶シリコンゲート６を堆積さ
せる。このゲートはＰチャネル層４およびベース層３の
表面にゲート酸化膜５を介して設ける平板型の伝導度変
調型MOSFETのゲート６と同時に形成できる。Ａ部の平板
型の伝導度変調型MOSFETとＢ部のＵ字状溝を有する伝導
度変調型MOSFETのそれぞれのソース層７および71は両ゲ
ート６とPSG層９を介するソース電極12に接触し、ソー
ス電極はソース端子Ｓに接続され、チャネル層４にも高
不純物濃度のP++層13を介して接触している。P++層はラ
ッチアップの防止とソース電極12のオーム性接触の双方
に役立つ。両多結晶シリコンゲート６には、PSG層９の
開口部でゲート電極14が接触し、ゲート電極14はゲート
端子Ｇと接続されている。なおドレイン層１には図示し
ないドレイン電極を介してドレイン端子Ｄが接続されて
いる。FIG. 1 shows an embodiment of the present invention in cross section, and parts common to FIG. 2 are denoted by the same reference numerals. As shown in FIG. 2, a P + drain layer (first layer) 1, an N + buffer layer (second layer) 2, and an N − base layer (second layer) 3 are laminated, and a surface portion of the second layer is formed. A conventional planar conductivity modulation having a MOS structure on a substrate having a P-type channel (first region) 4 formed thereon and an N + source layer (second region) 7 formed on the surface of the channel layer 4. Type M
A U-shaped groove 11 is formed in contact with the N + source layer (third region) 71 at the edge of the OSET substrate. The groove 11 can be formed by selective wet etching or dry etching from the substrate surface. After a gate oxide film 5 is formed on the inner surface of this groove, a polycrystalline silicon gate 6 is deposited by a low pressure CVD method. This gate can be formed simultaneously with the gate 6 of a planar conductivity modulation type MOSFET provided on the surfaces of the P channel layer 4 and the base layer 3 via the gate oxide film 5. The source layers 7 and 71 of the plate-type conductivity modulation MOSFET of part A and the conductivity modulation MOSFET having a U-shaped groove of part B are in contact with the source electrode 12 via both gates 6 and PSG layer 9. The source electrode is connected to the source terminal S, and is also in contact with the channel layer 4 through the P ++ layer 13 having a high impurity concentration. The P ++ layer helps both prevent latch-up and ohmic contact of the source electrode 12. The gate electrode 14 is in contact with both polycrystalline silicon gates 6 at the opening of the PSG layer 9, and the gate electrode 14 is connected to the gate terminal G. The drain terminal D is connected to the drain layer 1 via a drain electrode (not shown).
このような構造にすることにより、Ｓ端子とＤ端子の
間にＡ部の平板型の伝導度変調型MOSFETのＢ部のＵ型の
伝導度変調型MOSFETの双方が並列に接続されることにな
り、電圧の立上り時にはＢ部の基板面に垂直なチャネル
を通して電子が注入されていく。ひき続き電子の注入に
より正孔がドレイン側から注入され、伝導度変調が生ず
る。ひとたび大きな伝導度変調が生じてしまえば、前述
のようにJFET効果はなくなり、Ａ部の伝導度変調型MOSF
ETに大きな電流が流れる。この結果、第３図に示されて
いるようなＩ−Ｖ特性の立上りの遅れはなくなる。Ｂ部
のＵ型の伝導度変調型MOSFETの耐量は低いが、素子面積
の大部分を占めるＡ部の平板状伝導度変調型MOSFETが耐
量を負うため、問題はない。With such a structure, both the U-type conductivity modulation type MOSFET in the B portion and the U-type conductivity modulation type MOSFET in the B portion are connected in parallel between the S terminal and the D terminal. When the voltage rises, electrons are injected through a channel perpendicular to the substrate surface of the portion B. Subsequently, holes are injected from the drain side by electron injection, and conductivity modulation occurs. Once large conductivity modulation occurs, the JFET effect disappears as described above, and the conductivity modulation type MOSF
A large current flows through ET. As a result, there is no longer a delay in rising of the IV characteristic as shown in FIG. Although the resistance of the U-type conductivity modulation type MOSFET in the part B is low, there is no problem because the flat conductivity modulation type MOSFET in the part A which occupies most of the element area bears the resistance.
以上の説明は、Ｎチャネル伝導度変調型MOSFETについ
て行ったが、Ｐチャネル伝導度変調型MOSFETでも同様に
実施できる。Although the above description has been made with respect to the N-channel conductivity modulation type MOSFET, the same description can be applied to the P-channel conductivity modulation type MOSFET.
〔発明の効果〕 本発明によれば、一つの半導体基板内に平板型の伝導
度変調型MOSFETとＵ型の伝導度変調型MOSFETを併設する
ことにより、平板型の伝導度変調型MOSFETにおけるLFET
効果に基づくＩ−Ｖ特性の立ち上がりの遅れがＵ型の伝
導度変調型MOSFETの特性により補なわれるため、最初か
ら一様に立ち上がるＩ−Ｖ特性が得られる。従ってテレ
ビの水平偏向のように立ち上がりが問題になる用途にも
適する伝導度変調型MOSFETを得ることができる。[Effects of the Invention] According to the present invention, a planar conductivity modulation MOSFET and a U-type conductivity modulation MOSFET are provided side by side in one semiconductor substrate, so that an LFET in a flat conductivity modulation MOSFET is provided.
Since the delay of the rise of the IV characteristic based on the effect is compensated for by the characteristic of the U-type conductivity modulation type MOSFET, the IV characteristic which rises uniformly from the beginning can be obtained. Therefore, it is possible to obtain a conductivity modulation type MOSFET which is suitable for applications in which rising is a problem, such as horizontal deflection of a television.
第１図は本発明の一実施例の伝導度変調型MOSFETの断面
図、第２図は従来の平板型の伝導度変調型MOSFETの断面
図、第３図は平板型の伝導度変調型MOSFETの電流・電圧
特性線図、第４図はＵ型の伝導度変調型MOSFETの電流・
電圧特性線図である。 1:P+ドレイン層、2:N+バッファ層、3:N-ベース層、4:P
形のチャネル層、5:ゲート酸化膜、6:ゲート、7,71:N+
ソース層、11:U字状溝、12:ソース電極。FIG. 1 is a sectional view of a conductivity-modulated MOSFET according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional planar-conductivity-modulated MOSFET, and FIG. FIG. 4 shows the current and voltage characteristics of the U-type conductivity modulation type MOSFET.
FIG. 3 is a voltage characteristic diagram. 1: P + drain layer, 2: N + buffer layer, 3: N - base layer, 4: P
Channel layer, 5: gate oxide film, 6: gate, 7,71: N +
Source layer, 11: U-shaped groove, 12: source electrode.
Claims (1)
とが積層され、その第二層の表面部に選択的に第一導電
形の第一領域が、さらにその第一領域の表面部に選択的
に第二導電形の第二領域が形成され、第二層と第二領域
にはさまれた第一領域表面上に絶縁膜を介してゲートが
設けられ、第二領域表面および第二領域の第二層より遠
い側にある第一領域表面に一方の主電極が接触するもの
において、第一領域の表面部に選択的に第二導電形の第
三領域が形成され、第一領域の表面から第三領域に隣接
して第二層に達するＵ字状の溝が形成され、第二層と第
三領域にはさまれた第一領域の露出するＵ字状溝内側面
上に絶縁膜を介して補助ゲートが設けられ、第三領域お
よび第三領域の反Ｕ字状溝側にある第一領域表面に前記
一方の主電極が接触することを特徴とする伝導度変調型
MOSFET。A first layer of a first conductivity type and a second layer of a second conductivity type are laminated, and a first region of the first conductivity type is selectively formed on the surface of the second layer. A second region of the second conductivity type is selectively formed on the surface of the first region, and a gate is provided via an insulating film on the surface of the first region sandwiched between the second layer and the second region, In one in which one main electrode is in contact with the surface of the second region and the surface of the first region on the side farther than the second layer of the second region, the third region of the second conductivity type is selectively formed on the surface of the first region. Is formed, a U-shaped groove is formed from the surface of the first region to reach the second layer adjacent to the third region, and the exposed U of the first region sandwiched between the second layer and the third region is formed. An auxiliary gate is provided on the inner surface of the U-shaped groove via an insulating film, and the one main electrode is in contact with the third region and the surface of the first region on the side opposite to the U-shaped groove of the third region. Conductivity modulation type, characterized by
MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1134409A JP2611429B2 (en) | 1989-05-26 | 1989-05-26 | Conductivity modulation type MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1134409A JP2611429B2 (en) | 1989-05-26 | 1989-05-26 | Conductivity modulation type MOSFET |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02312281A JPH02312281A (en) | 1990-12-27 |
| JP2611429B2 true JP2611429B2 (en) | 1997-05-21 |
Family
ID=15127710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1134409A Expired - Lifetime JP2611429B2 (en) | 1989-05-26 | 1989-05-26 | Conductivity modulation type MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2611429B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3015679B2 (en) * | 1993-09-01 | 2000-03-06 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US6677641B2 (en) * | 2001-10-17 | 2004-01-13 | Fairchild Semiconductor Corporation | Semiconductor structure with improved smaller forward voltage loss and higher blocking capability |
| ITTO20120742A1 (en) * | 2012-08-24 | 2014-02-25 | St Microelectronics Srl | SEMICONDUCTOR DEVICE WITH IMPROVED LINEAR AND SWITCHING OPERATING MODES, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND METHOD OF POLARIZATION OF THE SEMICONDUCTOR DEVICE |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6237965A (en) * | 1985-08-13 | 1987-02-18 | Tdk Corp | Longitudinal semiconductor device and manufacture thereof |
| JPS63266882A (en) * | 1987-04-24 | 1988-11-02 | Hitachi Ltd | Vertical-type insulated-gate field-effect transistor |
-
1989
- 1989-05-26 JP JP1134409A patent/JP2611429B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02312281A (en) | 1990-12-27 |
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