JPH0418700B2 - - Google Patents

Info

Publication number
JPH0418700B2
JPH0418700B2 JP57226514A JP22651482A JPH0418700B2 JP H0418700 B2 JPH0418700 B2 JP H0418700B2 JP 57226514 A JP57226514 A JP 57226514A JP 22651482 A JP22651482 A JP 22651482A JP H0418700 B2 JPH0418700 B2 JP H0418700B2
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
melting point
high melting
conductor layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57226514A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59119742A (ja
Inventor
Ryoichi Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57226514A priority Critical patent/JPS59119742A/ja
Publication of JPS59119742A publication Critical patent/JPS59119742A/ja
Publication of JPH0418700B2 publication Critical patent/JPH0418700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP57226514A 1982-12-25 1982-12-25 半導体装置の製造方法 Granted JPS59119742A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226514A JPS59119742A (ja) 1982-12-25 1982-12-25 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226514A JPS59119742A (ja) 1982-12-25 1982-12-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59119742A JPS59119742A (ja) 1984-07-11
JPH0418700B2 true JPH0418700B2 (enrdf_load_stackoverflow) 1992-03-27

Family

ID=16846315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226514A Granted JPS59119742A (ja) 1982-12-25 1982-12-25 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59119742A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPS59119742A (ja) 1984-07-11

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