JPH0416994B2 - - Google Patents
Info
- Publication number
- JPH0416994B2 JPH0416994B2 JP57052500A JP5250082A JPH0416994B2 JP H0416994 B2 JPH0416994 B2 JP H0416994B2 JP 57052500 A JP57052500 A JP 57052500A JP 5250082 A JP5250082 A JP 5250082A JP H0416994 B2 JPH0416994 B2 JP H0416994B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- pulse
- output
- gain control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000926 separation method Methods 0.000 claims description 24
- 239000002131 composite material Substances 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 9
- 230000003111 delayed effect Effects 0.000 claims description 5
- 230000007257 malfunction Effects 0.000 claims description 5
- 230000001934 delay Effects 0.000 claims description 2
- 238000007493 shaping process Methods 0.000 claims description 2
- 239000000284 extract Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 230000008602 contraction Effects 0.000 description 5
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/52—Automatic gain control
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Receiver Circuits (AREA)
- Television Signal Processing For Recording (AREA)
Description
【発明の詳細な説明】
本発明は、磁気記録再生装置、テレビジヨン装
置などに使用される映像信号の自動利得制御装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control device for video signals used in magnetic recording and reproducing devices, television devices, and the like.
一般に、映像信号の自動利得制御装置は、複合
映像信号より取り出した映像信号の帰線消去部分
に一定のレベル値のパルスを挿入し、このパルス
の大きさと水平同期信号の大きさとの和を検出す
ることによつて複合映像信号の利得を制御してい
る。帰線消去部分に挿入するパルスは、複合映像
信号より同期分離回路によつて取り出した水平同
期信号を基準にして発生している。 Generally, an automatic gain control device for a video signal inserts a pulse of a certain level value into the blanking portion of the video signal extracted from the composite video signal, and detects the sum of the magnitude of this pulse and the magnitude of the horizontal synchronization signal. By doing this, the gain of the composite video signal is controlled. The pulses inserted into the blanking portion are generated based on the horizontal synchronization signal extracted from the composite video signal by the synchronization separation circuit.
したがつて、映像信号に雑音パルスが含まれて
いる場合やある期間連続して同期信号部分だけが
正規のレベルより小さくなる様な場合に同期分離
回路が誤動作して、その出力に水平同期信号以外
の余分なパルスが現われたりあるいはパルス幅が
異常に長くなつて正常なレベル検出が行なわれ
ず、その結果複合映像信号の利得が異常に抑え込
まてしまう様な不都合があつた。 Therefore, if the video signal contains noise pulses or if only the synchronization signal part becomes lower than the normal level for a certain period of time, the synchronization separation circuit will malfunction and the horizontal synchronization signal will be output. Inconveniences have arisen in that extra pulses appear or the pulse width becomes abnormally long, preventing normal level detection from being performed, and as a result, the gain of the composite video signal is abnormally suppressed.
第１図は従来の自動利得制御装置のブロツク図
を示すものである。図において、端子１に映像信
号等の入力信号が加えられ、利得制御回路２を通
つて出力端子３より取り出されると共に混合回路
４及び同期信号分離回路５に加えられる。 FIG. 1 shows a block diagram of a conventional automatic gain control device. In the figure, an input signal such as a video signal is applied to a terminal 1, passed through a gain control circuit 2, taken out from an output terminal 3, and applied to a mixing circuit 4 and a synchronizing signal separation circuit 5.
同期信号分離回路５の出力は遅延パルス発生回
路６に加えられ、水平同期信号より所定の位相遅
れ時間で所定レベル値のパルスを発生させて混合
回路４に加えられる。混合回路４では上記映像信
号の水平同期信号部分がクランプされた後、帰線
消去部分に上記所定レベル値のパルスが混合さ
れ、この出力が尖頭値検出回路７に加えられる。
尖頭検出回路７は印加される信号の尖頭値を検出
し、尖頭値の大きさに応じた例えば直流電圧がホ
ールド回路８を介して利得制御回路２に供給され
る。 The output of the synchronizing signal separation circuit 5 is applied to a delayed pulse generating circuit 6, which generates a pulse of a predetermined level value with a predetermined phase delay time from the horizontal synchronizing signal, and the pulse is applied to the mixing circuit 4. In the mixing circuit 4, after the horizontal synchronizing signal portion of the video signal is clamped, the pulse of the predetermined level value is mixed with the blanking portion, and this output is applied to the peak value detection circuit 7.
The peak detection circuit 7 detects the peak value of the applied signal, and a DC voltage, for example, corresponding to the magnitude of the peak value is supplied to the gain control circuit 2 via the hold circuit 8.
上記の様な構成の装置において、例えば第２図
Ａの如き複合映像信号が入力端子１に供給された
場合、同期信号分離回路５の出力に第２図Ｂの如
き信号が得られる。第２図Ｂに示すｃ，ｄはそれ
ぞれ第２図Ａに示す複合映像信号に含まれる雑音
パルスａ、同期信号の縮みｂによつて同期信号分
離回路５が誤動作した結果発生したパルスであ
る。このようなパルス信号ｃ，ｄが遅延パルス発
生回路６に加えられたとき、遅延パルス発生回路
６が同期信号分離回路５の出力を積分した後、波
形整形を行なう方式であれば、その出力として第
２図Ｃのような信号が得られ、この場合、雑音パ
ルスｃの様な幅の狭いパルスは除去できるが、同
期信号の縮みｂによつて発生した幅の広いパルス
ｄはそのままの巾のパルスとして出力に現われ
る。混合回路４は第２図ＡとＣに示した波形の信
号を混合するのでその出力は第２図Ｄに示す様に
なる。また遅延パルス発生回路６が同期信号分離
回路５の出力の立ち上り部分を検出して一定時間
遅らせて単安定マルチバイブレータを動作させる
方式であればその出力として第２図Ｅのような信
号が得られ、同期信号の縮みｂによつて発生した
幅の広いパルスｄに対しては位相は異なるものの
正規の幅のパルスを帰線消去部分の範囲内に発生
させることができるが、幅の狭い雑音パルスｃに
対しても一定幅のパルスが出力に現われる。その
結果混合回路４の出力は第２図Ｆに示す様にな
る。 In the apparatus configured as described above, when a composite video signal as shown in FIG. 2A is supplied to the input terminal 1, a signal as shown in FIG. 2B is obtained at the output of the synchronization signal separation circuit 5. C and d shown in FIG. 2B are pulses generated as a result of malfunction of the synchronization signal separation circuit 5 due to the noise pulse a and the contraction b of the synchronization signal contained in the composite video signal shown in FIG. 2A, respectively. When such pulse signals c and d are applied to the delayed pulse generation circuit 6, if the delay pulse generation circuit 6 integrates the output of the synchronization signal separation circuit 5 and then performs waveform shaping, the output will be A signal as shown in Figure 2C is obtained. In this case, narrow pulses such as noise pulse c can be removed, but the wide pulse d generated by the contraction b of the synchronization signal remains as it is. Appears on the output as a pulse. Since the mixing circuit 4 mixes the signals having the waveforms shown in FIG. 2A and C, its output becomes as shown in FIG. 2D. Furthermore, if the delay pulse generation circuit 6 detects the rising edge of the output of the synchronizing signal separation circuit 5 and delays it for a certain period of time to operate the monostable multivibrator, a signal as shown in FIG. 2 E can be obtained as its output. , it is possible to generate a pulse with a normal width within the range of the blanking part, although the phase is different from the wide pulse d generated by the contraction b of the synchronization signal, but a narrow noise pulse A pulse with a constant width also appears at the output for c. As a result, the output of the mixing circuit 4 becomes as shown in FIG. 2F.
第２図Ｄ，Ｆに示す信号が尖頭値検出回路７に
加えられると、正規の信号レベルV0より大きい
V1，V2を検出し利得制御回路２の利得を異常に
抑え込んでしまう。一般に尖頭値検出回路７と利
得制御回路２の間に接続されているホールド回路
８は充電時定数に比べて放電時定数が大きく設定
されているので一度V1あるいはV2を検出すると
元の状態に復帰するのに長時間を要し、その間端
子３に出力される映像信号レベルは正規のレベル
値より小さい状態が続いてしまうという欠点があ
つた。 When the signals shown in FIG. 2 D and F are applied to the peak value detection circuit 7, the signal level is greater than the normal signal level V 0 .
V 1 and V 2 are detected and the gain of the gain control circuit 2 is abnormally suppressed. Generally, the hold circuit 8 connected between the peak value detection circuit 7 and the gain control circuit 2 has a discharging time constant set larger than the charging time constant, so once V 1 or V 2 is detected, the original value is restored. There is a drawback that it takes a long time to return to the normal state, and during that time the video signal level output to the terminal 3 continues to be lower than the normal level value.
本発明は、このような欠点を除去するものであ
り、雑音、同期信号の縮みなどに対しても安定し
たAGC特性を得ることができる自動利得制御装
置を提供するものである。 The present invention eliminates these drawbacks and provides an automatic gain control device that can obtain stable AGC characteristics even against noise, synchronization signal compression, and the like.
以下本発明の一実施例を第３図、第４図を用い
て説明する。第３図は本発明の一実施例である自
動利得制御装置のブロツク図である。 An embodiment of the present invention will be described below with reference to FIGS. 3 and 4. FIG. 3 is a block diagram of an automatic gain control device which is an embodiment of the present invention.
第３図において端子１には映像信号等の入力信
号が加えられ、利得制御回路２を通つて出力端子
３より取り出されると共に混合回路４及び同期信
号分離回路５に加えられる。同期信号分離回路５
の出力は、パルス遅延回路９に加えられると共に
遅延回路を構成する単安定マルチバイブレータ１
０に加えられる。パルス遅延回路９は入力パルス
を積分して台形波あるいは三角波とした後波形整
形して遅延パルスを得る方式により遅延時間を帰
線消去部分のバツクポーチの幅より短くする様に
設定する（以上第４図Ｃを発生する方法）。単安
定マルチバイブレータ１０は、水平同期信号の前
縁でトリガされパルス幅は水平同期信号の幅より
2μsec以上長く帰線消去部分より短くなる程度に
設定する（以上第４図Ｄを発生する方法）。 In FIG. 3, an input signal such as a video signal is applied to a terminal 1, taken out from an output terminal 3 through a gain control circuit 2, and applied to a mixing circuit 4 and a synchronizing signal separation circuit 5. Synchronous signal separation circuit 5
The output of is applied to the pulse delay circuit 9 and monostable multivibrator 1 constituting the delay circuit.
Added to 0. The pulse delay circuit 9 integrates the input pulse to form a trapezoidal wave or a triangular wave, and then shapes the waveform to obtain a delayed pulse.The pulse delay circuit 9 sets the delay time to be shorter than the width of the back porch of the blanking portion (see the fourth example above). Figure C). The monostable multivibrator 10 is triggered by the leading edge of the horizontal sync signal, and the pulse width is less than the width of the horizontal sync signal.
Set it so that it is longer than the blanking part by 2 μsec or more (this is the method for generating D in Figure 4).
パルス遅延回路９の出力と単安定マルチバイブ
レータ１０の出力はこの２つの出力から基準パル
スを発生させるためにパルス発生回路を構成する
掛算器１１に加えられ、掛算器１１の出力すなわ
ち基準パルスは混合回路４で水平同期信号部分で
クランプされた上記映像信号の帰線消去部分に所
定レベル値で混合される。混合回路４の出力は尖
頭値検出回路７に加えられ、尖頭値の大きさに応
じた直流電圧がホールド回路８を介して利得制御
回路２に供給される。 The output of the pulse delay circuit 9 and the output of the monostable multivibrator 10 are applied to a multiplier 11 that constitutes a pulse generation circuit in order to generate a reference pulse from these two outputs, and the output of the multiplier 11, that is, the reference pulse is mixed. The circuit 4 mixes the blanking portion of the video signal clamped with the horizontal synchronizing signal portion at a predetermined level value. The output of the mixing circuit 4 is applied to the peak value detection circuit 7, and a DC voltage corresponding to the magnitude of the peak value is supplied to the gain control circuit 2 via the hold circuit 8.
次にこの装置において、第４図Ａの如き複合映
像信号が入力端子１に供給されて、同期信号分離
回路５の出力に第４図Ｂの如き信号が得られた場
合を考える。第４図Ｂに示すｃ，ｄはそれぞれ第
４図Ａに示す複合映像信号に含まれる雑音パルス
ａ、同期信号の縮みｂによつて同期信号分離回路
５が誤動作した結果発生したものである。このよ
うな信号がパルス遅延回路９に加えられたとき、
雑音パルスｃの様な幅の狭いパルスは除去されて
第４図Ｃの如き出力信号が得られる。また第４図
Ｂの如き信号が単安定マルチバイブレータ１０に
加えられたときパルスの幅とは無関係に第４図Ｄ
の如出力信号が得られる。したがつて第４図Ｃ，
Ｄの如き信号が掛算器１１の入力として加えられ
るのでその出力には第４図Ｅの如き信号が得ら
れ、混合回路４の出力すなわち尖頭値検出回路７
の入力には第４図Ｆの如き信号が現われ、正規の
信号レベルV0が検出されるので利得制御回路２
の利得は安定に保たれる。 Next, let us consider a case in which, in this apparatus, a composite video signal as shown in FIG. 4A is supplied to the input terminal 1, and a signal as shown in FIG. 4B is obtained at the output of the synchronizing signal separation circuit 5. Items c and d shown in FIG. 4B are generated as a result of the synchronization signal separation circuit 5 malfunctioning due to the noise pulse a and the contraction b of the synchronization signal contained in the composite video signal shown in FIG. 4A, respectively. When such a signal is applied to the pulse delay circuit 9,
Narrow pulses such as noise pulse c are removed to obtain an output signal as shown in FIG. 4C. Furthermore, when a signal as shown in FIG. 4B is applied to the monostable multivibrator 10, the signal shown in FIG. 4D is applied regardless of the pulse width.
An output signal like this is obtained. Therefore, Fig. 4C,
Since a signal such as D is added as an input to the multiplier 11, a signal as shown in FIG.
A signal as shown in FIG .
The gain of is kept stable.
このように本実施例では混合回路４に入力され
るパルス信号（第４図Ｅ）の後縁が、平常動作時
にはパルス遅延回路９の出力（第４図Ｃ）すなわ
ち同期信号分離回路５の出力（第４図Ｂ）の後縁
を所定の時間だけ遅らせた信号によつて決定さ
れ、第４図Ｂに示すｄの様な異常に幅の広いパル
スが現れた時には単安定マルチバイブレータ１０
の出力（第４図Ｄ）の後縁すなわち同期信号分離
回路５の出力（第４図Ｂ）の前縁を所定の時間だ
け遅らせた信号によつて決定されるので、前記混
合回路４に入力されるパルス信号の後縁は常に入
力された複合映像信号の水平ブランキング期間内
に制限される。したがつて映像信号部分に前記パ
ルス信号が混合されることがないので、出力され
る複合映像信号の利得が異常に抑え込まれること
を防止できる。また上述例においては、同期信号
分離回路５の入力を出力端子３から供給している
が、これを入力端子１から供給するようにしても
同様の効果が得られる。 In this way, in this embodiment, the trailing edge of the pulse signal input to the mixing circuit 4 (FIG. 4E) is the output of the pulse delay circuit 9 (FIG. 4C), that is, the output of the synchronizing signal separation circuit 5 during normal operation. (Fig. 4B) is determined by the signal whose trailing edge is delayed by a predetermined time, and when an abnormally wide pulse like d shown in Fig. 4B appears, the monostable multivibrator 10
The input signal to the mixing circuit 4 is determined by a signal obtained by delaying the trailing edge of the output (FIG. 4D), that is, the leading edge of the output of the synchronizing signal separation circuit 5 (FIG. 4B) by a predetermined time. The trailing edge of the pulse signal is always limited to the horizontal blanking period of the input composite video signal. Therefore, since the pulse signal is not mixed into the video signal portion, it is possible to prevent the gain of the output composite video signal from being abnormally suppressed. Further, in the above example, the input of the synchronizing signal separation circuit 5 is supplied from the output terminal 3, but the same effect can be obtained even if it is supplied from the input terminal 1.
以上のように本発明によれば、同期信号分離回
路がノイズパルスや同期信号の縮み等によつて誤
動作した時でも安定した利得制御動作が可能とな
る。 As described above, according to the present invention, stable gain control operation is possible even when the synchronization signal separation circuit malfunctions due to noise pulses, contraction of the synchronization signal, or the like.
第１図は従来の自動利得制御装置のブロツク
図、第２図は同装置の波形図、第３図は本発明の
一実施例である自動利得制御装置のブロツク図、
第４図は同装置の波形図である。
１……端子、２……利得制御回路、３……出力
端子、４……混合回路、５……同期信号分離回
路、６……遅延パルス発生回路、７……尖頭値検
出回路、８……ホールド回路、９……パルス遅延
回路、１０……単安定マルチバイブレータ、１１
……掛算器。
FIG. 1 is a block diagram of a conventional automatic gain control device, FIG. 2 is a waveform diagram of the same device, and FIG. 3 is a block diagram of an automatic gain control device that is an embodiment of the present invention.
FIG. 4 is a waveform diagram of the same device. DESCRIPTION OF SYMBOLS 1...Terminal, 2...Gain control circuit, 3...Output terminal, 4...Mixing circuit, 5...Synchronizing signal separation circuit, 6...Delay pulse generation circuit, 7...Peak value detection circuit, 8 ... Hold circuit, 9 ... Pulse delay circuit, 10 ... Monostable multivibrator, 11
...Multiplier.
Claims (1)
２と、上記複合映像信号より水平同期信号を取り
出す同期信号分離回路５と、上記同期信号分離回
路５の出力信号の前縁から所定の時間だけ遅らせ
た信号を発生する遅延回路１０と、上記同期信号
分離回路５の出力信号を積分した後、波形整形を
行なうことにより上記同期信号分離回路５の出力
信号の後縁を所定の時間だけ遅延した信号を発生
するパルス遅延回路９と、上記遅延回路１０の出
力と上記パルス遅延回路９の出力信号を用いて基
準パルスを発生するパルス発生回路１１と、上記
利得制御回路２の出力信号の一部に、上記出力信
号中の水平同期信号とは逆極性になるように上記
基準パルスを一定レベルで混合する混合回路４
と、この混合された上記基準パルスおよび上記利
得制御回路２の出力信号のうちいずれか信号レベ
ルが大きい方の信号の大きさと上記水平同期信号
の大きさとの和に応じて上記利得制御回路２の利
得を制御する尖頭値検出回路７を具備し、上記基
準パルスの後縁が、定常時には上記水平同期信号
の後縁から所定の遅延時間となる様に、また上記
同期信号分離回路５の誤動作によりその出力信号
の幅が上記複合映像信号に含まれる水平同期信号
の幅に比べて極端に広くなつた時には上記水平同
期信号の前縁から所定の期間以内に制限する様
に、さらに上記同期信号分離回路５の誤動作によ
りその出力信号の幅が上記複合映像信号に含まれ
る水平同期信号の幅に比べて極端に狭くなつた時
にはその幅の狭い信号を上記パルス遅延回路９の
積分により除去する様に構成して、上記尖頭値検
出回路７に異常に大きい信号が入力されるのを阻
止することを特徴とする自動利得制御装置。1 a gain control circuit 2 that controls the gain of the composite video signal; a sync signal separation circuit 5 that extracts a horizontal sync signal from the composite video signal; and a sync signal separation circuit 5 that delays the leading edge of the output signal of the sync signal separation circuit 5 by a predetermined time After integrating the output signals of the delay circuit 10 that generates a signal and the output signal of the synchronization signal separation circuit 5, waveform shaping is performed to generate a signal in which the trailing edge of the output signal of the synchronization signal separation circuit 5 is delayed by a predetermined time. a pulse delay circuit 9 that generates a reference pulse, a pulse generation circuit 11 that generates a reference pulse using the output of the delay circuit 10 and the output signal of the pulse delay circuit 9, and a part of the output signal of the gain control circuit 2. , a mixing circuit 4 that mixes the reference pulse at a constant level so that the polarity is opposite to that of the horizontal synchronization signal in the output signal;
and the output signal of the gain control circuit 2 according to the sum of the magnitude of the signal having a higher signal level among the mixed reference pulse and the output signal of the gain control circuit 2 and the magnitude of the horizontal synchronization signal. A peak value detection circuit 7 for controlling the gain is provided so that the trailing edge of the reference pulse has a predetermined delay time from the trailing edge of the horizontal synchronizing signal in a steady state, and a malfunction of the synchronizing signal separation circuit 5 is provided. When the width of the output signal becomes extremely wide compared to the width of the horizontal synchronization signal included in the composite video signal, the synchronization signal is further limited to within a predetermined period from the leading edge of the horizontal synchronization signal. When the width of the output signal becomes extremely narrow compared to the width of the horizontal synchronizing signal included in the composite video signal due to a malfunction of the separation circuit 5, the narrow signal is removed by the integration of the pulse delay circuit 9. An automatic gain control device configured to prevent an abnormally large signal from being input to the peak value detection circuit 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57052500A JPS58170177A (en) | 1982-03-30 | 1982-03-30 | Automatic gain controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57052500A JPS58170177A (en) | 1982-03-30 | 1982-03-30 | Automatic gain controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58170177A JPS58170177A (en) | 1983-10-06 |
| JPH0416994B2 true JPH0416994B2 (en) | 1992-03-25 |
Family
ID=12916439
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57052500A Granted JPS58170177A (en) | 1982-03-30 | 1982-03-30 | Automatic gain controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58170177A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0757021B2 (en) * | 1983-11-17 | 1995-06-14 | 松下電器産業株式会社 | Automatic gain control device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS517819A (en) * | 1974-07-08 | 1976-01-22 | Sony Corp | Agc kairo |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5829660Y2 (en) * | 1978-11-16 | 1983-06-29 | ソニー株式会社 | AGC circuit |
-
1982
- 1982-03-30 JP JP57052500A patent/JPS58170177A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS517819A (en) * | 1974-07-08 | 1976-01-22 | Sony Corp | Agc kairo |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58170177A (en) | 1983-10-06 |
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