JPS58170177A - Automatic gain controller - Google Patents

Automatic gain controller

Info

Publication number
JPS58170177A
JPS58170177A JP57052500A JP5250082A JPS58170177A JP S58170177 A JPS58170177 A JP S58170177A JP 57052500 A JP57052500 A JP 57052500A JP 5250082 A JP5250082 A JP 5250082A JP S58170177 A JPS58170177 A JP S58170177A
Authority
JP
Japan
Prior art keywords
signal
circuit
output
pulse
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57052500A
Other languages
Japanese (ja)
Other versions
JPH0416994B2 (en
Inventor
Yoshiyuki Yamamoto
義之 山本
Seiichi Hashimoto
清一 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57052500A priority Critical patent/JPS58170177A/en
Publication of JPS58170177A publication Critical patent/JPS58170177A/en
Publication of JPH0416994B2 publication Critical patent/JPH0416994B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/44Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/52Automatic gain control

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

PURPOSE:To assure the stable characteristics of an automatic gain controller even to the shrinkage of a noise and a synchronizing signal, by limiting the width of a horizontal synchronizing signal within a prescribed period from the front edge of said signal in case the width of the signal is extraordinarily increased so that the rear edge of the reference pulse lags by a prescribed time from the rear edge of the horizontal synchronizing signal in a normal state. CONSTITUTION:The composite video signals of the Fig. A are supplied, and the signals of the Fig. B are obtained at an output of a synchronizing signal separating circuit 5. In this case, signals (c) and (d) are generated by the malfunction of the circuit 5 which are due to a noise pulse (a) and the shrinkage (b) of a synchronizing signal. When such signals (c) and (d) are applied to a pulse delaying circuit 9, a pulse (c) of a narrow width is eliminated and the signals of the Fig. C are obtained. When the signals of the Fig. B are applied to a monostable multivibrator 10, an output of the Fig. D is obtained regardless of the pulse width. Therefore signals of the Figures C and D are applied to a multiplier 11, and the signals of the Fig. E are obtained at the output of the multiplier 11. Then the signal of the Fig. F emerge to the output of a mixing circuit 4, i.e., the input of a peak value detecting circuit 7. Thus the normal signal level V0 is detected to keep the stable gain of a gain control circuit 2.

Description

【発明の詳細な説明】 本発明は、磁気記録再生装置、テレビジョン装置などに
使用さ扛る映像信号の自動利得制御装置に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control device for video signals used in magnetic recording and reproducing devices, television devices, and the like.

一般に、映像信号の自動利得制御装置は、複合映像信号
より取り出した映像信号の帰線消去部分に一定(7)レ
ベル値のパルスヲ挿入し、このノ(ルスの大きさと水平
同期信号の大きさとの和を検出することによって複合映
像信号の利得を制御している。帰線消去部分に挿入する
パルスは、複合映像信号より同期分離回路によって取り
出した水平同期信号を基準にして発生している。
Generally, an automatic gain control device for a video signal inserts a pulse of a constant (7) level value into the blanking portion of the video signal extracted from the composite video signal, and then adjusts the magnitude of this pulse to the magnitude of the horizontal synchronizing signal. The gain of the composite video signal is controlled by detecting the sum.The pulses inserted into the blanking portion are generated based on the horizontal synchronization signal extracted from the composite video signal by the synchronization separation circuit.

したがって、映像信号に雑音)(ルスが含まnている場
合やある期間連続して同期信号部分だけが正規のレベル
より小さくなる様な場合に同期分離回路が誤動作して、
その出力に水平同期信号以外の余分なパルスが現わ扛た
すあるいはパルス幅が異常に長くなって正常なレベル検
出が行なわ扛ず、その結果複合映像信号の利得が異常に
抑え込まnてしまう様な不都付があった。
Therefore, if the video signal contains noise (noise) or if only the synchronization signal part becomes lower than the normal level for a certain period of time, the synchronization separation circuit will malfunction.
If an extra pulse other than the horizontal synchronization signal appears in the output, or the pulse width becomes abnormally long, normal level detection is not performed, and as a result, the gain of the composite video signal is abnormally suppressed. There were various inconveniences.

第1図は従来の自動利得制(財)装置のブロック図を示
すものである。図において、端子1に映像信号等の入力
信号が加えらn1利得制御回路2を通って出力端子3よ
り取り出さ孔ると共に混合回路4及び同期信号分離回路
5に加えらnる〇同期信号分離回路6の出力は遅延パル
ス発生回路6に加えらn1水平同期信号より所定の位相
遅n時間で所定レベル値のパルスを発生させて混合回路
4に加えらfる。混合回路4では上記映像信号の水平同
期信号部分がクランプさnた後、帰線消1      
去部分に上記所定レベル値のパルスが混合さnlこの出
力が尖頭値検出回路7に加えらnる。尖頭値検出回路7
は印加さnる信号の尖頭値を検出し、尖頭値の大きさに
応じた例えば直流電圧がポ゛−ルド回路8を介して利得
制御回路2に供給さ扛る。
FIG. 1 shows a block diagram of a conventional automatic profit system (wealth) system. In the figure, an input signal such as a video signal is applied to a terminal 1, passes through a gain control circuit 2, is taken out from an output terminal 3, and is also applied to a mixing circuit 4 and a sync signal separation circuit 5. The output of 6 is applied to the delayed pulse generation circuit 6, which generates a pulse of a predetermined level value with a predetermined phase delay n time from the horizontal synchronizing signal n1, and is applied to the mixing circuit 4. In the mixing circuit 4, after the horizontal synchronizing signal part of the video signal is clamped, blanking circuit 1
The pulse of the predetermined level value mentioned above is mixed with the output portion of the signal, and this output is applied to the peak value detection circuit 7. Peak value detection circuit 7
detects the peak value of the applied signal, and supplies, for example, a DC voltage to the gain control circuit 2 via the field circuit 8 in accordance with the magnitude of the peak value.

上記の様な構成の装置において、例えば第2図ムの如き
複合映像信号が入力端子1に供給さf′1.た場合、同
期信号分離回路6の出力に第2図Bの如き信号が得らn
る。第2図Bに示すc、  dはそ扛ぞn第2図ムに示
す複合映像信号に含まnる雑音パルスa、同期信号の縮
みbによって同期信号分離回路6が誤動作した結果発生
したパルスである。
In the apparatus configured as described above, a composite video signal as shown in FIG. 2, for example, is supplied to the input terminal 1 f'1. In this case, a signal as shown in FIG. 2B is obtained at the output of the synchronizing signal separation circuit 6.
Ru. C and d shown in Figure 2B are pulses generated as a result of malfunction of the synchronization signal separation circuit 6 due to the noise pulse a and the compression of the synchronization signal b contained in the composite video signal shown in Figure 2B. be.

このようなパルス信号C9dが遅延パルス発生回路6に
加えらr′したとき、遅延パルス発生回路らが同期信号
分離回路6の出力を積分した後、波形整形を行なう方式
であ扛ば、その出力として第2図Cのような信号が得ら
扛、この場合、雑音パルスCの様な幅の狭いパルスは除
去できるが、同期信号の縮みbによって発生した幅の広
いパルスdはそのままの巾のパルスとして出力に現わ扛
る。混合回路4は第2図ムとCに示した波形の信号を混
合するのでその出力は第2図りに示す様になる。
When such a pulse signal C9d is applied to the delayed pulse generation circuit 6, if the delayed pulse generation circuits integrate the output of the synchronizing signal separation circuit 6 and then perform waveform shaping, the output In this case, a narrow pulse like the noise pulse C can be removed, but the wide pulse d generated by the contraction b of the synchronization signal remains as it is. Appears in the output as a pulse. Since the mixing circuit 4 mixes the signals having the waveforms shown in FIG. 2 and C, the output thereof is as shown in the second diagram.

また遅延パルス発生回路eが同期信号分離回路6の出力
の立ち上り部分を検出して一定時間遅らせて単安定マル
チバイブレータを動作させる方式であnばその出力とし
て第2図Rのような信号が得ら扛、同期信号の縮みbに
よって発生した幅の広いパルスdに対しては位相は異な
るものの正規の幅のパルスを帰線消去部分の範囲内に発
生させることができるが、幅の狭い雑音パルスCに対し
ても一定幅のパルスが出力に現わ扛る。その結果混合回
路4の出力は第2図Fに示す様になる。
If the delay pulse generation circuit e detects the rising edge of the output of the synchronizing signal separation circuit 6 and delays it for a certain period of time to operate the monostable multivibrator, then a signal as shown in FIG. 2 R is obtained as its output. Although the phase is different from the wide pulse d generated by the contraction of the synchronization signal b, a normal width pulse can be generated within the range of the blanking part, but a narrow noise pulse A pulse with a constant width also appears in the output for C. As a result, the output of the mixing circuit 4 becomes as shown in FIG. 2F.

第2図り、  Fに示す信号が尖頭値検出回路7に加え
ら扛ると、正規の信号レベルvoより大きいvl。
In the second diagram, when the signal shown at F is applied to the peak value detection circuit 7, the signal level vl is higher than the normal signal level vo.

v2を検出し利得制御回路2の利得を異常に抑え込んで
し1つ。一般に尖頭値検出回路7と利得制御回路2の間
に接続さ扛ているホールド回路8は充電時定数に比べて
放電時定数が犬さく設定さ扛ているので一度v1あるい
はv2を検出すると元の状態に復帰するのに長時間を要
し、その間端子3に出力さnる映像信号レベルは正規の
レベル値より小さい状態が続いてし1つという欠点があ
った。
v2 was detected and the gain of gain control circuit 2 was abnormally suppressed. In general, the hold circuit 8 connected between the peak value detection circuit 7 and the gain control circuit 2 has a discharging time constant set to be much smaller than the charging time constant, so once v1 or v2 is detected, the It takes a long time to return to the above state, and during this time the video signal level output to the terminal 3 continues to be lower than the normal level value.

不発明は、このような欠点を除去するものであり、雑音
、同期信号の縮みなどに対しても安定したムGC特性を
得ることができる自動利得制(ホ)装置を提供するもの
である。
The object of the present invention is to eliminate such drawbacks and provide an automatic gain control device that can obtain stable GC characteristics even against noise, synchronization signal compression, and the like.

以下本発明の一実施例を第3図1第4図を用いて説明す
る。第3図服本発明の一実施例である自動利得制御装置
のブロック図である。
An embodiment of the present invention will be described below with reference to FIG. 3 and FIG. 4. FIG. 3 is a block diagram of an automatic gain control device which is an embodiment of the present invention.

第3図において端子1には映像信号等の入力信号が加え
らn1利得制御回路2を通って出力端子3よジ取9出さ
nると共に混合回路4及び同期信号分離回路6に加えら
扛る。同期信号分離回路6の出力は、パルス遅延回路9
に加えら扛ると共に単安定マルチバイブレータ1oに加
えらnる。パルス遅延回路9は入力パルスを積分して台
形波あるいは三角波とした後波形整形して遅延パルスを
得る方式により遅延時間を帰線消去部分のバンクポーチ
の幅より短くする様に設定する。単安定マルチバイブレ
ータ10は、水平同期信号の前縁でトリガさnパルス幅
は水平同期信号の幅より2μ要以上長く帰線消去部分よ
り短くなる程度に設定する0 パルス遅延回路9の出力と単安定マルチパイプレ−タ1
0の出力は掛算器11に加えら扛、掛算器11の出力す
なわち基準パルスは混合回路4で水平同期信号部分でク
ランプさnた上記映像信号の帰線消去部分に所定レベル
値で混合さnる。混合回路4の出力は尖頭値検出回路7
に加えらn1尖頭値の大きさに応じfC直流電圧がホー
ルド回路8を介して利得制御回路2に供給さnる。
In FIG. 3, an input signal such as a video signal is applied to a terminal 1, passes through a gain control circuit 2, is output from an output terminal 3, and is also applied to a mixing circuit 4 and a synchronizing signal separation circuit 6. . The output of the synchronization signal separation circuit 6 is sent to the pulse delay circuit 9.
is added to the monostable multivibrator 1o. The pulse delay circuit 9 integrates the input pulse to form a trapezoidal wave or a triangular wave, and then shapes the waveform to obtain a delayed pulse.The pulse delay circuit 9 sets the delay time to be shorter than the width of the bank pouch in the blanking portion. The monostable multivibrator 10 is triggered at the leading edge of the horizontal synchronizing signal, and the pulse width is set to be at least 2μ longer than the width of the horizontal synchronizing signal and shorter than the blanking part. Stable multi piperator 1
The output of 0 is applied to the multiplier 11, and the output of the multiplier 11, that is, the reference pulse, is mixed at a predetermined level with the blanking portion of the video signal clamped by the horizontal synchronizing signal portion in the mixing circuit 4. Ru. The output of the mixing circuit 4 is sent to the peak value detection circuit 7
In addition to n1, a DC voltage fC is supplied to the gain control circuit 2 via the hold circuit 8 according to the magnitude of the peak value n1.

次にこの装置において、第4図ムの如き複合映像信号が
入力端子1に供給さtて、同期信号分離回路6の出力に
第4図Bの如き信号が得ら扛た場合を考える。第4図B
に示すc、  dはそ扛ぞ扛第4[凶ムに示す複合映像
信号に含ま【る雑音パルスa、同期信号の縮みbによっ
て同期信号分離回路6が誤動作した結果発生したもので
ある。このような信号がパルス遅延回路9に加えらnJ
Cとき、雑音パルスCの様な幅の狭いキ(ルスは除去さ
れて1    第4図Cの如き出力信号が得らnる。ま
た第4図Bの如き信号が単安定マルチバイブレータ10
に加えら2″I−タときパルスの幅とは無関係に第4図
りの如き出力信号が得ら扛る。したがって第4図C2D
の如き信号が掛算器11の入力として加えら扛るのでそ
の出力には第4図Eの如き信号が得ら扛、混合回路4の
出力すなわち尖−頭領検出回路7の入力には第4図Fの
如き信号が現われ、正規の信号レベルvoが検出さnる
ので利得制御回路2の利得は安定に保た扛る。− このように本実施例では混合回路4に入力さ扛るパルス
信号(第4図E)の後縁が、平常動作時にはパルス遅延
回路9の出力(第4図C)すなわち同期信号分離回路6
の出力(第4図B)の後縁を所定の時間だけ遅らせた信
号によって決定さ【、第4図Bに示すdの様な異常に幅
の広いパルスが現nた時には単安定マルチバイブレータ
10(7)出力(第4図D)の後縁すなわち同期信号分
離回路5の出力(第4図B)の前縁を所定の時間だけ遅
らせた信号によって決定さ扛るので、パルス遅延回路9
の遅延時間及び単安定マルチバイブレータ10の出力パ
ルス幅は共に比較的バラツキが大きくても、正常な動作
が可能となる。
Next, consider a case in which a composite video signal as shown in FIG. 4B is supplied to the input terminal 1 of this apparatus, and a signal as shown in FIG. Figure 4B
C and d shown in FIG. 4 are generated as a result of the synchronization signal separation circuit 6 malfunctioning due to noise pulses a and compression of the synchronization signal b included in the composite video signal shown in FIG. When such a signal is applied to the pulse delay circuit 9, nJ
When C, a narrow pulse like the noise pulse C is removed and an output signal as shown in FIG. 4C is obtained.Also, a signal as shown in FIG.
In addition to 2" I-ta, an output signal as shown in Figure 4 is obtained regardless of the width of the pulse. Therefore, Figure 4 C2D
Since a signal such as shown in FIG. 4 is applied as an input to the multiplier 11, a signal as shown in FIG. Since a signal such as F appears and a normal signal level vo is detected, the gain of the gain control circuit 2 is kept stable. - In this way, in this embodiment, the trailing edge of the pulse signal input to the mixing circuit 4 (FIG. 4E) is the output of the pulse delay circuit 9 (FIG. 4C), that is, the synchronizing signal separation circuit 6 during normal operation.
The output of the monostable multivibrator 10 is determined by a signal whose trailing edge (FIG. 4B) is delayed by a predetermined time. (7) Since the trailing edge of the output (FIG. 4D), that is, the leading edge of the output (FIG. 4B) of the synchronizing signal separation circuit 5, is determined by a signal delayed by a predetermined time, the pulse delay circuit 9
Normal operation is possible even if both the delay time and the output pulse width of the monostable multivibrator 10 have relatively large variations.

なお本実施例においては、単安定マルチバイブレータ1
0と掛算器11で基準パルスの幅を制限するようにした
が、こ扛の代わりに水平同期信号の前縁から所定の遅し
時間でパルスを発生させて、そのパルスの前縁でパルス
遅延回路9の出力をリセットするようにしても同様の効
果が得ら扛る。
In this example, monostable multivibrator 1
The width of the reference pulse is limited by 0 and the multiplier 11, but instead of this, a pulse is generated at a predetermined delay time from the leading edge of the horizontal synchronizing signal, and the pulse delay circuit is activated at the leading edge of the pulse. Even if the output of 9 is reset, the same effect cannot be obtained.

fた上述例においては、同期信号分離回路6の入力を出
力端子3から供給しているが、こn1r、入力端子1か
ら供給するようにしても同様の効果が得らnる。
In the above example, the input of the synchronizing signal separation circuit 6 is supplied from the output terminal 3, but the same effect can be obtained even if the input is supplied from the input terminal 1.

以上のように本発明によnば、同期信号分離回路がノイ
ズパルスや同期信号の縮み等によって誤動作した時でも
安定した利得制御動作が可能となる。
As described above, according to the present invention, stable gain control operation is possible even when the synchronization signal separation circuit malfunctions due to noise pulses, contraction of the synchronization signal, or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の自動利得制呻装誼のブロック図、第2図
は同装置の波形図、第3図は本発明の一実施例である自
動利得側(財)装置のブロック図、第4図は同装置の波
形図である。 1・・・・・・端子、2・・・・・・利得制御回路、3
・・・・・・出力端子、4・・・・・・混合回路、6・
・・・・・同期信号分離回路、6・・・・・・遅延パル
ス発生回路、7・・・・・・尖頭値検出回路、8・・・
・・・ホールド回路、9・・・・・・パルス遅延回路、
10・・・・・・単安定マルチバイブレータ、11・・
・・・・掛算器。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第 
Ill @3wA II 4 図 特許庁長官殿 l事件の表示 昭和57年特許願第 62500  シJ゛2発明の名
称 自動利得制御装置 3補正をする者 ]I・(;、こ5)巽・、      特  許  出
  願  人(L+・1  大阪府門真市大字門真10
06番地名 41H・ (582)松下電器産業株式会
社代表賃      山   下   俊   彦4代
理人 〒571 住 j;1   大阪府門真市大字門真1006番地〔
連イ3先屯活(虫刺437−1 t21持許分室〕! 6補正の対象
FIG. 1 is a block diagram of a conventional automatic gain control system, FIG. 2 is a waveform diagram of the same device, and FIG. 3 is a block diagram of an automatic gain control device that is an embodiment of the present invention. Figure 4 is a waveform diagram of the same device. 1...terminal, 2...gain control circuit, 3
...Output terminal, 4...Mixing circuit, 6.
... Synchronization signal separation circuit, 6 ... Delay pulse generation circuit, 7 ... Peak value detection circuit, 8 ...
...Hold circuit, 9...Pulse delay circuit,
10... Monostable multivibrator, 11...
...Multiplier. Name of agent: Patent attorney Toshio Nakao and 1 other person
Ill @3wA II 4 Figure Director General of the Patent Office l Case Display Patent Application No. 62500 of 1982 Applicant (L+・1 10 Oaza Kadoma, Kadoma City, Osaka Prefecture)
06 Address Name 41H (582) Matsushita Electric Industrial Co., Ltd. Representative Toshihiko Yamashita 4 Agent 571 Address: 1 1006 Kadoma, Kadoma City, Osaka Prefecture
3 consecutive active duty (Mushibite 437-1 t21 holding branch)! Subject to 6 corrections

Claims (1)

【特許請求の範囲】[Claims] 複合映像信号の利得を制御する利得制御回路と、上記複
合映像信号より水平同期信号を取り出す同期分離回路と
、上記水平同期信号の前縁から所定の時間だけ遅らせた
信号を発生する遅延回路と、上記水平同期信号の後縁を
所定の時間だけ遅延した信号を発生する遅延パルス発生
回路と、上記遅延回路の出力と上記遅延パルス発生回路
の出力を用いて基準パルスを発生するパルス発生回路と
、上記利得制御回路の出力信号の一部に、上記出力信号
中の水平同期信号とは逆極性になるように上記基準パル
スを一定レベルで混合する混合回路と、この混合さnた
上記基準パルスおよび上記出力信号のうちいず匙か大き
い方の信号の大きさと上記水平同期信号の大きさとの和
に応じて上記利得側(財)回路の利得を制御する尖頭値
検出回路を具備し、上記基準パルスの後縁が、定常時に
は上記水平同期信号の後縁から所定の遅延時間となる様
に、上記水平同期信号の幅が異常に広くなった時には上
記水平同期信号の前縁から所定の期間以内に制限する様
にして、上記尖頭値検出回路に異常に大きい信号が入力
さnるのを阻止する様に構成したことを特徴とする自動
利得制御装置。
a gain control circuit that controls the gain of the composite video signal; a synchronization separation circuit that extracts a horizontal synchronization signal from the composite video signal; and a delay circuit that generates a signal delayed by a predetermined time from the leading edge of the horizontal synchronization signal; a delay pulse generation circuit that generates a signal in which the trailing edge of the horizontal synchronization signal is delayed by a predetermined time; a pulse generation circuit that generates a reference pulse using the output of the delay circuit and the output of the delay pulse generation circuit; a mixing circuit that mixes the reference pulse at a certain level into a part of the output signal of the gain control circuit so that the polarity is opposite to that of the horizontal synchronization signal in the output signal; a peak value detection circuit for controlling the gain of the gain side circuit according to the sum of the magnitude of the larger one of the output signals and the magnitude of the horizontal synchronization signal; The trailing edge of the reference pulse is a predetermined delay time from the trailing edge of the horizontal synchronizing signal during normal conditions, and a predetermined delay time from the leading edge of the horizontal synchronizing signal when the width of the horizontal synchronizing signal becomes abnormally wide. An automatic gain control device characterized in that the automatic gain control device is configured to prevent an abnormally large signal from being input to the peak value detection circuit.
JP57052500A 1982-03-30 1982-03-30 Automatic gain controller Granted JPS58170177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57052500A JPS58170177A (en) 1982-03-30 1982-03-30 Automatic gain controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57052500A JPS58170177A (en) 1982-03-30 1982-03-30 Automatic gain controller

Publications (2)

Publication Number Publication Date
JPS58170177A true JPS58170177A (en) 1983-10-06
JPH0416994B2 JPH0416994B2 (en) 1992-03-25

Family

ID=12916439

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57052500A Granted JPS58170177A (en) 1982-03-30 1982-03-30 Automatic gain controller

Country Status (1)

Country Link
JP (1) JPS58170177A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109387A (en) * 1983-11-17 1985-06-14 Matsushita Electric Ind Co Ltd Automatic gain controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517819A (en) * 1974-07-08 1976-01-22 Sony Corp Agc kairo
JPS5574169U (en) * 1978-11-16 1980-05-22

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS517819A (en) * 1974-07-08 1976-01-22 Sony Corp Agc kairo
JPS5574169U (en) * 1978-11-16 1980-05-22

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60109387A (en) * 1983-11-17 1985-06-14 Matsushita Electric Ind Co Ltd Automatic gain controller

Also Published As

Publication number Publication date
JPH0416994B2 (en) 1992-03-25

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