JPH04162678A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04162678A JPH04162678A JP29026190A JP29026190A JPH04162678A JP H04162678 A JPH04162678 A JP H04162678A JP 29026190 A JP29026190 A JP 29026190A JP 29026190 A JP29026190 A JP 29026190A JP H04162678 A JPH04162678 A JP H04162678A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- gate
- field oxide
- gate oxide
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000006378 damage Effects 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
庄1」]l止肚分厨−
この発明は、半導体装置の製造方法に関し、特に高耐圧
MO5ICの高圧Pチャンネルトランジスタのゲート酸
化膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a gate oxide film of a high voltage P-channel transistor of a high breakdown voltage MO5IC.
従来叫改斂
表示デイスプレィのドライバ等に用いられている、高耐
圧MO5IGの出力Pチャンネルトランジスタの構造を
、第3図に示す。FIG. 3 shows the structure of an output P-channel transistor of a high-voltage MO5IG, which is used as a driver for a conventional high-voltage display.
第3図において、1はソース電極、2はゲートのポリシ
リコン、3はドレイン電極、4は層間膜のPSG、5は
フィールド酸化膜、6はゲート酸化膜、7はフィールド
酸化膜とゲート酸化膜の接合部である。In FIG. 3, 1 is a source electrode, 2 is a gate polysilicon, 3 is a drain electrode, 4 is an interlayer film PSG, 5 is a field oxide film, 6 is a gate oxide film, and 7 is a field oxide film and a gate oxide film. It is the joint of
ゲートのポリシリコン2にマイナスの高電圧が加わると
、ゲート酸化膜6の下にP形の反転層が形成され、ソー
ス電極1とドレイン電極3の間に電流を流すことができ
る。When a high negative voltage is applied to the gate polysilicon 2, a P-type inversion layer is formed under the gate oxide film 6, allowing current to flow between the source electrode 1 and the drain electrode 3.
■の −
ところで、上記のトランジスタは、第4図(B)でフィ
ールド酸化膜5を形成し、その後第4図(C)でゲート
酸化膜6を形成している。(2) By the way, in the above transistor, the field oxide film 5 is formed in FIG. 4(B), and then the gate oxide film 6 is formed in FIG. 4(C).
そのため、フィールド酸化膜5とゲート酸化膜6の境界
部7で酸素の供給不足や重金属、ゴミなどにより、酸化
膜質が劣化し、ゲートに高電圧がかかった際に、境界部
の破壊や、ゲートとソース、ドレイン間でリーク電流を
発生するという欠点があった。Therefore, the quality of the oxide film deteriorates at the boundary part 7 between the field oxide film 5 and the gate oxide film 6 due to insufficient supply of oxygen, heavy metals, dust, etc., and when a high voltage is applied to the gate, the boundary part may be destroyed or the gate oxide film 6 may be damaged. This has the drawback of generating leakage current between the source and drain.
、の
この発明は、上記の課題を解決するために、フィールド
酸化膜とゲート酸化膜を同時に形成する工程と、ゲート
部分の酸化膜を所定厚さだけ残して除去する工程とを含
むことを特徴とするものである。In order to solve the above-mentioned problem, this invention is characterized by including a step of simultaneously forming a field oxide film and a gate oxide film, and a step of removing the oxide film in the gate portion leaving only a predetermined thickness. That is.
1且
上記の製造方法により、フィールド酸化膜とゲート酸化
膜の境界部の酸化膜質の劣化がなくなるため、ゲートと
ソース、ドレイン間の耐圧が向上し、ゲート酸化膜の破
壊や、ゲートとソース、ドレイン間でのリーク電流の発
生も防止できる。1. The above manufacturing method eliminates deterioration of the oxide film quality at the boundary between the field oxide film and the gate oxide film, improving the withstand voltage between the gate, source, and drain, preventing destruction of the gate oxide film, and preventing damage to the gate, source, and drain. It is also possible to prevent leakage current from occurring between the drains.
災胤阻
以下、この発明の実施例について、図面を参照して説明
する。Embodiments of the present invention will now be described with reference to the drawings.
第1図は、この発明の実施例のフィールド酸化膜とゲー
ト酸化膜を同時に形成した高圧Pチャンネルトランジス
タの断面図を示す。各部の名称及び動作原理は、前述の
第3図と同様であるので、説明を省略する。FIG. 1 shows a cross-sectional view of a high voltage P-channel transistor in which a field oxide film and a gate oxide film are simultaneously formed according to an embodiment of the present invention. The names and operating principles of each part are the same as those shown in FIG. 3 above, so explanations will be omitted.
第2図(A)〜(E)は、このトランジスタの製造フロ
ーに従う断面図を示す。FIGS. 2(A) to 2(E) show cross-sectional views according to the manufacturing flow of this transistor.
第2図(B)で全面に厚さ1.8um程度のフィールド
酸化膜を形成し、第2図(C)でゲート部分の酸化膜を
エッチすることにより例えば、厚さ4000〜6000
人のゲート酸化膜6を形成する。By forming a field oxide film with a thickness of about 1.8 um on the entire surface as shown in FIG. 2(B), and etching the oxide film on the gate part in FIG.
A human gate oxide film 6 is formed.
、 この方法は、フィールド酸化膜5とゲート酸化膜6
の境界部の酸化膜質の劣化がなくなるため、境界部での
ゲート酸化膜の破壊や、ゲートとソース、ドレイン間の
リーク電流の発生を防ぐという利点がある。, This method consists of a field oxide film 5 and a gate oxide film 6.
This eliminates deterioration of the oxide film quality at the boundary, which has the advantage of preventing damage to the gate oxide film at the boundary and leakage current between the gate, source, and drain.
主肌二処敦
この発明は、以上のように、フィールド酸化膜とゲート
酸化膜を同時に形成することにより、フィールド酸化膜
とゲート酸化膜の境界部をなくし、ゲート酸化膜の破壊
やゲートとソース、ドレイン間のリーク電流の発生を防
止する効果がある。As described above, this invention eliminates the boundary between the field oxide film and the gate oxide film by forming the field oxide film and the gate oxide film at the same time. This has the effect of preventing leakage current between the drains.
第1図は、この発明のフィールド酸化膜とゲート酸化膜
を同時に形成した高圧Pチャンネルトランジスタの断面
図である。
第2図(A)〜(E)は、この発明のフィールド酸化膜
とゲート酸化膜を同時に形成した高圧Pチャンネルトラ
ンジスタの製造フローに従う断面図である。
第3図は、従来のフィールド酸化膜とゲート酸化膜を別
々に形成した高圧Pチャンネルトランジスタの断面図で
ある。
第4図(A)〜(E)は、従来のフィールド酸化膜とゲ
ート酸化膜を別々の工程で形成した高圧Pチャンネルト
ランジスタの製造フローに従う断面図である。
1・・・・・・ソース電極、
2・・・・・・ゲートのポリシリコン、3・・・・・・
ドレイン電極、
4・・・・・・層間膜のPSGl
5・・・・・・フィールド酸化膜、
6・・・・・・ゲート酸化膜、
7・・・・・・フィールド酸化膜と
ゲート酸化膜の接合部。
112図FIG. 1 is a cross-sectional view of a high voltage P-channel transistor in which a field oxide film and a gate oxide film are simultaneously formed according to the present invention. FIGS. 2A to 2E are cross-sectional views showing a manufacturing flow of a high-voltage P-channel transistor in which a field oxide film and a gate oxide film are simultaneously formed according to the present invention. FIG. 3 is a cross-sectional view of a conventional high voltage P-channel transistor in which a field oxide film and a gate oxide film are formed separately. FIGS. 4A to 4E are cross-sectional views showing the manufacturing flow of a conventional high-voltage P-channel transistor in which a field oxide film and a gate oxide film are formed in separate steps. 1... Source electrode, 2... Gate polysilicon, 3...
Drain electrode, 4... PSGl of interlayer film 5... Field oxide film, 6... Gate oxide film, 7... Field oxide film and gate oxide film joint of. Figure 112
Claims (1)
いて、 フィールド酸化膜とゲート酸化膜を同時に形成する工程
と、ゲート部分の酸化膜を所定厚さだけ残して除去する
工程とを含むことを特徴とする半導体装置の製造方法。[Claims] A high-voltage P-channel transistor of a high-voltage MOSIC includes a step of simultaneously forming a field oxide film and a gate oxide film, and a step of removing the oxide film at the gate portion leaving only a predetermined thickness. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29026190A JPH04162678A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29026190A JPH04162678A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04162678A true JPH04162678A (en) | 1992-06-08 |
Family
ID=17753848
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29026190A Pending JPH04162678A (en) | 1990-10-25 | 1990-10-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04162678A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005079208A (en) * | 2003-08-28 | 2005-03-24 | Nec Electronics Corp | Mis type semiconductor device and its manufacturing method |
US7217612B2 (en) | 2000-12-07 | 2007-05-15 | Sanyo Electric Co., Ltd. | Manufacturing method for a semiconductor device with reduced local current |
-
1990
- 1990-10-25 JP JP29026190A patent/JPH04162678A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7217612B2 (en) | 2000-12-07 | 2007-05-15 | Sanyo Electric Co., Ltd. | Manufacturing method for a semiconductor device with reduced local current |
JP2005079208A (en) * | 2003-08-28 | 2005-03-24 | Nec Electronics Corp | Mis type semiconductor device and its manufacturing method |
US7750402B2 (en) | 2003-08-28 | 2010-07-06 | Nec Electronics Corporation | Lateral planar type power semiconductor device including drain buried region immediately below drain region and its manufacturing method |
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