JPH04162438A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH04162438A
JPH04162438A JP2286173A JP28617390A JPH04162438A JP H04162438 A JPH04162438 A JP H04162438A JP 2286173 A JP2286173 A JP 2286173A JP 28617390 A JP28617390 A JP 28617390A JP H04162438 A JPH04162438 A JP H04162438A
Authority
JP
Japan
Prior art keywords
aluminum
film
silicon nitride
nitride film
pads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2286173A
Other languages
English (en)
Inventor
Ryutaro Mera
米良　竜太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP2286173A priority Critical patent/JPH04162438A/ja
Publication of JPH04162438A publication Critical patent/JPH04162438A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に樹脂封止型半導体装置
に関する。
〔従来の技術〕
従来、樹脂封止型半導体装置は製造工程に於いて、半導
体電気回路に接続するアルミ配線を形成後、パッシベー
ション膜であるシリコン窒化膜をプラズマ成長させ、露
光・エツチンク技術によってアルミパッド部のみのこの
シリコン窒化膜を除去しアルミパッドを形成していた。
その際、使用する露光用マスクは多種のグー１へ組合せ
やパッケージの組合せに対し、共通化している為、その
半導体装置に必要とされるアルミパッド数ではなく、最
大数のアルミパッドを有する構造となっていた。故に、
その装置に不必要なアルミパッドがパッシベーション膜
におおわれない状態で存在していた。
〔発明が解決しようとする課題〕
上述した従来の半導体装置は、不必要なアルミパッドま
でが露出した状態であるため、樹脂封止後浸透した水分
の影響てボンディングワイヤに接続されないアルミパッ
ドの腐食がすすみ、故障の原因となるという品質上の欠
点があった。
〔課題を解決するための手段〕
本発明の半導体装置は、アルミ配線と一体的に形成され
たアルミバットを有する半導体装置において、前記アル
ミパッドは全てホンティングワイヤと接続されているも
のである。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は本発明の一実施例の断面図である。以下製造方
法と共に説明する。
まず半導体基板１上にアルミをスパッタ後、パターニン
グし下層アルミ配線２を形成する。次で層間膜としてシ
リコン窒化膜３Ａをプラズマ成長させたのちアルミをス
パッタし、パターニングして上層アルミ配線４を形成す
る。次に、パッシベーション膜であるＰＳＧ膜５を気相
成長法により、次で、パッシベーション膜であるシリコ
ン窒化膜３Ｂをプラズマ成長法によりそれぞれ形成する
。次に、フォトレジスト塗布後、必要なアルミパッド部
のシリコン窒化膜３ＢとＰＳＧ膜５を除去できるように
パターニングされた露光用マスクを用いて露光・現像し
てマスクを形成し、プラスマエッチング法によりシリコ
ン窒化膜３ＢとＰＳＧ膜５を除去しアルミパッド６Ａ、
６Ｂを形成する。次でこのアルミパッド６Ａ、６Ｂにボ
ンディングワイヤ７Ａ、７Ｂをボンディングする。
このように本実施例によれは、ボンディングワイヤを接
続する部分にのみアルミパッドを形成するため、従来の
ように樹脂封止後、不必要なアルミパッドの腐食による
半導体装置の故障はなくなる。
〔発明の効果〕
以上説明したように本発明は、ワイヤホンディングを実
施しない部分にはアルミパッドを形成しないことにより
、今まで露出されたままであった不要のアルミバットが
、封止樹脂を浸透した水分の影響で腐食して故障の原因
となるという品質上の欠点をなくすことができるという
効果がある。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図である。 １・・・半導体基板、２・・・下層アルミ配線、３Ａ。 ３Ｂ・・・シリコン窒化膜、４・・上層アルミ配線、５
・・・ＰＳＧ膜、６Ａ、６Ｂ・・・アルミパッド、７Ａ
。 ７Ｂ・・・ボンディングワイヤ。 第１図

Claims (1)

    【特許請求の範囲】
  1. 　アルミ配線と一体的に形成されたアルミパッドを有す
    る半導体装置において、前記アルミパッドは全てボンデ
    ィングワイヤと接続されていることを特徴とする半導体
    装置。
JP2286173A 1990-10-24 1990-10-24 半導体装置 Pending JPH04162438A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2286173A JPH04162438A (ja) 1990-10-24 1990-10-24 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2286173A JPH04162438A (ja) 1990-10-24 1990-10-24 半導体装置

Publications (1)

Publication Number Publication Date
JPH04162438A true JPH04162438A (ja) 1992-06-05

Family

ID=17700890

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2286173A Pending JPH04162438A (ja) 1990-10-24 1990-10-24 半導体装置

Country Status (1)

Country Link
JP (1) JPH04162438A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268808B1 (ko) * 1997-12-31 2000-10-16 김영환 반도체소자의제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100268808B1 (ko) * 1997-12-31 2000-10-16 김영환 반도체소자의제조방법

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