JPS6178151A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6178151A
JPS6178151A JP59200225A JP20022584A JPS6178151A JP S6178151 A JPS6178151 A JP S6178151A JP 59200225 A JP59200225 A JP 59200225A JP 20022584 A JP20022584 A JP 20022584A JP S6178151 A JPS6178151 A JP S6178151A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor device
bonding pad
pad
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59200225A
Other languages
English (en)
Inventor
Yukio Tomita
富田　行雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59200225A priority Critical patent/JPS6178151A/ja
Priority to DE8585306788T priority patent/DE3574527D1/de
Priority to EP85306788A priority patent/EP0177251B1/en
Publication of JPS6178151A publication Critical patent/JPS6178151A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、多層配線半導体装置のボンディングパッドの
構造に関するものである。
（従来の技ｆ＃） 半導体素子、特に集積回路素子は、より高集積化するた
め、近年多層配線技術が多用されつつある。またこれに
よりボンディングパッドの構造も複雑になり、眉間絶縁
膜などの段差がパッド巧にあり、ボンディング工程時に
層間絶縁膜の破壊などが起り、問題となる。
（発明が解決しようとする問題点） そこで１本発明はボンディングパッド内での段差をなく
し、より信頼度の高いボンディングパッドの構造を提供
することにある。
（問題点を解決するための手段） 本発明では、スルーホールをボンディングパッド外周部
に設けることにより眉間絶縁膜による段差をボンディン
グパッド内に作らず平坦部でワ・イヤボンディング可能
な半導体装置を得る。
（作用） 本発明によれば、ボンディング部に眉間絶縁膜の段部が
存在しないので、ワイヤボンディング時の圧力で眉間絶
縁膜が破壊されることはなく、信頼性の高い半導体装置
を得ることができる。
第２図は従来のボンディングパッドの構造を示す。半導
体基板１の上に菰散層２、さらに絶縁層３があり、ボン
ディングパッドの＄ＩＡＩ電極４さらに層間絶縁膜５．
第２ＡＩ電極６がある。この構造のパッドにＡｕ線７に
てボンディングを行う。かかる構造では、ボンディング
時の機械的ひずみで層間絶ｌ！＆！ＩＸ５を破壊し、近
くを通る配線に影響をあたえる。
（実施例） 次に５図面を参照して本発明を説明する。
第１図は本発明の一実施例を示す。半導体基板１１、拡
散層１２．絶縁層１３は従来と同一構造であるが第１人
１電極１４を、パッド外周部に設けた層関絶Ｒ膜１５の
スルーホールにて第２Ａ１電極１６と接続しＡｕ線１７
にてボンディングを行う。この構造であれば、ワイヤボ
ンディング直下に（まほとんど段差はなくワイヤボンデ
ィング時にその圧力で層間絶縁膜１５が破壊されること
はないので高信頼度の半導体装置が得られる。
（発明の効果） 本発明によれば、ワイヤボンディング時に眉間絶縁膜が
破壊されることのない信頼度の高い半導体装置を得るこ
とができる。
【図面の簡単な説明】
第１図は本発明の一実施例によるボンディングパッド構
造を示す断面図、第２図は従来の多層配線技術における
ボンディングパッド構造を示す断面図である。 ｌ、１１・・・・・・半導体基板、２，１２・・・・・
・拡散層。 ３．１３・・・・・・絶縁層、４，１４・・・・・・第
１ＡＩ電極。 ５．１５・・・・・・層間絶縁膜、６，１６・・・・・
・第２ＡＩ電極、７，１７・・・・・・Ａｕ線。

Claims (1)

    【特許請求の範囲】
  1. 　半導体基板上に配線層とボンディングパッドとこれら
    の間に設置された層間絶縁膜とを有し、前記ボンディン
    グパッドは中央部の周囲で前記配線層と前記ボンディン
    グパッドとは前記層間絶縁膜のスルーホールを介して接
    続されていることを特徴とする半導体装置。
JP59200225A 1984-09-25 1984-09-25 半導体装置 Pending JPS6178151A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP59200225A JPS6178151A (ja) 1984-09-25 1984-09-25 半導体装置
DE8585306788T DE3574527D1 (de) 1984-09-25 1985-09-24 Halbleiterbauelement mit zuverlaessiger bondfleckenstruktur.
EP85306788A EP0177251B1 (en) 1984-09-25 1985-09-24 A semiconductor device having a reliable bonding pad structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59200225A JPS6178151A (ja) 1984-09-25 1984-09-25 半導体装置

Publications (1)

Publication Number Publication Date
JPS6178151A true JPS6178151A (ja) 1986-04-21

Family

ID=16420887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59200225A Pending JPS6178151A (ja) 1984-09-25 1984-09-25 半導体装置

Country Status (3)

Country Link
EP (1) EP0177251B1 (ja)
JP (1) JPS6178151A (ja)
DE (1) DE3574527D1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696406A (en) * 1993-10-29 1997-12-09 Nec Corportion Semiconductor device and method for fabricating the same
US5739587A (en) * 1995-02-21 1998-04-14 Seiko Epson Corporation Semiconductor device having a multi-latered wiring structure

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8902695A (nl) * 1989-11-01 1991-06-03 Philips Nv Interconnectiestructuur.
JP2616227B2 (ja) * 1990-11-24 1997-06-04 日本電気株式会社 半導体装置
US5309025A (en) * 1992-07-27 1994-05-03 Sgs-Thomson Microelectronics, Inc. Semiconductor bond pad structure and method
US6093894A (en) 1997-05-06 2000-07-25 International Business Machines Corporation Multiconductor bonded connection assembly with direct thermal compression bonding through a base layer
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
DE10333465B4 (de) * 2003-07-22 2008-07-24 Infineon Technologies Ag Elektronisches Bauteil mit Halbleiterchip, Verfahren zur Herstellung desselben sowie Verfahren zur Herstellung eines Halbleiterwafers mit Kontaktflecken
JP6806252B2 (ja) * 2017-07-13 2021-01-06 富士電機株式会社 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
JPS5421165A (en) * 1977-07-18 1979-02-17 Nec Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696406A (en) * 1993-10-29 1997-12-09 Nec Corportion Semiconductor device and method for fabricating the same
US5739587A (en) * 1995-02-21 1998-04-14 Seiko Epson Corporation Semiconductor device having a multi-latered wiring structure

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